|
| enum | IRQn_Type {
Reset_IRQn = -15
, NonMaskableInt_IRQn = -14
, HardFault_IRQn = -13
, MemoryManagement_IRQn = -12
,
BusFault_IRQn = -11
, UsageFault_IRQn = -10
, SVCall_IRQn = -5
, DebugMonitor_IRQn = -4
,
PendSV_IRQn = -2
, SysTick_IRQn = -1
, BROWNOUT_IRQn = 0
, WDT_IRQn = 1
,
RTC_IRQn = 2
, VCOMP_IRQn = 3
, IOSLAVE_IRQn = 4
, IOSLAVEACC_IRQn = 5
,
IOMSTR0_IRQn = 6
, IOMSTR1_IRQn = 7
, IOMSTR2_IRQn = 8
, IOMSTR3_IRQn = 9
,
IOMSTR4_IRQn = 10
, IOMSTR5_IRQn = 11
, IOMSTR6_IRQn = 12
, IOMSTR7_IRQn = 13
,
TIMER_IRQn = 14
, UART0_IRQn = 15
, UART1_IRQn = 16
, UART2_IRQn = 17
,
UART3_IRQn = 18
, ADC_IRQn = 19
, MSPI0_IRQn = 20
, MSPI1_IRQn = 21
,
MSPI2_IRQn = 22
, CLKGEN_IRQn = 23
, CRYPTOSEC_IRQn = 24
, SDIO_IRQn = 26
,
USB0_IRQn = 27
, GPU_IRQn = 28
, DC_IRQn = 29
, DSI_IRQn = 30
,
STIMER_CMPR0_IRQn = 32
, STIMER_CMPR1_IRQn = 33
, STIMER_CMPR2_IRQn = 34
, STIMER_CMPR3_IRQn = 35
,
STIMER_CMPR4_IRQn = 36
, STIMER_CMPR5_IRQn = 37
, STIMER_CMPR6_IRQn = 38
, STIMER_CMPR7_IRQn = 39
,
STIMER_OVF_IRQn = 40
, AUDADC0_IRQn = 42
, I2S0_IRQn = 44
, I2S1_IRQn = 45
,
PDM0_IRQn = 48
, PDM1_IRQn = 49
, PDM2_IRQn = 50
, PDM3_IRQn = 51
,
GPIO0_001F_IRQn = 56
, GPIO0_203F_IRQn = 57
, GPIO0_405F_IRQn = 58
, GPIO0_607F_IRQn = 59
,
GPIO1_001F_IRQn = 60
, GPIO1_203F_IRQn = 61
, GPIO1_405F_IRQn = 62
, GPIO1_607F_IRQn = 63
,
TIMER0_IRQn = 67
, TIMER1_IRQn = 68
, TIMER2_IRQn = 69
, TIMER3_IRQn = 70
,
TIMER4_IRQn = 71
, TIMER5_IRQn = 72
, TIMER6_IRQn = 73
, TIMER7_IRQn = 74
,
TIMER8_IRQn = 75
, TIMER9_IRQn = 76
, TIMER10_IRQn = 77
, TIMER11_IRQn = 78
,
TIMER12_IRQn = 79
, TIMER13_IRQn = 80
, TIMER14_IRQn = 81
, TIMER15_IRQn = 82
,
CACHE_IRQn = 83
, MAX_IRQn = 84
} |
| |
| enum | ADC_CFG_CLKSEL_Enum { ADC_CFG_CLKSEL_HFRC_48MHZ = 0
, ADC_CFG_CLKSEL_HFRC_48MHZ1 = 1
, ADC_CFG_CLKSEL_RESVD2 = 2
, ADC_CFG_CLKSEL_RESVD3 = 3
} |
| |
| enum | ADC_CFG_RPTTRIGSEL_Enum { ADC_CFG_RPTTRIGSEL_TMR = 0
, ADC_CFG_RPTTRIGSEL_INT = 1
} |
| |
| enum | ADC_CFG_TRIGPOL_Enum { ADC_CFG_TRIGPOL_RISING_EDGE = 0
, ADC_CFG_TRIGPOL_FALLING_EDGE = 1
} |
| |
| enum | ADC_CFG_TRIGSEL_Enum {
ADC_CFG_TRIGSEL_EXT0 = 0
, ADC_CFG_TRIGSEL_EXT1 = 1
, ADC_CFG_TRIGSEL_EXT2 = 2
, ADC_CFG_TRIGSEL_EXT3 = 3
,
ADC_CFG_TRIGSEL_VCOMP = 4
, ADC_CFG_TRIGSEL_SWT = 7
} |
| |
| enum | ADC_CFG_DFIFORDEN_Enum { ADC_CFG_DFIFORDEN_DIS = 0
, ADC_CFG_DFIFORDEN_EN = 1
} |
| |
| enum | ADC_CFG_CKMODE_Enum { ADC_CFG_CKMODE_LPCKMODE = 0
, ADC_CFG_CKMODE_LLCKMODE = 1
} |
| |
| enum | ADC_CFG_LPMODE_Enum { ADC_CFG_LPMODE_MODE0 = 0
, ADC_CFG_LPMODE_MODE1 = 1
} |
| |
| enum | ADC_CFG_RPTEN_Enum { ADC_CFG_RPTEN_SINGLE_SCAN = 0
, ADC_CFG_RPTEN_REPEATING_SCAN = 1
} |
| |
| enum | ADC_CFG_ADCEN_Enum { ADC_CFG_ADCEN_DIS = 0
, ADC_CFG_ADCEN_EN = 1
} |
| |
| enum | ADC_STAT_PWDSTAT_Enum { ADC_STAT_PWDSTAT_ON = 0
, ADC_STAT_PWDSTAT_POWERED_DOWN = 1
} |
| |
| enum | ADC_SWT_SWT_Enum { ADC_SWT_SWT_GEN_SW_TRIGGER = 55
, ADC_SWT_SWT_NO_SW_TRIGGER = 0
} |
| |
| enum | ADC_SL0CFG_ADSEL0_Enum {
ADC_SL0CFG_ADSEL0_AVG_1_MSRMT = 0
, ADC_SL0CFG_ADSEL0_AVG_2_MSRMTS = 1
, ADC_SL0CFG_ADSEL0_AVG_4_MSRMTS = 2
, ADC_SL0CFG_ADSEL0_AVG_8_MSRMT = 3
,
ADC_SL0CFG_ADSEL0_AVG_16_MSRMTS = 4
, ADC_SL0CFG_ADSEL0_AVG_32_MSRMTS = 5
, ADC_SL0CFG_ADSEL0_AVG_64_MSRMTS = 6
, ADC_SL0CFG_ADSEL0_AVG_128_MSRMTS = 7
} |
| |
| enum | ADC_SL0CFG_PRMODE0_Enum { ADC_SL0CFG_PRMODE0_P12B0 = 0
, ADC_SL0CFG_PRMODE0_P12B1 = 1
, ADC_SL0CFG_PRMODE0_P10B = 2
, ADC_SL0CFG_PRMODE0_P8B = 3
} |
| |
| enum | ADC_SL0CFG_CHSEL0_Enum {
ADC_SL0CFG_CHSEL0_SE0 = 0
, ADC_SL0CFG_CHSEL0_SE1 = 1
, ADC_SL0CFG_CHSEL0_SE2 = 2
, ADC_SL0CFG_CHSEL0_SE3 = 3
,
ADC_SL0CFG_CHSEL0_SE4 = 4
, ADC_SL0CFG_CHSEL0_SE5 = 5
, ADC_SL0CFG_CHSEL0_SE6 = 6
, ADC_SL0CFG_CHSEL0_SE7 = 7
,
ADC_SL0CFG_CHSEL0_TEMP = 8
, ADC_SL0CFG_CHSEL0_BATT = 9
, ADC_SL0CFG_CHSEL0_TESTMUX = 10
, ADC_SL0CFG_CHSEL0_VSS = 11
} |
| |
| enum | ADC_SL0CFG_WCEN0_Enum { ADC_SL0CFG_WCEN0_WCEN = 1
, ADC_SL0CFG_WCEN0_WCDIS = 0
} |
| |
| enum | ADC_SL0CFG_SLEN0_Enum { ADC_SL0CFG_SLEN0_SLEN = 1
, ADC_SL0CFG_SLEN0_SLDIS = 0
} |
| |
| enum | ADC_SL1CFG_ADSEL1_Enum {
ADC_SL1CFG_ADSEL1_AVG_1_MSRMT = 0
, ADC_SL1CFG_ADSEL1_AVG_2_MSRMTS = 1
, ADC_SL1CFG_ADSEL1_AVG_4_MSRMTS = 2
, ADC_SL1CFG_ADSEL1_AVG_8_MSRMT = 3
,
ADC_SL1CFG_ADSEL1_AVG_16_MSRMTS = 4
, ADC_SL1CFG_ADSEL1_AVG_32_MSRMTS = 5
, ADC_SL1CFG_ADSEL1_AVG_64_MSRMTS = 6
, ADC_SL1CFG_ADSEL1_AVG_128_MSRMTS = 7
} |
| |
| enum | ADC_SL1CFG_PRMODE1_Enum { ADC_SL1CFG_PRMODE1_P12B0 = 0
, ADC_SL1CFG_PRMODE1_P12B1 = 1
, ADC_SL1CFG_PRMODE1_P10B = 2
, ADC_SL1CFG_PRMODE1_P8B = 3
} |
| |
| enum | ADC_SL1CFG_CHSEL1_Enum {
ADC_SL1CFG_CHSEL1_SE0 = 0
, ADC_SL1CFG_CHSEL1_SE1 = 1
, ADC_SL1CFG_CHSEL1_SE2 = 2
, ADC_SL1CFG_CHSEL1_SE3 = 3
,
ADC_SL1CFG_CHSEL1_SE4 = 4
, ADC_SL1CFG_CHSEL1_SE5 = 5
, ADC_SL1CFG_CHSEL1_SE6 = 6
, ADC_SL1CFG_CHSEL1_SE7 = 7
,
ADC_SL1CFG_CHSEL1_TEMP = 8
, ADC_SL1CFG_CHSEL1_BATT = 9
, ADC_SL1CFG_CHSEL1_TESTMUX = 10
, ADC_SL1CFG_CHSEL1_VSS = 11
} |
| |
| enum | ADC_SL1CFG_WCEN1_Enum { ADC_SL1CFG_WCEN1_WCEN = 1
, ADC_SL1CFG_WCEN1_WCDIS = 0
} |
| |
| enum | ADC_SL1CFG_SLEN1_Enum { ADC_SL1CFG_SLEN1_SLEN = 1
, ADC_SL1CFG_SLEN1_SLDIS = 0
} |
| |
| enum | ADC_SL2CFG_ADSEL2_Enum {
ADC_SL2CFG_ADSEL2_AVG_1_MSRMT = 0
, ADC_SL2CFG_ADSEL2_AVG_2_MSRMTS = 1
, ADC_SL2CFG_ADSEL2_AVG_4_MSRMTS = 2
, ADC_SL2CFG_ADSEL2_AVG_8_MSRMT = 3
,
ADC_SL2CFG_ADSEL2_AVG_16_MSRMTS = 4
, ADC_SL2CFG_ADSEL2_AVG_32_MSRMTS = 5
, ADC_SL2CFG_ADSEL2_AVG_64_MSRMTS = 6
, ADC_SL2CFG_ADSEL2_AVG_128_MSRMTS = 7
} |
| |
| enum | ADC_SL2CFG_PRMODE2_Enum { ADC_SL2CFG_PRMODE2_P12B0 = 0
, ADC_SL2CFG_PRMODE2_P12B1 = 1
, ADC_SL2CFG_PRMODE2_P10B = 2
, ADC_SL2CFG_PRMODE2_P8B = 3
} |
| |
| enum | ADC_SL2CFG_CHSEL2_Enum {
ADC_SL2CFG_CHSEL2_SE0 = 0
, ADC_SL2CFG_CHSEL2_SE1 = 1
, ADC_SL2CFG_CHSEL2_SE2 = 2
, ADC_SL2CFG_CHSEL2_SE3 = 3
,
ADC_SL2CFG_CHSEL2_SE4 = 4
, ADC_SL2CFG_CHSEL2_SE5 = 5
, ADC_SL2CFG_CHSEL2_SE6 = 6
, ADC_SL2CFG_CHSEL2_SE7 = 7
,
ADC_SL2CFG_CHSEL2_TEMP = 8
, ADC_SL2CFG_CHSEL2_BATT = 9
, ADC_SL2CFG_CHSEL2_TESTMUX = 10
, ADC_SL2CFG_CHSEL2_VSS = 11
} |
| |
| enum | ADC_SL2CFG_WCEN2_Enum { ADC_SL2CFG_WCEN2_WCEN = 1
, ADC_SL2CFG_WCEN2_WCDIS = 0
} |
| |
| enum | ADC_SL2CFG_SLEN2_Enum { ADC_SL2CFG_SLEN2_SLEN = 1
, ADC_SL2CFG_SLEN2_SLDIS = 0
} |
| |
| enum | ADC_SL3CFG_ADSEL3_Enum {
ADC_SL3CFG_ADSEL3_AVG_1_MSRMT = 0
, ADC_SL3CFG_ADSEL3_AVG_2_MSRMTS = 1
, ADC_SL3CFG_ADSEL3_AVG_4_MSRMTS = 2
, ADC_SL3CFG_ADSEL3_AVG_8_MSRMT = 3
,
ADC_SL3CFG_ADSEL3_AVG_16_MSRMTS = 4
, ADC_SL3CFG_ADSEL3_AVG_32_MSRMTS = 5
, ADC_SL3CFG_ADSEL3_AVG_64_MSRMTS = 6
, ADC_SL3CFG_ADSEL3_AVG_128_MSRMTS = 7
} |
| |
| enum | ADC_SL3CFG_PRMODE3_Enum { ADC_SL3CFG_PRMODE3_P12B0 = 0
, ADC_SL3CFG_PRMODE3_P12B1 = 1
, ADC_SL3CFG_PRMODE3_P10B = 2
, ADC_SL3CFG_PRMODE3_P8B = 3
} |
| |
| enum | ADC_SL3CFG_CHSEL3_Enum {
ADC_SL3CFG_CHSEL3_SE0 = 0
, ADC_SL3CFG_CHSEL3_SE1 = 1
, ADC_SL3CFG_CHSEL3_SE2 = 2
, ADC_SL3CFG_CHSEL3_SE3 = 3
,
ADC_SL3CFG_CHSEL3_SE4 = 4
, ADC_SL3CFG_CHSEL3_SE5 = 5
, ADC_SL3CFG_CHSEL3_SE6 = 6
, ADC_SL3CFG_CHSEL3_SE7 = 7
,
ADC_SL3CFG_CHSEL3_TEMP = 8
, ADC_SL3CFG_CHSEL3_BATT = 9
, ADC_SL3CFG_CHSEL3_TESTMUX = 10
, ADC_SL3CFG_CHSEL3_VSS = 11
} |
| |
| enum | ADC_SL3CFG_WCEN3_Enum { ADC_SL3CFG_WCEN3_WCEN = 1
, ADC_SL3CFG_WCEN3_WCDIS = 0
} |
| |
| enum | ADC_SL3CFG_SLEN3_Enum { ADC_SL3CFG_SLEN3_SLEN = 1
, ADC_SL3CFG_SLEN3_SLDIS = 0
} |
| |
| enum | ADC_SL4CFG_ADSEL4_Enum {
ADC_SL4CFG_ADSEL4_AVG_1_MSRMT = 0
, ADC_SL4CFG_ADSEL4_AVG_2_MSRMTS = 1
, ADC_SL4CFG_ADSEL4_AVG_4_MSRMTS = 2
, ADC_SL4CFG_ADSEL4_AVG_8_MSRMT = 3
,
ADC_SL4CFG_ADSEL4_AVG_16_MSRMTS = 4
, ADC_SL4CFG_ADSEL4_AVG_32_MSRMTS = 5
, ADC_SL4CFG_ADSEL4_AVG_64_MSRMTS = 6
, ADC_SL4CFG_ADSEL4_AVG_128_MSRMTS = 7
} |
| |
| enum | ADC_SL4CFG_PRMODE4_Enum { ADC_SL4CFG_PRMODE4_P12B0 = 0
, ADC_SL4CFG_PRMODE4_P12B1 = 1
, ADC_SL4CFG_PRMODE4_P10B = 2
, ADC_SL4CFG_PRMODE4_P8B = 3
} |
| |
| enum | ADC_SL4CFG_CHSEL4_Enum {
ADC_SL4CFG_CHSEL4_SE0 = 0
, ADC_SL4CFG_CHSEL4_SE1 = 1
, ADC_SL4CFG_CHSEL4_SE2 = 2
, ADC_SL4CFG_CHSEL4_SE3 = 3
,
ADC_SL4CFG_CHSEL4_SE4 = 4
, ADC_SL4CFG_CHSEL4_SE5 = 5
, ADC_SL4CFG_CHSEL4_SE6 = 6
, ADC_SL4CFG_CHSEL4_SE7 = 7
,
ADC_SL4CFG_CHSEL4_TEMP = 8
, ADC_SL4CFG_CHSEL4_BATT = 9
, ADC_SL4CFG_CHSEL4_TESTMUX = 10
, ADC_SL4CFG_CHSEL4_VSS = 11
} |
| |
| enum | ADC_SL4CFG_WCEN4_Enum { ADC_SL4CFG_WCEN4_WCEN = 1
, ADC_SL4CFG_WCEN4_WCDIS = 0
} |
| |
| enum | ADC_SL4CFG_SLEN4_Enum { ADC_SL4CFG_SLEN4_SLEN = 1
, ADC_SL4CFG_SLEN4_SLDIS = 0
} |
| |
| enum | ADC_SL5CFG_ADSEL5_Enum {
ADC_SL5CFG_ADSEL5_AVG_1_MSRMT = 0
, ADC_SL5CFG_ADSEL5_AVG_2_MSRMTS = 1
, ADC_SL5CFG_ADSEL5_AVG_4_MSRMTS = 2
, ADC_SL5CFG_ADSEL5_AVG_8_MSRMT = 3
,
ADC_SL5CFG_ADSEL5_AVG_16_MSRMTS = 4
, ADC_SL5CFG_ADSEL5_AVG_32_MSRMTS = 5
, ADC_SL5CFG_ADSEL5_AVG_64_MSRMTS = 6
, ADC_SL5CFG_ADSEL5_AVG_128_MSRMTS = 7
} |
| |
| enum | ADC_SL5CFG_PRMODE5_Enum { ADC_SL5CFG_PRMODE5_P12B0 = 0
, ADC_SL5CFG_PRMODE5_P12B1 = 1
, ADC_SL5CFG_PRMODE5_P10B = 2
, ADC_SL5CFG_PRMODE5_P8B = 3
} |
| |
| enum | ADC_SL5CFG_CHSEL5_Enum {
ADC_SL5CFG_CHSEL5_SE0 = 0
, ADC_SL5CFG_CHSEL5_SE1 = 1
, ADC_SL5CFG_CHSEL5_SE2 = 2
, ADC_SL5CFG_CHSEL5_SE3 = 3
,
ADC_SL5CFG_CHSEL5_SE4 = 4
, ADC_SL5CFG_CHSEL5_SE5 = 5
, ADC_SL5CFG_CHSEL5_SE6 = 6
, ADC_SL5CFG_CHSEL5_SE7 = 7
,
ADC_SL5CFG_CHSEL5_TEMP = 8
, ADC_SL5CFG_CHSEL5_BATT = 9
, ADC_SL5CFG_CHSEL5_TESTMUX = 10
, ADC_SL5CFG_CHSEL5_VSS = 11
} |
| |
| enum | ADC_SL5CFG_WCEN5_Enum { ADC_SL5CFG_WCEN5_WCEN = 1
, ADC_SL5CFG_WCEN5_WCDIS = 0
} |
| |
| enum | ADC_SL5CFG_SLEN5_Enum { ADC_SL5CFG_SLEN5_SLEN = 1
, ADC_SL5CFG_SLEN5_SLDIS = 0
} |
| |
| enum | ADC_SL6CFG_ADSEL6_Enum {
ADC_SL6CFG_ADSEL6_AVG_1_MSRMT = 0
, ADC_SL6CFG_ADSEL6_AVG_2_MSRMTS = 1
, ADC_SL6CFG_ADSEL6_AVG_4_MSRMTS = 2
, ADC_SL6CFG_ADSEL6_AVG_8_MSRMT = 3
,
ADC_SL6CFG_ADSEL6_AVG_16_MSRMTS = 4
, ADC_SL6CFG_ADSEL6_AVG_32_MSRMTS = 5
, ADC_SL6CFG_ADSEL6_AVG_64_MSRMTS = 6
, ADC_SL6CFG_ADSEL6_AVG_128_MSRMTS = 7
} |
| |
| enum | ADC_SL6CFG_PRMODE6_Enum { ADC_SL6CFG_PRMODE6_P12B0 = 0
, ADC_SL6CFG_PRMODE6_P12B1 = 1
, ADC_SL6CFG_PRMODE6_P10B = 2
, ADC_SL6CFG_PRMODE6_P8B = 3
} |
| |
| enum | ADC_SL6CFG_CHSEL6_Enum {
ADC_SL6CFG_CHSEL6_SE0 = 0
, ADC_SL6CFG_CHSEL6_SE1 = 1
, ADC_SL6CFG_CHSEL6_SE2 = 2
, ADC_SL6CFG_CHSEL6_SE3 = 3
,
ADC_SL6CFG_CHSEL6_SE4 = 4
, ADC_SL6CFG_CHSEL6_SE5 = 5
, ADC_SL6CFG_CHSEL6_SE6 = 6
, ADC_SL6CFG_CHSEL6_SE7 = 7
,
ADC_SL6CFG_CHSEL6_TEMP = 8
, ADC_SL6CFG_CHSEL6_BATT = 9
, ADC_SL6CFG_CHSEL6_TESTMUX = 10
, ADC_SL6CFG_CHSEL6_VSS = 11
} |
| |
| enum | ADC_SL6CFG_WCEN6_Enum { ADC_SL6CFG_WCEN6_WCEN = 1
, ADC_SL6CFG_WCEN6_WCDIS = 0
} |
| |
| enum | ADC_SL6CFG_SLEN6_Enum { ADC_SL6CFG_SLEN6_SLEN = 1
, ADC_SL6CFG_SLEN6_SLDIS = 0
} |
| |
| enum | ADC_SL7CFG_ADSEL7_Enum {
ADC_SL7CFG_ADSEL7_AVG_1_MSRMT = 0
, ADC_SL7CFG_ADSEL7_AVG_2_MSRMTS = 1
, ADC_SL7CFG_ADSEL7_AVG_4_MSRMTS = 2
, ADC_SL7CFG_ADSEL7_AVG_8_MSRMT = 3
,
ADC_SL7CFG_ADSEL7_AVG_16_MSRMTS = 4
, ADC_SL7CFG_ADSEL7_AVG_32_MSRMTS = 5
, ADC_SL7CFG_ADSEL7_AVG_64_MSRMTS = 6
, ADC_SL7CFG_ADSEL7_AVG_128_MSRMTS = 7
} |
| |
| enum | ADC_SL7CFG_PRMODE7_Enum { ADC_SL7CFG_PRMODE7_P12B0 = 0
, ADC_SL7CFG_PRMODE7_P12B1 = 1
, ADC_SL7CFG_PRMODE7_P10B = 2
, ADC_SL7CFG_PRMODE7_P8B = 3
} |
| |
| enum | ADC_SL7CFG_CHSEL7_Enum {
ADC_SL7CFG_CHSEL7_SE0 = 0
, ADC_SL7CFG_CHSEL7_SE1 = 1
, ADC_SL7CFG_CHSEL7_SE2 = 2
, ADC_SL7CFG_CHSEL7_SE3 = 3
,
ADC_SL7CFG_CHSEL7_SE4 = 4
, ADC_SL7CFG_CHSEL7_SE5 = 5
, ADC_SL7CFG_CHSEL7_SE6 = 6
, ADC_SL7CFG_CHSEL7_SE7 = 7
,
ADC_SL7CFG_CHSEL7_TEMP = 8
, ADC_SL7CFG_CHSEL7_BATT = 9
, ADC_SL7CFG_CHSEL7_TESTMUX = 10
, ADC_SL7CFG_CHSEL7_VSS = 11
} |
| |
| enum | ADC_SL7CFG_WCEN7_Enum { ADC_SL7CFG_WCEN7_WCEN = 1
, ADC_SL7CFG_WCEN7_WCDIS = 0
} |
| |
| enum | ADC_SL7CFG_SLEN7_Enum { ADC_SL7CFG_SLEN7_SLEN = 1
, ADC_SL7CFG_SLEN7_SLDIS = 0
} |
| |
| enum | ADC_INTTRIGTIMER_TIMEREN_Enum { ADC_INTTRIGTIMER_TIMEREN_DIS = 0
, ADC_INTTRIGTIMER_TIMEREN_EN = 1
} |
| |
| enum | ADC_GAINCFG_UPDATEMODE_Enum { ADC_GAINCFG_UPDATEMODE_IMMED = 0
, ADC_GAINCFG_UPDATEMODE_ZX = 1
} |
| |
| enum | ADC_INTEN_SATCB_Enum { ADC_INTEN_SATCB_SATCBINT = 1
, ADC_INTEN_SATCB_NONSATCBINT = 0
} |
| |
| enum | ADC_INTEN_SATCA_Enum { ADC_INTEN_SATCA_SATCAINT = 1
, ADC_INTEN_SATCA_NONSATCAINT = 0
} |
| |
| enum | ADC_INTEN_ZXCB_Enum { ADC_INTEN_ZXCB_ZXCBINT = 1
, ADC_INTEN_ZXCB_NONZXCBINT = 0
} |
| |
| enum | ADC_INTEN_ZXCA_Enum { ADC_INTEN_ZXCA_ZXCAINT = 1
, ADC_INTEN_ZXCA_NONZXCAINT = 0
} |
| |
| enum | ADC_INTEN_DERR_Enum { ADC_INTEN_DERR_DMAERROR = 1
, ADC_INTEN_DERR_NODMAERROR = 0
} |
| |
| enum | ADC_INTEN_DCMP_Enum { ADC_INTEN_DCMP_DMACOMPLETE = 1
, ADC_INTEN_DCMP_DMAON = 0
} |
| |
| enum | ADC_INTEN_WCINC_Enum { ADC_INTEN_WCINC_WCINCINT = 1
, ADC_INTEN_WCINC_WCINCNOINT = 0
} |
| |
| enum | ADC_INTEN_WCEXC_Enum { ADC_INTEN_WCEXC_WCEXCINT = 1
, ADC_INTEN_WCEXC_WCEXCNOINT = 0
} |
| |
| enum | ADC_INTEN_FIFOOVR2_Enum { ADC_INTEN_FIFOOVR2_FIFOFULLINT = 1
, ADC_INTEN_FIFOOVR2_FIFOFULLNOINT = 0
} |
| |
| enum | ADC_INTEN_FIFOOVR1_Enum { ADC_INTEN_FIFOOVR1_FIFO75INT = 1
, ADC_INTEN_FIFOOVR1_FIFO75NOINT = 0
} |
| |
| enum | ADC_INTEN_SCNCMP_Enum { ADC_INTEN_SCNCMP_SCNCMPINT = 1
, ADC_INTEN_SCNCMP_SCNCMPNOINT = 0
} |
| |
| enum | ADC_INTEN_CNVCMP_Enum { ADC_INTEN_CNVCMP_CNVCMPINT = 1
, ADC_INTEN_CNVCMP_CNVCMPNOINT = 0
} |
| |
| enum | ADC_INTSTAT_SATCB_Enum { ADC_INTSTAT_SATCB_SATCBINT = 1
, ADC_INTSTAT_SATCB_NONSATCBINT = 0
} |
| |
| enum | ADC_INTSTAT_SATCA_Enum { ADC_INTSTAT_SATCA_SATCAINT = 1
, ADC_INTSTAT_SATCA_NONSATCAINT = 0
} |
| |
| enum | ADC_INTSTAT_ZXCB_Enum { ADC_INTSTAT_ZXCB_ZXCBINT = 1
, ADC_INTSTAT_ZXCB_NONZXCBINT = 0
} |
| |
| enum | ADC_INTSTAT_ZXCA_Enum { ADC_INTSTAT_ZXCA_ZXCAINT = 1
, ADC_INTSTAT_ZXCA_NONZXCAINT = 0
} |
| |
| enum | ADC_INTSTAT_DERR_Enum { ADC_INTSTAT_DERR_DMAERROR = 1
, ADC_INTSTAT_DERR_NODMAERROR = 0
} |
| |
| enum | ADC_INTSTAT_DCMP_Enum { ADC_INTSTAT_DCMP_DMACOMPLETE = 1
, ADC_INTSTAT_DCMP_DMAON = 0
} |
| |
| enum | ADC_INTSTAT_WCINC_Enum { ADC_INTSTAT_WCINC_WCINCINT = 1
, ADC_INTSTAT_WCINC_WCINCNOINT = 0
} |
| |
| enum | ADC_INTSTAT_WCEXC_Enum { ADC_INTSTAT_WCEXC_WCEXCINT = 1
, ADC_INTSTAT_WCEXC_WCEXCNOINT = 0
} |
| |
| enum | ADC_INTSTAT_FIFOOVR2_Enum { ADC_INTSTAT_FIFOOVR2_FIFOFULLINT = 1
, ADC_INTSTAT_FIFOOVR2_FIFOFULLNOINT = 0
} |
| |
| enum | ADC_INTSTAT_FIFOOVR1_Enum { ADC_INTSTAT_FIFOOVR1_FIFO75INT = 1
, ADC_INTSTAT_FIFOOVR1_FIFO75NOINT = 0
} |
| |
| enum | ADC_INTSTAT_SCNCMP_Enum { ADC_INTSTAT_SCNCMP_SCNCMPINT = 1
, ADC_INTSTAT_SCNCMP_SCNCMPNOINT = 0
} |
| |
| enum | ADC_INTSTAT_CNVCMP_Enum { ADC_INTSTAT_CNVCMP_CNVCMPINT = 1
, ADC_INTSTAT_CNVCMP_CNVCMPNOINT = 0
} |
| |
| enum | ADC_INTCLR_SATCB_Enum { ADC_INTCLR_SATCB_SATCBINT = 1
, ADC_INTCLR_SATCB_NONSATCBINT = 0
} |
| |
| enum | ADC_INTCLR_SATCA_Enum { ADC_INTCLR_SATCA_SATCAINT = 1
, ADC_INTCLR_SATCA_NONSATCAINT = 0
} |
| |
| enum | ADC_INTCLR_ZXCB_Enum { ADC_INTCLR_ZXCB_ZXCBINT = 1
, ADC_INTCLR_ZXCB_NONZXCBINT = 0
} |
| |
| enum | ADC_INTCLR_ZXCA_Enum { ADC_INTCLR_ZXCA_ZXCAINT = 1
, ADC_INTCLR_ZXCA_NONZXCAINT = 0
} |
| |
| enum | ADC_INTCLR_DERR_Enum { ADC_INTCLR_DERR_DMAERROR = 1
, ADC_INTCLR_DERR_NODMAERROR = 0
} |
| |
| enum | ADC_INTCLR_DCMP_Enum { ADC_INTCLR_DCMP_DMACOMPLETE = 1
, ADC_INTCLR_DCMP_DMAON = 0
} |
| |
| enum | ADC_INTCLR_WCINC_Enum { ADC_INTCLR_WCINC_WCINCINT = 1
, ADC_INTCLR_WCINC_WCINCNOINT = 0
} |
| |
| enum | ADC_INTCLR_WCEXC_Enum { ADC_INTCLR_WCEXC_WCEXCINT = 1
, ADC_INTCLR_WCEXC_WCEXCNOINT = 0
} |
| |
| enum | ADC_INTCLR_FIFOOVR2_Enum { ADC_INTCLR_FIFOOVR2_FIFOFULLINT = 1
, ADC_INTCLR_FIFOOVR2_FIFOFULLNOINT = 0
} |
| |
| enum | ADC_INTCLR_FIFOOVR1_Enum { ADC_INTCLR_FIFOOVR1_FIFO75INT = 1
, ADC_INTCLR_FIFOOVR1_FIFO75NOINT = 0
} |
| |
| enum | ADC_INTCLR_SCNCMP_Enum { ADC_INTCLR_SCNCMP_SCNCMPINT = 1
, ADC_INTCLR_SCNCMP_SCNCMPNOINT = 0
} |
| |
| enum | ADC_INTCLR_CNVCMP_Enum { ADC_INTCLR_CNVCMP_CNVCMPINT = 1
, ADC_INTCLR_CNVCMP_CNVCMPNOINT = 0
} |
| |
| enum | ADC_INTSET_SATCB_Enum { ADC_INTSET_SATCB_SATCBINT = 1
, ADC_INTSET_SATCB_NONSATCBINT = 0
} |
| |
| enum | ADC_INTSET_SATCA_Enum { ADC_INTSET_SATCA_SATCAINT = 1
, ADC_INTSET_SATCA_NONSATCAINT = 0
} |
| |
| enum | ADC_INTSET_ZXCB_Enum { ADC_INTSET_ZXCB_ZXCBINT = 1
, ADC_INTSET_ZXCB_NONZXCBINT = 0
} |
| |
| enum | ADC_INTSET_ZXCA_Enum { ADC_INTSET_ZXCA_ZXCAINT = 1
, ADC_INTSET_ZXCA_NONZXCAINT = 0
} |
| |
| enum | ADC_INTSET_DERR_Enum { ADC_INTSET_DERR_DMAERROR = 1
, ADC_INTSET_DERR_NODMAERROR = 0
} |
| |
| enum | ADC_INTSET_DCMP_Enum { ADC_INTSET_DCMP_DMACOMPLETE = 1
, ADC_INTSET_DCMP_DMAON = 0
} |
| |
| enum | ADC_INTSET_WCINC_Enum { ADC_INTSET_WCINC_WCINCINT = 1
, ADC_INTSET_WCINC_WCINCNOINT = 0
} |
| |
| enum | ADC_INTSET_WCEXC_Enum { ADC_INTSET_WCEXC_WCEXCINT = 1
, ADC_INTSET_WCEXC_WCEXCNOINT = 0
} |
| |
| enum | ADC_INTSET_FIFOOVR2_Enum { ADC_INTSET_FIFOOVR2_FIFOFULLINT = 1
, ADC_INTSET_FIFOOVR2_FIFOFULLNOINT = 0
} |
| |
| enum | ADC_INTSET_FIFOOVR1_Enum { ADC_INTSET_FIFOOVR1_FIFO75INT = 1
, ADC_INTSET_FIFOOVR1_FIFO75NOINT = 0
} |
| |
| enum | ADC_INTSET_SCNCMP_Enum { ADC_INTSET_SCNCMP_SCNCMPINT = 1
, ADC_INTSET_SCNCMP_SCNCMPNOINT = 0
} |
| |
| enum | ADC_INTSET_CNVCMP_Enum { ADC_INTSET_CNVCMP_CNVCMPINT = 1
, ADC_INTSET_CNVCMP_CNVCMPNOINT = 0
} |
| |
| enum | ADC_DMACFG_DMAMSK_Enum { ADC_DMACFG_DMAMSK_DIS = 0
, ADC_DMACFG_DMAMSK_EN = 1
} |
| |
| enum | ADC_DMACFG_DMADYNPRI_Enum { ADC_DMACFG_DMADYNPRI_DIS = 0
, ADC_DMACFG_DMADYNPRI_EN = 1
} |
| |
| enum | ADC_DMACFG_DMAPRI_Enum { ADC_DMACFG_DMAPRI_LOW = 0
, ADC_DMACFG_DMAPRI_HIGH = 1
} |
| |
| enum | ADC_DMACFG_DMADIR_Enum { ADC_DMACFG_DMADIR_P2M = 0
, ADC_DMACFG_DMADIR_M2P = 1
} |
| |
| enum | ADC_DMACFG_DMAEN_Enum { ADC_DMACFG_DMAEN_DIS = 0
, ADC_DMACFG_DMAEN_EN = 1
} |
| |
| enum | APBDMA_DEBUG_DEBUGEN_Enum { APBDMA_DEBUG_DEBUGEN_OFF = 0
, APBDMA_DEBUG_DEBUGEN_ARB = 1
} |
| |
| enum | AUDADC_CFG_CLKSEL_Enum { AUDADC_CFG_CLKSEL_OFF = 0
, AUDADC_CFG_CLKSEL_HFRC_48MHz = 1
, AUDADC_CFG_CLKSEL_XTALHS_24MHz = 2
, AUDADC_CFG_CLKSEL_HFRC2_48MHz = 3
} |
| |
| enum | AUDADC_CFG_RPTTRIGSEL_Enum { AUDADC_CFG_RPTTRIGSEL_TMR = 0
, AUDADC_CFG_RPTTRIGSEL_INT = 1
} |
| |
| enum | AUDADC_CFG_TRIGPOL_Enum { AUDADC_CFG_TRIGPOL_RISING_EDGE = 0
, AUDADC_CFG_TRIGPOL_FALLING_EDGE = 1
} |
| |
| enum | AUDADC_CFG_TRIGSEL_Enum {
AUDADC_CFG_TRIGSEL_EXT0 = 0
, AUDADC_CFG_TRIGSEL_EXT1 = 1
, AUDADC_CFG_TRIGSEL_EXT2 = 2
, AUDADC_CFG_TRIGSEL_EXT3 = 3
,
AUDADC_CFG_TRIGSEL_VCOMP = 4
, AUDADC_CFG_TRIGSEL_SWT = 7
} |
| |
| enum | AUDADC_CFG_SAMPMODE_Enum { AUDADC_CFG_SAMPMODE_LP = 0
, AUDADC_CFG_SAMPMODE_MED = 1
} |
| |
| enum | AUDADC_CFG_DFIFORDEN_Enum { AUDADC_CFG_DFIFORDEN_DIS = 0
, AUDADC_CFG_DFIFORDEN_EN = 1
} |
| |
| enum | AUDADC_CFG_CKMODE_Enum { AUDADC_CFG_CKMODE_LPCKMODE = 0
, AUDADC_CFG_CKMODE_LLCKMODE = 1
} |
| |
| enum | AUDADC_CFG_LPMODE_Enum { AUDADC_CFG_LPMODE_MODE0 = 0
, AUDADC_CFG_LPMODE_MODE1 = 1
} |
| |
| enum | AUDADC_CFG_RPTEN_Enum { AUDADC_CFG_RPTEN_SINGLE_SCAN = 0
, AUDADC_CFG_RPTEN_REPEATING_SCAN = 1
} |
| |
| enum | AUDADC_CFG_ADCEN_Enum { AUDADC_CFG_ADCEN_DIS = 0
, AUDADC_CFG_ADCEN_EN = 1
} |
| |
| enum | AUDADC_STAT_PWDSTAT_Enum { AUDADC_STAT_PWDSTAT_ON = 0
, AUDADC_STAT_PWDSTAT_POWERED_DOWN = 1
} |
| |
| enum | AUDADC_SWT_SWT_Enum { AUDADC_SWT_SWT_GEN_SW_TRIGGER = 55
, AUDADC_SWT_SWT_NO_SW_TRIGGER = 0
} |
| |
| enum | AUDADC_SL0CFG_ADSEL0_Enum {
AUDADC_SL0CFG_ADSEL0_AVG_1_MSRMT = 0
, AUDADC_SL0CFG_ADSEL0_AVG_2_MSRMTS = 1
, AUDADC_SL0CFG_ADSEL0_AVG_4_MSRMTS = 2
, AUDADC_SL0CFG_ADSEL0_AVG_8_MSRMT = 3
,
AUDADC_SL0CFG_ADSEL0_AVG_16_MSRMTS = 4
, AUDADC_SL0CFG_ADSEL0_AVG_32_MSRMTS = 5
, AUDADC_SL0CFG_ADSEL0_AVG_64_MSRMTS = 6
, AUDADC_SL0CFG_ADSEL0_AVG_128_MSRMTS = 7
} |
| |
| enum | AUDADC_SL0CFG_PRMODE0_Enum { AUDADC_SL0CFG_PRMODE0_P12B0 = 0
, AUDADC_SL0CFG_PRMODE0_P12B1 = 1
, AUDADC_SL0CFG_PRMODE0_P10B = 2
, AUDADC_SL0CFG_PRMODE0_P8B = 3
} |
| |
| enum | AUDADC_SL0CFG_CHSEL0_Enum { AUDADC_SL0CFG_CHSEL0_SE0 = 0
, AUDADC_SL0CFG_CHSEL0_SE1 = 1
, AUDADC_SL0CFG_CHSEL0_SE2 = 2
, AUDADC_SL0CFG_CHSEL0_SE3 = 3
} |
| |
| enum | AUDADC_SL0CFG_WCEN0_Enum { AUDADC_SL0CFG_WCEN0_WCEN = 1
, AUDADC_SL0CFG_WCEN0_WCDIS = 0
} |
| |
| enum | AUDADC_SL0CFG_SLEN0_Enum { AUDADC_SL0CFG_SLEN0_SLEN = 1
, AUDADC_SL0CFG_SLEN0_SLDIS = 0
} |
| |
| enum | AUDADC_SL1CFG_ADSEL1_Enum {
AUDADC_SL1CFG_ADSEL1_AVG_1_MSRMT = 0
, AUDADC_SL1CFG_ADSEL1_AVG_2_MSRMTS = 1
, AUDADC_SL1CFG_ADSEL1_AVG_4_MSRMTS = 2
, AUDADC_SL1CFG_ADSEL1_AVG_8_MSRMT = 3
,
AUDADC_SL1CFG_ADSEL1_AVG_16_MSRMTS = 4
, AUDADC_SL1CFG_ADSEL1_AVG_32_MSRMTS = 5
, AUDADC_SL1CFG_ADSEL1_AVG_64_MSRMTS = 6
, AUDADC_SL1CFG_ADSEL1_AVG_128_MSRMTS = 7
} |
| |
| enum | AUDADC_SL1CFG_PRMODE1_Enum { AUDADC_SL1CFG_PRMODE1_P12B0 = 0
, AUDADC_SL1CFG_PRMODE1_P12B1 = 1
, AUDADC_SL1CFG_PRMODE1_P10B = 2
, AUDADC_SL1CFG_PRMODE1_P8B = 3
} |
| |
| enum | AUDADC_SL1CFG_CHSEL1_Enum { AUDADC_SL1CFG_CHSEL1_SE0 = 0
, AUDADC_SL1CFG_CHSEL1_SE1 = 1
, AUDADC_SL1CFG_CHSEL1_SE2 = 2
, AUDADC_SL1CFG_CHSEL1_SE3 = 3
} |
| |
| enum | AUDADC_SL1CFG_WCEN1_Enum { AUDADC_SL1CFG_WCEN1_WCEN = 1
, AUDADC_SL1CFG_WCEN1_WCDIS = 0
} |
| |
| enum | AUDADC_SL1CFG_SLEN1_Enum { AUDADC_SL1CFG_SLEN1_SLEN = 1
, AUDADC_SL1CFG_SLEN1_SLDIS = 0
} |
| |
| enum | AUDADC_SL2CFG_ADSEL2_Enum {
AUDADC_SL2CFG_ADSEL2_AVG_1_MSRMT = 0
, AUDADC_SL2CFG_ADSEL2_AVG_2_MSRMTS = 1
, AUDADC_SL2CFG_ADSEL2_AVG_4_MSRMTS = 2
, AUDADC_SL2CFG_ADSEL2_AVG_8_MSRMT = 3
,
AUDADC_SL2CFG_ADSEL2_AVG_16_MSRMTS = 4
, AUDADC_SL2CFG_ADSEL2_AVG_32_MSRMTS = 5
, AUDADC_SL2CFG_ADSEL2_AVG_64_MSRMTS = 6
, AUDADC_SL2CFG_ADSEL2_AVG_128_MSRMTS = 7
} |
| |
| enum | AUDADC_SL2CFG_PRMODE2_Enum { AUDADC_SL2CFG_PRMODE2_P12B0 = 0
, AUDADC_SL2CFG_PRMODE2_P12B1 = 1
, AUDADC_SL2CFG_PRMODE2_P10B = 2
, AUDADC_SL2CFG_PRMODE2_P8B = 3
} |
| |
| enum | AUDADC_SL2CFG_CHSEL2_Enum { AUDADC_SL2CFG_CHSEL2_SE0 = 0
, AUDADC_SL2CFG_CHSEL2_SE1 = 1
, AUDADC_SL2CFG_CHSEL2_SE2 = 2
, AUDADC_SL2CFG_CHSEL2_SE3 = 3
} |
| |
| enum | AUDADC_SL2CFG_WCEN2_Enum { AUDADC_SL2CFG_WCEN2_WCEN = 1
, AUDADC_SL2CFG_WCEN2_WCDIS = 0
} |
| |
| enum | AUDADC_SL2CFG_SLEN2_Enum { AUDADC_SL2CFG_SLEN2_SLEN = 1
, AUDADC_SL2CFG_SLEN2_SLDIS = 0
} |
| |
| enum | AUDADC_SL3CFG_ADSEL3_Enum {
AUDADC_SL3CFG_ADSEL3_AVG_1_MSRMT = 0
, AUDADC_SL3CFG_ADSEL3_AVG_2_MSRMTS = 1
, AUDADC_SL3CFG_ADSEL3_AVG_4_MSRMTS = 2
, AUDADC_SL3CFG_ADSEL3_AVG_8_MSRMT = 3
,
AUDADC_SL3CFG_ADSEL3_AVG_16_MSRMTS = 4
, AUDADC_SL3CFG_ADSEL3_AVG_32_MSRMTS = 5
, AUDADC_SL3CFG_ADSEL3_AVG_64_MSRMTS = 6
, AUDADC_SL3CFG_ADSEL3_AVG_128_MSRMTS = 7
} |
| |
| enum | AUDADC_SL3CFG_PRMODE3_Enum { AUDADC_SL3CFG_PRMODE3_P12B0 = 0
, AUDADC_SL3CFG_PRMODE3_P12B1 = 1
, AUDADC_SL3CFG_PRMODE3_P10B = 2
, AUDADC_SL3CFG_PRMODE3_P8B = 3
} |
| |
| enum | AUDADC_SL3CFG_CHSEL3_Enum { AUDADC_SL3CFG_CHSEL3_SE0 = 0
, AUDADC_SL3CFG_CHSEL3_SE1 = 1
, AUDADC_SL3CFG_CHSEL3_SE2 = 2
, AUDADC_SL3CFG_CHSEL3_SE3 = 3
} |
| |
| enum | AUDADC_SL3CFG_WCEN3_Enum { AUDADC_SL3CFG_WCEN3_WCEN = 1
, AUDADC_SL3CFG_WCEN3_WCDIS = 0
} |
| |
| enum | AUDADC_SL3CFG_SLEN3_Enum { AUDADC_SL3CFG_SLEN3_SLEN = 1
, AUDADC_SL3CFG_SLEN3_SLDIS = 0
} |
| |
| enum | AUDADC_SL4CFG_ADSEL4_Enum {
AUDADC_SL4CFG_ADSEL4_AVG_1_MSRMT = 0
, AUDADC_SL4CFG_ADSEL4_AVG_2_MSRMTS = 1
, AUDADC_SL4CFG_ADSEL4_AVG_4_MSRMTS = 2
, AUDADC_SL4CFG_ADSEL4_AVG_8_MSRMT = 3
,
AUDADC_SL4CFG_ADSEL4_AVG_16_MSRMTS = 4
, AUDADC_SL4CFG_ADSEL4_AVG_32_MSRMTS = 5
, AUDADC_SL4CFG_ADSEL4_AVG_64_MSRMTS = 6
, AUDADC_SL4CFG_ADSEL4_AVG_128_MSRMTS = 7
} |
| |
| enum | AUDADC_SL4CFG_PRMODE4_Enum { AUDADC_SL4CFG_PRMODE4_P12B0 = 0
, AUDADC_SL4CFG_PRMODE4_P12B1 = 1
, AUDADC_SL4CFG_PRMODE4_P10B = 2
, AUDADC_SL4CFG_PRMODE4_P8B = 3
} |
| |
| enum | AUDADC_SL4CFG_CHSEL4_Enum { AUDADC_SL4CFG_CHSEL4_SE0 = 0
, AUDADC_SL4CFG_CHSEL4_SE1 = 1
, AUDADC_SL4CFG_CHSEL4_SE2 = 2
, AUDADC_SL4CFG_CHSEL4_SE3 = 3
} |
| |
| enum | AUDADC_SL4CFG_WCEN4_Enum { AUDADC_SL4CFG_WCEN4_WCEN = 1
, AUDADC_SL4CFG_WCEN4_WCDIS = 0
} |
| |
| enum | AUDADC_SL4CFG_SLEN4_Enum { AUDADC_SL4CFG_SLEN4_SLEN = 1
, AUDADC_SL4CFG_SLEN4_SLDIS = 0
} |
| |
| enum | AUDADC_SL5CFG_ADSEL5_Enum {
AUDADC_SL5CFG_ADSEL5_AVG_1_MSRMT = 0
, AUDADC_SL5CFG_ADSEL5_AVG_2_MSRMTS = 1
, AUDADC_SL5CFG_ADSEL5_AVG_4_MSRMTS = 2
, AUDADC_SL5CFG_ADSEL5_AVG_8_MSRMT = 3
,
AUDADC_SL5CFG_ADSEL5_AVG_16_MSRMTS = 4
, AUDADC_SL5CFG_ADSEL5_AVG_32_MSRMTS = 5
, AUDADC_SL5CFG_ADSEL5_AVG_64_MSRMTS = 6
, AUDADC_SL5CFG_ADSEL5_AVG_128_MSRMTS = 7
} |
| |
| enum | AUDADC_SL5CFG_PRMODE5_Enum { AUDADC_SL5CFG_PRMODE5_P12B0 = 0
, AUDADC_SL5CFG_PRMODE5_P12B1 = 1
, AUDADC_SL5CFG_PRMODE5_P10B = 2
, AUDADC_SL5CFG_PRMODE5_P8B = 3
} |
| |
| enum | AUDADC_SL5CFG_CHSEL5_Enum { AUDADC_SL5CFG_CHSEL5_SE0 = 0
, AUDADC_SL5CFG_CHSEL5_SE1 = 1
, AUDADC_SL5CFG_CHSEL5_SE2 = 2
, AUDADC_SL5CFG_CHSEL5_SE3 = 3
} |
| |
| enum | AUDADC_SL5CFG_WCEN5_Enum { AUDADC_SL5CFG_WCEN5_WCEN = 1
, AUDADC_SL5CFG_WCEN5_WCDIS = 0
} |
| |
| enum | AUDADC_SL5CFG_SLEN5_Enum { AUDADC_SL5CFG_SLEN5_SLEN = 1
, AUDADC_SL5CFG_SLEN5_SLDIS = 0
} |
| |
| enum | AUDADC_SL6CFG_ADSEL6_Enum {
AUDADC_SL6CFG_ADSEL6_AVG_1_MSRMT = 0
, AUDADC_SL6CFG_ADSEL6_AVG_2_MSRMTS = 1
, AUDADC_SL6CFG_ADSEL6_AVG_4_MSRMTS = 2
, AUDADC_SL6CFG_ADSEL6_AVG_8_MSRMT = 3
,
AUDADC_SL6CFG_ADSEL6_AVG_16_MSRMTS = 4
, AUDADC_SL6CFG_ADSEL6_AVG_32_MSRMTS = 5
, AUDADC_SL6CFG_ADSEL6_AVG_64_MSRMTS = 6
, AUDADC_SL6CFG_ADSEL6_AVG_128_MSRMTS = 7
} |
| |
| enum | AUDADC_SL6CFG_PRMODE6_Enum { AUDADC_SL6CFG_PRMODE6_P12B0 = 0
, AUDADC_SL6CFG_PRMODE6_P12B1 = 1
, AUDADC_SL6CFG_PRMODE6_P10B = 2
, AUDADC_SL6CFG_PRMODE6_P8B = 3
} |
| |
| enum | AUDADC_SL6CFG_CHSEL6_Enum { AUDADC_SL6CFG_CHSEL6_SE0 = 0
, AUDADC_SL6CFG_CHSEL6_SE1 = 1
, AUDADC_SL6CFG_CHSEL6_SE2 = 2
, AUDADC_SL6CFG_CHSEL6_SE3 = 3
} |
| |
| enum | AUDADC_SL6CFG_WCEN6_Enum { AUDADC_SL6CFG_WCEN6_WCEN = 1
, AUDADC_SL6CFG_WCEN6_WCDIS = 0
} |
| |
| enum | AUDADC_SL6CFG_SLEN6_Enum { AUDADC_SL6CFG_SLEN6_SLEN = 1
, AUDADC_SL6CFG_SLEN6_SLDIS = 0
} |
| |
| enum | AUDADC_SL7CFG_ADSEL7_Enum {
AUDADC_SL7CFG_ADSEL7_AVG_1_MSRMT = 0
, AUDADC_SL7CFG_ADSEL7_AVG_2_MSRMTS = 1
, AUDADC_SL7CFG_ADSEL7_AVG_4_MSRMTS = 2
, AUDADC_SL7CFG_ADSEL7_AVG_8_MSRMT = 3
,
AUDADC_SL7CFG_ADSEL7_AVG_16_MSRMTS = 4
, AUDADC_SL7CFG_ADSEL7_AVG_32_MSRMTS = 5
, AUDADC_SL7CFG_ADSEL7_AVG_64_MSRMTS = 6
, AUDADC_SL7CFG_ADSEL7_AVG_128_MSRMTS = 7
} |
| |
| enum | AUDADC_SL7CFG_PRMODE7_Enum { AUDADC_SL7CFG_PRMODE7_P12B0 = 0
, AUDADC_SL7CFG_PRMODE7_P12B1 = 1
, AUDADC_SL7CFG_PRMODE7_P10B = 2
, AUDADC_SL7CFG_PRMODE7_P8B = 3
} |
| |
| enum | AUDADC_SL7CFG_CHSEL7_Enum { AUDADC_SL7CFG_CHSEL7_SE0 = 0
, AUDADC_SL7CFG_CHSEL7_SE1 = 1
, AUDADC_SL7CFG_CHSEL7_SE2 = 2
, AUDADC_SL7CFG_CHSEL7_SE3 = 3
} |
| |
| enum | AUDADC_SL7CFG_WCEN7_Enum { AUDADC_SL7CFG_WCEN7_WCEN = 1
, AUDADC_SL7CFG_WCEN7_WCDIS = 0
} |
| |
| enum | AUDADC_SL7CFG_SLEN7_Enum { AUDADC_SL7CFG_SLEN7_SLEN = 1
, AUDADC_SL7CFG_SLEN7_SLDIS = 0
} |
| |
| enum | AUDADC_INTTRIGTIMER_TIMEREN_Enum { AUDADC_INTTRIGTIMER_TIMEREN_DIS = 0
, AUDADC_INTTRIGTIMER_TIMEREN_EN = 1
} |
| |
| enum | AUDADC_GAINCFG_UPDATEMODE_Enum { AUDADC_GAINCFG_UPDATEMODE_IMMED = 0
, AUDADC_GAINCFG_UPDATEMODE_ZX = 1
} |
| |
| enum | AUDADC_INTEN_SATCB_Enum { AUDADC_INTEN_SATCB_SATCBINT = 1
, AUDADC_INTEN_SATCB_NONSATCBINT = 0
} |
| |
| enum | AUDADC_INTEN_SATCA_Enum { AUDADC_INTEN_SATCA_SATCAINT = 1
, AUDADC_INTEN_SATCA_NONSATCAINT = 0
} |
| |
| enum | AUDADC_INTEN_ZXCB_Enum { AUDADC_INTEN_ZXCB_ZXCBINT = 1
, AUDADC_INTEN_ZXCB_NONZXCBINT = 0
} |
| |
| enum | AUDADC_INTEN_ZXCA_Enum { AUDADC_INTEN_ZXCA_ZXCAINT = 1
, AUDADC_INTEN_ZXCA_NONZXCAINT = 0
} |
| |
| enum | AUDADC_INTEN_DERR_Enum { AUDADC_INTEN_DERR_DMAERROR = 1
, AUDADC_INTEN_DERR_NODMAERROR = 0
} |
| |
| enum | AUDADC_INTEN_DCMP_Enum { AUDADC_INTEN_DCMP_DMACOMPLETE = 1
, AUDADC_INTEN_DCMP_DMAON = 0
} |
| |
| enum | AUDADC_INTEN_WCINC_Enum { AUDADC_INTEN_WCINC_WCINCINT = 1
, AUDADC_INTEN_WCINC_WCINCNOINT = 0
} |
| |
| enum | AUDADC_INTEN_WCEXC_Enum { AUDADC_INTEN_WCEXC_WCEXCINT = 1
, AUDADC_INTEN_WCEXC_WCEXCNOINT = 0
} |
| |
| enum | AUDADC_INTEN_FIFOOVR2_Enum { AUDADC_INTEN_FIFOOVR2_FIFOFULLINT = 1
, AUDADC_INTEN_FIFOOVR2_FIFOFULLNOINT = 0
} |
| |
| enum | AUDADC_INTEN_FIFOOVR1_Enum { AUDADC_INTEN_FIFOOVR1_FIFO75INT = 1
, AUDADC_INTEN_FIFOOVR1_FIFO75NOINT = 0
} |
| |
| enum | AUDADC_INTEN_SCNCMP_Enum { AUDADC_INTEN_SCNCMP_SCNCMPINT = 1
, AUDADC_INTEN_SCNCMP_SCNCMPNOINT = 0
} |
| |
| enum | AUDADC_INTEN_CNVCMP_Enum { AUDADC_INTEN_CNVCMP_CNVCMPINT = 1
, AUDADC_INTEN_CNVCMP_CNVCMPNOINT = 0
} |
| |
| enum | AUDADC_INTSTAT_SATCB_Enum { AUDADC_INTSTAT_SATCB_SATCBINT = 1
, AUDADC_INTSTAT_SATCB_NONSATCBINT = 0
} |
| |
| enum | AUDADC_INTSTAT_SATCA_Enum { AUDADC_INTSTAT_SATCA_SATCAINT = 1
, AUDADC_INTSTAT_SATCA_NONSATCAINT = 0
} |
| |
| enum | AUDADC_INTSTAT_ZXCB_Enum { AUDADC_INTSTAT_ZXCB_ZXCBINT = 1
, AUDADC_INTSTAT_ZXCB_NONZXCBINT = 0
} |
| |
| enum | AUDADC_INTSTAT_ZXCA_Enum { AUDADC_INTSTAT_ZXCA_ZXCAINT = 1
, AUDADC_INTSTAT_ZXCA_NONZXCAINT = 0
} |
| |
| enum | AUDADC_INTSTAT_DERR_Enum { AUDADC_INTSTAT_DERR_DMAERROR = 1
, AUDADC_INTSTAT_DERR_NODMAERROR = 0
} |
| |
| enum | AUDADC_INTSTAT_DCMP_Enum { AUDADC_INTSTAT_DCMP_DMACOMPLETE = 1
, AUDADC_INTSTAT_DCMP_DMAON = 0
} |
| |
| enum | AUDADC_INTSTAT_WCINC_Enum { AUDADC_INTSTAT_WCINC_WCINCINT = 1
, AUDADC_INTSTAT_WCINC_WCINCNOINT = 0
} |
| |
| enum | AUDADC_INTSTAT_WCEXC_Enum { AUDADC_INTSTAT_WCEXC_WCEXCINT = 1
, AUDADC_INTSTAT_WCEXC_WCEXCNOINT = 0
} |
| |
| enum | AUDADC_INTSTAT_FIFOOVR2_Enum { AUDADC_INTSTAT_FIFOOVR2_FIFOFULLINT = 1
, AUDADC_INTSTAT_FIFOOVR2_FIFOFULLNOINT = 0
} |
| |
| enum | AUDADC_INTSTAT_FIFOOVR1_Enum { AUDADC_INTSTAT_FIFOOVR1_FIFO75INT = 1
, AUDADC_INTSTAT_FIFOOVR1_FIFO75NOINT = 0
} |
| |
| enum | AUDADC_INTSTAT_SCNCMP_Enum { AUDADC_INTSTAT_SCNCMP_SCNCMPINT = 1
, AUDADC_INTSTAT_SCNCMP_SCNCMPNOINT = 0
} |
| |
| enum | AUDADC_INTSTAT_CNVCMP_Enum { AUDADC_INTSTAT_CNVCMP_CNVCMPINT = 1
, AUDADC_INTSTAT_CNVCMP_CNVCMPNOINT = 0
} |
| |
| enum | AUDADC_INTCLR_SATCB_Enum { AUDADC_INTCLR_SATCB_SATCBINT = 1
, AUDADC_INTCLR_SATCB_NONSATCBINT = 0
} |
| |
| enum | AUDADC_INTCLR_SATCA_Enum { AUDADC_INTCLR_SATCA_SATCAINT = 1
, AUDADC_INTCLR_SATCA_NONSATCAINT = 0
} |
| |
| enum | AUDADC_INTCLR_ZXCB_Enum { AUDADC_INTCLR_ZXCB_ZXCBINT = 1
, AUDADC_INTCLR_ZXCB_NONZXCBINT = 0
} |
| |
| enum | AUDADC_INTCLR_ZXCA_Enum { AUDADC_INTCLR_ZXCA_ZXCAINT = 1
, AUDADC_INTCLR_ZXCA_NONZXCAINT = 0
} |
| |
| enum | AUDADC_INTCLR_DERR_Enum { AUDADC_INTCLR_DERR_DMAERROR = 1
, AUDADC_INTCLR_DERR_NODMAERROR = 0
} |
| |
| enum | AUDADC_INTCLR_DCMP_Enum { AUDADC_INTCLR_DCMP_DMACOMPLETE = 1
, AUDADC_INTCLR_DCMP_DMAON = 0
} |
| |
| enum | AUDADC_INTCLR_WCINC_Enum { AUDADC_INTCLR_WCINC_WCINCINT = 1
, AUDADC_INTCLR_WCINC_WCINCNOINT = 0
} |
| |
| enum | AUDADC_INTCLR_WCEXC_Enum { AUDADC_INTCLR_WCEXC_WCEXCINT = 1
, AUDADC_INTCLR_WCEXC_WCEXCNOINT = 0
} |
| |
| enum | AUDADC_INTCLR_FIFOOVR2_Enum { AUDADC_INTCLR_FIFOOVR2_FIFOFULLINT = 1
, AUDADC_INTCLR_FIFOOVR2_FIFOFULLNOINT = 0
} |
| |
| enum | AUDADC_INTCLR_FIFOOVR1_Enum { AUDADC_INTCLR_FIFOOVR1_FIFO75INT = 1
, AUDADC_INTCLR_FIFOOVR1_FIFO75NOINT = 0
} |
| |
| enum | AUDADC_INTCLR_SCNCMP_Enum { AUDADC_INTCLR_SCNCMP_SCNCMPINT = 1
, AUDADC_INTCLR_SCNCMP_SCNCMPNOINT = 0
} |
| |
| enum | AUDADC_INTCLR_CNVCMP_Enum { AUDADC_INTCLR_CNVCMP_CNVCMPINT = 1
, AUDADC_INTCLR_CNVCMP_CNVCMPNOINT = 0
} |
| |
| enum | AUDADC_INTSET_SATCB_Enum { AUDADC_INTSET_SATCB_SATCBINT = 1
, AUDADC_INTSET_SATCB_NONSATCBINT = 0
} |
| |
| enum | AUDADC_INTSET_SATCA_Enum { AUDADC_INTSET_SATCA_SATCAINT = 1
, AUDADC_INTSET_SATCA_NONSATCAINT = 0
} |
| |
| enum | AUDADC_INTSET_ZXCB_Enum { AUDADC_INTSET_ZXCB_ZXCBINT = 1
, AUDADC_INTSET_ZXCB_NONZXCBINT = 0
} |
| |
| enum | AUDADC_INTSET_ZXCA_Enum { AUDADC_INTSET_ZXCA_ZXCAINT = 1
, AUDADC_INTSET_ZXCA_NONZXCAINT = 0
} |
| |
| enum | AUDADC_INTSET_DERR_Enum { AUDADC_INTSET_DERR_DMAERROR = 1
, AUDADC_INTSET_DERR_NODMAERROR = 0
} |
| |
| enum | AUDADC_INTSET_DCMP_Enum { AUDADC_INTSET_DCMP_DMACOMPLETE = 1
, AUDADC_INTSET_DCMP_DMAON = 0
} |
| |
| enum | AUDADC_INTSET_WCINC_Enum { AUDADC_INTSET_WCINC_WCINCINT = 1
, AUDADC_INTSET_WCINC_WCINCNOINT = 0
} |
| |
| enum | AUDADC_INTSET_WCEXC_Enum { AUDADC_INTSET_WCEXC_WCEXCINT = 1
, AUDADC_INTSET_WCEXC_WCEXCNOINT = 0
} |
| |
| enum | AUDADC_INTSET_FIFOOVR2_Enum { AUDADC_INTSET_FIFOOVR2_FIFOFULLINT = 1
, AUDADC_INTSET_FIFOOVR2_FIFOFULLNOINT = 0
} |
| |
| enum | AUDADC_INTSET_FIFOOVR1_Enum { AUDADC_INTSET_FIFOOVR1_FIFO75INT = 1
, AUDADC_INTSET_FIFOOVR1_FIFO75NOINT = 0
} |
| |
| enum | AUDADC_INTSET_SCNCMP_Enum { AUDADC_INTSET_SCNCMP_SCNCMPINT = 1
, AUDADC_INTSET_SCNCMP_SCNCMPNOINT = 0
} |
| |
| enum | AUDADC_INTSET_CNVCMP_Enum { AUDADC_INTSET_CNVCMP_CNVCMPINT = 1
, AUDADC_INTSET_CNVCMP_CNVCMPNOINT = 0
} |
| |
| enum | AUDADC_DMACFG_DMADYNPRI_Enum { AUDADC_DMACFG_DMADYNPRI_DIS = 0
, AUDADC_DMACFG_DMADYNPRI_EN = 1
} |
| |
| enum | AUDADC_DMACFG_DMAPRI_Enum { AUDADC_DMACFG_DMAPRI_LOW = 0
, AUDADC_DMACFG_DMAPRI_HIGH = 1
} |
| |
| enum | AUDADC_DMACFG_DMADIR_Enum { AUDADC_DMACFG_DMADIR_P2M = 0
, AUDADC_DMACFG_DMADIR_M2P = 1
} |
| |
| enum | AUDADC_DMACFG_DMAEN_Enum { AUDADC_DMACFG_DMAEN_DIS = 0
, AUDADC_DMACFG_DMAEN_EN = 1
} |
| |
| enum | CLKGEN_OCTRL_OSEL_Enum { CLKGEN_OCTRL_OSEL_RTC_XT = 0
, CLKGEN_OCTRL_OSEL_RTC_LFRC = 1
} |
| |
| enum | CLKGEN_CLKOUT_CKEN_Enum { CLKGEN_CLKOUT_CKEN_DIS = 0
, CLKGEN_CLKOUT_CKEN_EN = 1
} |
| |
| enum | CLKGEN_CLKOUT_CKSEL_Enum {
CLKGEN_CLKOUT_CKSEL_LFRC = 0
, CLKGEN_CLKOUT_CKSEL_XT_DIV2 = 1
, CLKGEN_CLKOUT_CKSEL_XT_DIV4 = 2
, CLKGEN_CLKOUT_CKSEL_XT_DIV8 = 3
,
CLKGEN_CLKOUT_CKSEL_XT_DIV16 = 4
, CLKGEN_CLKOUT_CKSEL_XT_DIV32 = 5
, CLKGEN_CLKOUT_CKSEL_RTC_1Hz = 16
, CLKGEN_CLKOUT_CKSEL_XT_DIV2M = 22
,
CLKGEN_CLKOUT_CKSEL_XT = 23
, CLKGEN_CLKOUT_CKSEL_CG_100Hz = 24
, CLKGEN_CLKOUT_CKSEL_HFRC = 25
, CLKGEN_CLKOUT_CKSEL_HFRC_DIV4 = 26
,
CLKGEN_CLKOUT_CKSEL_HFRC_DIV8 = 27
, CLKGEN_CLKOUT_CKSEL_HFRC_DIV16 = 28
, CLKGEN_CLKOUT_CKSEL_HFRC_DIV64 = 29
, CLKGEN_CLKOUT_CKSEL_HFRC_DIV128 = 30
,
CLKGEN_CLKOUT_CKSEL_HFRC_DIV256 = 31
, CLKGEN_CLKOUT_CKSEL_HFRC_DIV512 = 32
, CLKGEN_CLKOUT_CKSEL_FLASH_CLK = 34
, CLKGEN_CLKOUT_CKSEL_LFRC_DIV2 = 35
,
CLKGEN_CLKOUT_CKSEL_LFRC_DIV32 = 36
, CLKGEN_CLKOUT_CKSEL_LFRC_DIV512 = 37
, CLKGEN_CLKOUT_CKSEL_LFRC_DIV32K = 38
, CLKGEN_CLKOUT_CKSEL_XT_DIV256 = 39
,
CLKGEN_CLKOUT_CKSEL_XT_DIV8K = 40
, CLKGEN_CLKOUT_CKSEL_XT_DIV64K = 41
, CLKGEN_CLKOUT_CKSEL_ULFRC_DIV16 = 42
, CLKGEN_CLKOUT_CKSEL_ULFRC_DIV128 = 43
,
CLKGEN_CLKOUT_CKSEL_ULFRC_1Hz = 44
, CLKGEN_CLKOUT_CKSEL_ULFRC_DIV4K = 45
, CLKGEN_CLKOUT_CKSEL_ULFRC_DIV1M = 46
, CLKGEN_CLKOUT_CKSEL_HFRC_DIV64K = 47
,
CLKGEN_CLKOUT_CKSEL_HFRC_DIV16M = 48
, CLKGEN_CLKOUT_CKSEL_LFRC_DIV1M = 49
, CLKGEN_CLKOUT_CKSEL_HFRCNE = 50
, CLKGEN_CLKOUT_CKSEL_HFRCNE_DIV8 = 51
,
CLKGEN_CLKOUT_CKSEL_XTNE = 53
, CLKGEN_CLKOUT_CKSEL_XTNE_DIV16 = 54
, CLKGEN_CLKOUT_CKSEL_LFRCNE_DIV32 = 55
, CLKGEN_CLKOUT_CKSEL_LFRCNE = 57
,
CLKGEN_CLKOUT_CKSEL_HFRC2_6MHz = 58
, CLKGEN_CLKOUT_CKSEL_HFRC2_12MHz = 59
, CLKGEN_CLKOUT_CKSEL_HFRC2_24MHz = 60
} |
| |
| enum | CLKGEN_HFADJ_HFADJMAXDELTA_Enum { CLKGEN_HFADJ_HFADJMAXDELTA_DISABLED = 0
, CLKGEN_HFADJ_HFADJMAXDELTA_ENABLED = 1
} |
| |
| enum | CLKGEN_HFADJ_HFADJGAIN_Enum {
CLKGEN_HFADJ_HFADJGAIN_Gain_of_1 = 0
, CLKGEN_HFADJ_HFADJGAIN_Gain_of_1_in_2 = 1
, CLKGEN_HFADJ_HFADJGAIN_Gain_of_1_in_4 = 2
, CLKGEN_HFADJ_HFADJGAIN_Gain_of_1_in_8 = 3
,
CLKGEN_HFADJ_HFADJGAIN_Gain_of_1_in_16 = 4
, CLKGEN_HFADJ_HFADJGAIN_Gain_of_1_in_32 = 5
} |
| |
| enum | CLKGEN_HFADJ_HFWARMUP_Enum { CLKGEN_HFADJ_HFWARMUP_1SEC = 0
, CLKGEN_HFADJ_HFWARMUP_2SEC = 1
} |
| |
| enum | CLKGEN_HFADJ_HFADJCK_Enum {
CLKGEN_HFADJ_HFADJCK_4SEC = 0
, CLKGEN_HFADJ_HFADJCK_16SEC = 1
, CLKGEN_HFADJ_HFADJCK_32SEC = 2
, CLKGEN_HFADJ_HFADJCK_64SEC = 3
,
CLKGEN_HFADJ_HFADJCK_128SEC = 4
, CLKGEN_HFADJ_HFADJCK_256SEC = 5
, CLKGEN_HFADJ_HFADJCK_512SEC = 6
, CLKGEN_HFADJ_HFADJCK_1024SEC = 7
} |
| |
| enum | CLKGEN_HFADJ_HFADJEN_Enum { CLKGEN_HFADJ_HFADJEN_DIS = 0
, CLKGEN_HFADJ_HFADJEN_EN = 1
} |
| |
| enum | CLKGEN_CLOCKENSTAT_CLOCKENSTAT_Enum {
CLKGEN_CLOCKENSTAT_CLOCKENSTAT_PERIPH_ALL_XTAL_EN = 16777216
, CLKGEN_CLOCKENSTAT_CLOCKENSTAT_PERIPH_ALL_HFRC_EN = 33554432
, CLKGEN_CLOCKENSTAT_CLOCKENSTAT_HFADJEN = 67108864
, CLKGEN_CLOCKENSTAT_CLOCKENSTAT_HFRC_EN_HFADJ = 134217728
,
CLKGEN_CLOCKENSTAT_CLOCKENSTAT_nOSEL = 268435456
, CLKGEN_CLOCKENSTAT_CLOCKENSTAT_clkout_xtal_en = 536870912
, CLKGEN_CLOCKENSTAT_CLOCKENSTAT_clkout_hfrc_en = 1073741824
} |
| |
| enum | CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_Enum {
CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_ADC_CLKEN = 1
, CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_APBDMA_ACTIVITY_CLKEN = 2
, CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_APBDMA_AOH_CLKEN = 4
, CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_APBDMA_AOL_CLKEN = 8
,
CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_APBDMA_APB_CLKEN = 16
, CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_APBDMA_AUD_CLKEN = 32
, CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_APBDMA_CRYPTO_CLKEN = 64
, CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_APBDMA_DBG_CLKEN = 128
,
CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_APBDMA_DISP_CLKEN = 256
, CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_APBDMA_DISPPHY_CLKEN = 512
, CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_APBDMA_DSPA_CLKEN = 1024
, CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_APBDMA_GFX_CLKEN = 2048
,
CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_APBDMA_HSPA_CLKEN = 4096
, CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_APBDMA_HSPB_CLKEN = 8192
, CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_APBDMA_HSPC_CLKEN = 16384
, CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_APBDMA_IOS_CLKEN = 32768
,
CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_APBDMA_MSPI0_CLKEN = 65536
, CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_APBDMA_MSPI1_CLKEN = 131072
, CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_APBDMA_MSPI2_CLKEN = 262144
, CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_APBDMA_SDIO_CLKEN = 524288
,
CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_APBDMA_USB_CLKEN = 1048576
, CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_AUDADC_CLKEN = 2097152
, CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_CM4_TPIU_CLKEN = 4194304
, CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_DBG_TPIU_CLKEN = 8388608
,
CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_DBG_TS_CLKEN = 16777216
, CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_DISP_CLK_CLKEN = 33554432
, CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_DPHY_PLL_REF_CLKEN = 67108864
, CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_DSP_I2S0_CLKEN = 134217728
,
CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_DSP_I2S0_REFCLK_CLKEN = 268435456
, CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_DSP_I2S1_CLKEN = 536870912
, CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_DSP_I2S1_REFCLK_CLKEN = 1073741824
, CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_DSP_MILLI_CLKEN = -2147483648
} |
| |
| enum | CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_Enum {
CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_DSP_PDM0_CLKEN = 1
, CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_DSP_PDM1_CLKEN = 2
, CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_DSP_PDM2_CLKEN = 4
, CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_DSP_PDM3_CLKEN = 8
,
CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_I3C0_REFCLK_CLKEN = 16
, CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_I3C1_REFCLK_CLKEN = 32
, CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_IOMSTRIFC0_CLKEN = 64
, CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_IOMSTRIFC1_CLKEN = 128
,
CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_IOMSTRIFC2_CLKEN = 256
, CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_IOMSTRIFC3_CLKEN = 512
, CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_IOMSTRIFC4_CLKEN = 1024
, CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_IOMSTRIFC5_CLKEN = 2048
,
CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_IOMSTRIFC6_CLKEN = 4096
, CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_IOMSTRIFC7_CLKEN = 8192
, CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_RSTGEN_CLKEN = 16384
, CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_RSTGEN_POS_CLKEN = 32768
,
CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_RTC_CLKEN = 65536
, CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_SDIO_XIN_CLKEN = 131072
, CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_UART0HF_CLKEN = 262144
, CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_UART1HF_CLKEN = 524288
,
CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_UART2HF_CLKEN = 1048576
, CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_UART3HF_CLKEN = 2097152
, CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_USB_REFCLK_CLKEN = 4194304
, CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_WDT_CLKEN = 8388608
} |
| |
| enum | CLKGEN_MISC_HFRC96TRUNKGATE_Enum { CLKGEN_MISC_HFRC96TRUNKGATE_DIS = 0
, CLKGEN_MISC_HFRC96TRUNKGATE_EN = 1
} |
| |
| enum | CLKGEN_MISC_HFRCFUNCCLKGATEEN_Enum { CLKGEN_MISC_HFRCFUNCCLKGATEEN_DIS = 0
, CLKGEN_MISC_HFRCFUNCCLKGATEEN_EN = 1
} |
| |
| enum | CLKGEN_MISC_ETMTRACECLKCLKGATEEN_Enum { CLKGEN_MISC_ETMTRACECLKCLKGATEEN_DIS = 0
, CLKGEN_MISC_ETMTRACECLKCLKGATEEN_EN = 1
} |
| |
| enum | CLKGEN_MISC_APBDMACPUCLKCLKGATEEN_Enum { CLKGEN_MISC_APBDMACPUCLKCLKGATEEN_DIS = 0
, CLKGEN_MISC_APBDMACPUCLKCLKGATEEN_EN = 1
} |
| |
| enum | CLKGEN_MISC_GFXAXICLKCLKGATEEN_Enum { CLKGEN_MISC_GFXAXICLKCLKGATEEN_DIS = 0
, CLKGEN_MISC_GFXAXICLKCLKGATEEN_EN = 1
} |
| |
| enum | CLKGEN_MISC_GFXCLKCLKGATEEN_Enum { CLKGEN_MISC_GFXCLKCLKGATEEN_DIS = 0
, CLKGEN_MISC_GFXCLKCLKGATEEN_EN = 1
} |
| |
| enum | CLKGEN_MISC_CM4DAXICLKGATEEN_Enum { CLKGEN_MISC_CM4DAXICLKGATEEN_DIS = 0
, CLKGEN_MISC_CM4DAXICLKGATEEN_EN = 1
} |
| |
| enum | CLKGEN_MISC_PWRONCLKENUSBREFCLK_Enum { CLKGEN_MISC_PWRONCLKENUSBREFCLK_USBREFCLKENRST = 0
, CLKGEN_MISC_PWRONCLKENUSBREFCLK_DEFEATURE = 1
} |
| |
| enum | CLKGEN_MISC_PWRONCLKENI2S1REFCLK_Enum { CLKGEN_MISC_PWRONCLKENI2S1REFCLK_I2S1REFCLKENRST = 0
, CLKGEN_MISC_PWRONCLKENI2S1REFCLK_DEFEATURE = 1
} |
| |
| enum | CLKGEN_MISC_PWRONCLKENI2S0REFCLK_Enum { CLKGEN_MISC_PWRONCLKENI2S0REFCLK_I2S0REFCLKENRST = 0
, CLKGEN_MISC_PWRONCLKENI2S0REFCLK_DEFEATURE = 1
} |
| |
| enum | CLKGEN_MISC_AXIXACLKENOVRRIDE_Enum { CLKGEN_MISC_AXIXACLKENOVRRIDE_DEFEATURE_DISABLED = 0
, CLKGEN_MISC_AXIXACLKENOVRRIDE_DEFEATURE = 1
} |
| |
| enum | CLKGEN_MISC_PWRONCLKENI2S1_Enum { CLKGEN_MISC_PWRONCLKENI2S1_I2S1CLKENRST = 0
, CLKGEN_MISC_PWRONCLKENI2S1_DEFEATURE = 1
} |
| |
| enum | CLKGEN_MISC_PWRONCLKENI2S0_Enum { CLKGEN_MISC_PWRONCLKENI2S0_I2S0CLKENRST = 0
, CLKGEN_MISC_PWRONCLKENI2S0_DEFEATURE = 1
} |
| |
| enum | CLKGEN_MISC_PWRONCLKENCRYPTO_Enum { CLKGEN_MISC_PWRONCLKENCRYPTO_CRYPTOCLKENRST = 0
, CLKGEN_MISC_PWRONCLKENCRYPTO_DEFEATURE = 1
} |
| |
| enum | CLKGEN_MISC_PWRONCLKENSDIO_Enum { CLKGEN_MISC_PWRONCLKENSDIO_SDIOCLKENRST = 0
, CLKGEN_MISC_PWRONCLKENSDIO_DEFEATURE = 1
} |
| |
| enum | CLKGEN_MISC_PWRONCLKENUSB_Enum { CLKGEN_MISC_PWRONCLKENUSB_USBCLKENRST = 0
, CLKGEN_MISC_PWRONCLKENUSB_DEFEATURE = 1
} |
| |
| enum | CLKGEN_MISC_PWRONCLKENGFX_Enum { CLKGEN_MISC_PWRONCLKENGFX_GFXCLKENRST = 0
, CLKGEN_MISC_PWRONCLKENGFX_DEFEATURE = 1
} |
| |
| enum | CLKGEN_MISC_PWRONCLKENDISPPHY_Enum { CLKGEN_MISC_PWRONCLKENDISPPHY_DISPPHYCLKENRST = 0
, CLKGEN_MISC_PWRONCLKENDISPPHY_DEFEATURE = 1
} |
| |
| enum | CLKGEN_MISC_PWRONCLKENDISP_Enum { CLKGEN_MISC_PWRONCLKENDISP_DISPCLKENRST = 0
, CLKGEN_MISC_PWRONCLKENDISP_DEFEATURE = 1
} |
| |
| enum | CLKGEN_MISC_FRCHFRC2_Enum { CLKGEN_MISC_FRCHFRC2_NOFRC = 0
, CLKGEN_MISC_FRCHFRC2_FRC = 1
} |
| |
| enum | CLKGEN_MISC_USEHFRC2FQ192MHZ_Enum { CLKGEN_MISC_USEHFRC2FQ192MHZ_HFRCFQ192MHz = 0
, CLKGEN_MISC_USEHFRC2FQ192MHZ_HFRC2FQ192MHz = 1
} |
| |
| enum | CLKGEN_MISC_USEHFRC2FQ96MHZ_Enum { CLKGEN_MISC_USEHFRC2FQ96MHZ_HFRCFQ96MHz = 0
, CLKGEN_MISC_USEHFRC2FQ96MHZ_HFRC2FQ96MHz = 1
} |
| |
| enum | CLKGEN_MISC_USEHFRC2FQ48MHZ_Enum { CLKGEN_MISC_USEHFRC2FQ48MHZ_HFRCFQ48MHz = 0
, CLKGEN_MISC_USEHFRC2FQ48MHZ_HFRC2FQ48MHz = 1
} |
| |
| enum | CLKGEN_MISC_FRCBURSTOFF_Enum { CLKGEN_MISC_FRCBURSTOFF_BURSTCLKON = 0
, CLKGEN_MISC_FRCBURSTOFF_BURSTCLKOFF = 1
} |
| |
| enum | CLKGEN_MISC_FRCHFRC_Enum { CLKGEN_MISC_FRCHFRC_NOFRC = 0
, CLKGEN_MISC_FRCHFRC_FRC = 1
} |
| |
| enum | CLKGEN_HF2ADJ0_HF2ADJFASTSTREN_Enum { CLKGEN_HF2ADJ0_HF2ADJFASTSTREN_DIS = 0
, CLKGEN_HF2ADJ0_HF2ADJFASTSTREN_EN = 1
} |
| |
| enum | CLKGEN_HF2ADJ0_HF2ADJEN_Enum { CLKGEN_HF2ADJ0_HF2ADJEN_DIS = 0
, CLKGEN_HF2ADJ0_HF2ADJEN_EN = 1
} |
| |
| enum | CLKGEN_HF2ADJ1_HF2ADJTRIMEN_Enum {
CLKGEN_HF2ADJ1_HF2ADJTRIMEN_TRIM_EN0 = 0
, CLKGEN_HF2ADJ1_HF2ADJTRIMEN_TRIM_EN1 = 1
, CLKGEN_HF2ADJ1_HF2ADJTRIMEN_TRIM_EN2 = 2
, CLKGEN_HF2ADJ1_HF2ADJTRIMEN_TRIM_EN3 = 3
,
CLKGEN_HF2ADJ1_HF2ADJTRIMEN_TRIM_EN4 = 4
, CLKGEN_HF2ADJ1_HF2ADJTRIMEN_TRIM_EN5 = 5
, CLKGEN_HF2ADJ1_HF2ADJTRIMEN_TRIM_EN6 = 6
, CLKGEN_HF2ADJ1_HF2ADJTRIMEN_TRIM_EN7 = 7
} |
| |
| enum | CLKGEN_HF2ADJ2_HF2ADJXTALDIVRATIO_Enum { CLKGEN_HF2ADJ2_HF2ADJXTALDIVRATIO_XTAL32M = 0
, CLKGEN_HF2ADJ2_HF2ADJXTALDIVRATIO_XTAL32M_DIV2 = 1
, CLKGEN_HF2ADJ2_HF2ADJXTALDIVRATIO_XTAL32M_DIV4 = 2
, CLKGEN_HF2ADJ2_HF2ADJXTALDIVRATIO_XTAL32M_DIV8 = 3
} |
| |
| enum | CLKGEN_DISPCLKCTRL_DISPCLKSEL_Enum { CLKGEN_DISPCLKCTRL_DISPCLKSEL_OFF = 0
, CLKGEN_DISPCLKCTRL_DISPCLKSEL_HFRC48 = 1
, CLKGEN_DISPCLKCTRL_DISPCLKSEL_HFRC96 = 2
, CLKGEN_DISPCLKCTRL_DISPCLKSEL_DPHYPLL = 3
} |
| |
| enum | CLKGEN_DISPCLKCTRL_PLLCLKSEL_Enum { CLKGEN_DISPCLKCTRL_PLLCLKSEL_OFF = 0
, CLKGEN_DISPCLKCTRL_PLLCLKSEL_HFRC12 = 1
, CLKGEN_DISPCLKCTRL_PLLCLKSEL_HFRC6 = 2
, CLKGEN_DISPCLKCTRL_PLLCLKSEL_HFXT_16 = 3
} |
| |
| enum | CPU_CACHECFG_CONFIG_Enum {
CPU_CACHECFG_CONFIG_W1_128B_512E = 4
, CPU_CACHECFG_CONFIG_W2_128B_512E = 5
, CPU_CACHECFG_CONFIG_W1_128B_1024E = 8
, CPU_CACHECFG_CONFIG_W1_128B_2048E = 12
,
CPU_CACHECFG_CONFIG_W2_128B_2048E = 13
, CPU_CACHECFG_CONFIG_W1_128B_4096E = 14
} |
| |
| enum | CPU_CACHECTRL_RESETSTAT_Enum { CPU_CACHECTRL_RESETSTAT_CLEAR = 1
, CPU_CACHECTRL_RESETSTAT_DEFAULT = 0
} |
| |
| enum | CPU_DAXICFG_MRUGROUPLEVEL_Enum { CPU_DAXICFG_MRUGROUPLEVEL_MAX = 0
, CPU_DAXICFG_MRUGROUPLEVEL_ONELESSTHANMAX = 1
, CPU_DAXICFG_MRUGROUPLEVEL_TWOLESSTHANMAX = 2
, CPU_DAXICFG_MRUGROUPLEVEL_THREELESSTHANMAX = 3
} |
| |
| enum | CPU_DAXICFG_AGINGCOUNTER_Enum {
CPU_DAXICFG_AGINGCOUNTER_ONE = 0
, CPU_DAXICFG_AGINGCOUNTER_TWO = 1
, CPU_DAXICFG_AGINGCOUNTER_FOUR = 2
, CPU_DAXICFG_AGINGCOUNTER_EIGHT = 3
,
CPU_DAXICFG_AGINGCOUNTER_SIXTEEN = 4
, CPU_DAXICFG_AGINGCOUNTER_THIRTYTWO = 5
, CPU_DAXICFG_AGINGCOUNTER_SIXTYFOUR = 6
, CPU_DAXICFG_AGINGCOUNTER_ONEHUNDREDTWENTYEIGHT = 7
,
CPU_DAXICFG_AGINGCOUNTER_TWOHUNDEREDFIFTYSIX = 8
, CPU_DAXICFG_AGINGCOUNTER_FIVEHUNDREDTWELVE = 9
, CPU_DAXICFG_AGINGCOUNTER_ONEK = 10
, CPU_DAXICFG_AGINGCOUNTER_TWOK = 11
,
CPU_DAXICFG_AGINGCOUNTER_FOURK = 12
, CPU_DAXICFG_AGINGCOUNTER_EIGHTK = 13
, CPU_DAXICFG_AGINGCOUNTER_SIXTEENK = 14
, CPU_DAXICFG_AGINGCOUNTER_THIRTYTWOK = 15
,
CPU_DAXICFG_AGINGCOUNTER_SIXTYFOURK = 16
} |
| |
| enum | CPU_DAXICFG_BUFFERENABLE_Enum {
CPU_DAXICFG_BUFFERENABLE_ONE = 0
, CPU_DAXICFG_BUFFERENABLE_TWO = 1
, CPU_DAXICFG_BUFFERENABLE_THREE = 2
, CPU_DAXICFG_BUFFERENABLE_FOUR = 3
,
CPU_DAXICFG_BUFFERENABLE_FIVE = 4
, CPU_DAXICFG_BUFFERENABLE_SIX = 5
, CPU_DAXICFG_BUFFERENABLE_SEVEN = 6
, CPU_DAXICFG_BUFFERENABLE_EIGHT = 7
,
CPU_DAXICFG_BUFFERENABLE_THIRTEEN = 8
, CPU_DAXICFG_BUFFERENABLE_FOURTEEN = 9
, CPU_DAXICFG_BUFFERENABLE_FIFTEEN = 10
, CPU_DAXICFG_BUFFERENABLE_SIXTEEN = 11
,
CPU_DAXICFG_BUFFERENABLE_TWENTYNINE = 12
, CPU_DAXICFG_BUFFERENABLE_THIRTY = 13
, CPU_DAXICFG_BUFFERENABLE_THIRTYONE = 14
, CPU_DAXICFG_BUFFERENABLE_THIRTYTWO = 15
} |
| |
| enum | CPU_DAXICFG_DAXISTATECLKGATEEN_Enum { CPU_DAXICFG_DAXISTATECLKGATEEN_EN = 0
, CPU_DAXICFG_DAXISTATECLKGATEEN_DIS = 1
} |
| |
| enum | CPU_DAXICFG_DAXIDATACLKGATEEN_Enum { CPU_DAXICFG_DAXIDATACLKGATEEN_EN = 0
, CPU_DAXICFG_DAXIDATACLKGATEEN_DIS = 1
} |
| |
| enum | CPU_DAXICFG_DAXIBECLKGATEEN_Enum { CPU_DAXICFG_DAXIBECLKGATEEN_EN = 0
, CPU_DAXICFG_DAXIBECLKGATEEN_DIS = 1
} |
| |
| enum | CPU_DAXICFG_DAXIPASSTHROUGH_Enum { CPU_DAXICFG_DAXIPASSTHROUGH_DIS = 0
, CPU_DAXICFG_DAXIPASSTHROUGH_EN = 1
} |
| |
| enum | CPU_DAXICFG_AGINGSENABLE_Enum { CPU_DAXICFG_AGINGSENABLE_DIS = 0
, CPU_DAXICFG_AGINGSENABLE_EN = 1
} |
| |
| enum | CPU_DAXICFG_FLUSHLEVEL_Enum { CPU_DAXICFG_FLUSHLEVEL_TWO = 0
, CPU_DAXICFG_FLUSHLEVEL_THREE = 1
} |
| |
| enum | CPU_FAULTSTATUS_SYSFAULT_Enum { CPU_FAULTSTATUS_SYSFAULT_NOFAULT = 0
, CPU_FAULTSTATUS_SYSFAULT_FAULT = 1
} |
| |
| enum | CPU_FAULTSTATUS_DCODEFAULT_Enum { CPU_FAULTSTATUS_DCODEFAULT_NOFAULT = 0
, CPU_FAULTSTATUS_DCODEFAULT_FAULT = 1
} |
| |
| enum | CPU_FAULTSTATUS_ICODEFAULT_Enum { CPU_FAULTSTATUS_ICODEFAULT_NOFAULT = 0
, CPU_FAULTSTATUS_ICODEFAULT_FAULT = 1
} |
| |
| enum | CPU_FAULTCAPTUREEN_FAULTCAPTUREEN_Enum { CPU_FAULTCAPTUREEN_FAULTCAPTUREEN_DIS = 0
, CPU_FAULTCAPTUREEN_FAULTCAPTUREEN_EN = 1
} |
| |
| enum | CRYPTO_OPCODE_OPCODE_Enum {
CRYPTO_OPCODE_OPCODE_ADD = 4
, CRYPTO_OPCODE_OPCODE_SUB = 5
, CRYPTO_OPCODE_OPCODE_MODADD = 6
, CRYPTO_OPCODE_OPCODE_MODSUB = 7
,
CRYPTO_OPCODE_OPCODE_AND = 8
, CRYPTO_OPCODE_OPCODE_OR = 9
, CRYPTO_OPCODE_OPCODE_XOR = 10
, CRYPTO_OPCODE_OPCODE_SHR0 = 12
,
CRYPTO_OPCODE_OPCODE_SHR1 = 13
, CRYPTO_OPCODE_OPCODE_SHL0 = 14
, CRYPTO_OPCODE_OPCODE_SHL1 = 15
, CRYPTO_OPCODE_OPCODE_MULLOW = 16
,
CRYPTO_OPCODE_OPCODE_MODMUL = 17
, CRYPTO_OPCODE_OPCODE_MODMULN = 18
, CRYPTO_OPCODE_OPCODE_MODEXP = 19
, CRYPTO_OPCODE_OPCODE_DIVISION = 20
,
CRYPTO_OPCODE_OPCODE_DIV = 21
, CRYPTO_OPCODE_OPCODE_MODDIV = 22
, CRYPTO_OPCODE_OPCODE_TERMINATE = 0
} |
| |
| enum | CRYPTO_RNGISR_WHICHKATERR_Enum { CRYPTO_RNGISR_WHICHKATERR_INSTANT_1 = 0
, CRYPTO_RNGISR_WHICHKATERR_INSTANT_2 = 1
, CRYPTO_RNGISR_WHICHKATERR_RESEED_1 = 2
, CRYPTO_RNGISR_WHICHKATERR_RESEED_2 = 3
} |
| |
| enum | CRYPTO_TRNGCONFIG_SOPSEL_Enum { CRYPTO_TRNGCONFIG_SOPSEL_SOP_DATA_1 = 1
, CRYPTO_TRNGCONFIG_SOPSEL_SOP_DATA_2 = 0
} |
| |
| enum | CRYPTO_RNGVERSION_RNGUSE5SBOXES_Enum { CRYPTO_RNGVERSION_RNGUSE5SBOXES_20_SBOX_AES = 0
, CRYPTO_RNGVERSION_RNGUSE5SBOXES_5_SBOX_AES = 1
} |
| |
| enum | CRYPTO_RNGVERSION_RESEEDINGEXISTS_Enum { CRYPTO_RNGVERSION_RESEEDINGEXISTS_EXISTS = 1
, CRYPTO_RNGVERSION_RESEEDINGEXISTS_NORESEED = 0
} |
| |
| enum | CRYPTO_RNGVERSION_KATEXISTS_Enum { CRYPTO_RNGVERSION_KATEXISTS_NO_EXIST = 0
, CRYPTO_RNGVERSION_KATEXISTS_EXISTS = 1
} |
| |
| enum | CRYPTO_RNGVERSION_PRNGEXISTS_Enum { CRYPTO_RNGVERSION_PRNGEXISTS_NO_EXIST = 0
, CRYPTO_RNGVERSION_PRNGEXISTS_EXISTS = 1
} |
| |
| enum | CRYPTO_RNGVERSION_TRNGTESTSBYPASSEN_Enum { CRYPTO_RNGVERSION_TRNGTESTSBYPASSEN_TRNG_NE = 0
, CRYPTO_RNGVERSION_TRNGTESTSBYPASSEN_TRNG_E = 1
} |
| |
| enum | CRYPTO_RNGVERSION_AUTOCORREXISTS_Enum { CRYPTO_RNGVERSION_AUTOCORREXISTS_NO_EXIST = 0
, CRYPTO_RNGVERSION_AUTOCORREXISTS_EXISTS = 1
} |
| |
| enum | CRYPTO_RNGVERSION_CRNGTEXISTS_Enum { CRYPTO_RNGVERSION_CRNGTEXISTS_NO_EXIST = 0
, CRYPTO_RNGVERSION_CRNGTEXISTS_EXISTS = 1
} |
| |
| enum | CRYPTO_RNGVERSION_EHRWIDTH192_Enum { CRYPTO_RNGVERSION_EHRWIDTH192_128_EHR = 0
, CRYPTO_RNGVERSION_EHRWIDTH192_192_EHR = 1
} |
| |
| enum | CRYPTO_CHACHACONTROLREG_NUMOFROUNDS_Enum { CRYPTO_CHACHACONTROLREG_NUMOFROUNDS_20_ROUNDS = 0
, CRYPTO_CHACHACONTROLREG_NUMOFROUNDS_12_ROUNDS = 1
, CRYPTO_CHACHACONTROLREG_NUMOFROUNDS_8_ROUNDS = 2
, CRYPTO_CHACHACONTROLREG_NUMOFROUNDS_N_A = 3
} |
| |
| enum | CRYPTO_CHACHACONTROLREG_KEYLEN_Enum { CRYPTO_CHACHACONTROLREG_KEYLEN_256_BIT = 0
, CRYPTO_CHACHACONTROLREG_KEYLEN_128_BIT = 1
} |
| |
| enum | CRYPTO_CHACHACONTROLREG_CALCKEYFORPOLY1305_Enum { CRYPTO_CHACHACONTROLREG_CALCKEYFORPOLY1305_DISABLE = 0
, CRYPTO_CHACHACONTROLREG_CALCKEYFORPOLY1305_ENABLE = 1
} |
| |
| enum | CRYPTO_CHACHACONTROLREG_INITFROMHOST_Enum { CRYPTO_CHACHACONTROLREG_INITFROMHOST_DISABLE = 0
, CRYPTO_CHACHACONTROLREG_INITFROMHOST_ENABLE = 1
} |
| |
| enum | CRYPTO_CHACHACONTROLREG_CHACHAORSALSA_Enum { CRYPTO_CHACHACONTROLREG_CHACHAORSALSA_CHACHA = 0
, CRYPTO_CHACHACONTROLREG_CHACHAORSALSA_SALSA = 1
} |
| |
| enum | CRYPTO_CHACHAHWFLAGS_FASTCHACHA_Enum { CRYPTO_CHACHAHWFLAGS_FASTCHACHA_DISABLE = 0
, CRYPTO_CHACHAHWFLAGS_FASTCHACHA_ENABLE = 1
} |
| |
| enum | CRYPTO_CHACHAHWFLAGS_SALSAEXISTS_Enum { CRYPTO_CHACHAHWFLAGS_SALSAEXISTS_DISABLE = 0
, CRYPTO_CHACHAHWFLAGS_SALSAEXISTS_ENABLE = 1
} |
| |
| enum | CRYPTO_CHACHAHWFLAGS_CHACHAEXISTS_Enum { CRYPTO_CHACHAHWFLAGS_CHACHAEXISTS_DISABLE = 0
, CRYPTO_CHACHAHWFLAGS_CHACHAEXISTS_ENABLE = 1
} |
| |
| enum | CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHADOUTBYTEORDER_Enum { CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHADOUTBYTEORDER_DISABLE = 0
, CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHADOUTBYTEORDER_ENABLE = 1
} |
| |
| enum | CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHADOUTWORDORDER_Enum { CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHADOUTWORDORDER_DISABLE = 0
, CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHADOUTWORDORDER_ENABLE = 1
} |
| |
| enum | CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHACOREMATRIXLBEORDER_Enum { CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHACOREMATRIXLBEORDER_DISABLE = 0
, CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHACOREMATRIXLBEORDER_ENABLE = 1
} |
| |
| enum | CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHADINBYTEORDER_Enum { CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHADINBYTEORDER_DISABLE = 0
, CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHADINBYTEORDER_ENABLE = 1
} |
| |
| enum | CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHADINWORDORDER_Enum { CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHADINWORDORDER_DISABLE = 0
, CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHADINWORDORDER_ENABLE = 1
} |
| |
| enum | CRYPTO_CHACHADEBUGREG_CHACHADEBUGFSMSTATE_Enum { CRYPTO_CHACHADEBUGREG_CHACHADEBUGFSMSTATE_IDLE_STATE = 0
, CRYPTO_CHACHADEBUGREG_CHACHADEBUGFSMSTATE_INIT_STATE = 1
} |
| |
| enum | CRYPTO_AESCONTROL_AESXORCRYPTOKEY_Enum { CRYPTO_AESCONTROL_AESXORCRYPTOKEY_CRYPTOKEY = 0
, CRYPTO_AESCONTROL_AESXORCRYPTOKEY_CRYPTOKEY_XOR = 1
} |
| |
| enum | CRYPTO_AESCONTROL_AESOUTMIDTUNTOHASH_Enum { CRYPTO_AESCONTROL_AESOUTMIDTUNTOHASH_HASH_2 = 0
, CRYPTO_AESCONTROL_AESOUTMIDTUNTOHASH_HASH_1 = 1
} |
| |
| enum | CRYPTO_AESCONTROL_AESTUNNELB1PADEN_Enum { CRYPTO_AESCONTROL_AESTUNNELB1PADEN_DATA_NO_PAD = 0
, CRYPTO_AESCONTROL_AESTUNNELB1PADEN_DATA_IS_PAD = 1
} |
| |
| enum | CRYPTO_AESCONTROL_AESOUTPUTMIDTUNNELDATA_Enum { CRYPTO_AESCONTROL_AESOUTPUTMIDTUNNELDATA_ENGINE_RSLT_2 = 0
, CRYPTO_AESCONTROL_AESOUTPUTMIDTUNNELDATA_ENGINE_RSLT_1 = 1
} |
| |
| enum | CRYPTO_AESCONTROL_AESTUNNEL0ENCRYPT_Enum { CRYPTO_AESCONTROL_AESTUNNEL0ENCRYPT_TUNNEL_1_D = 0
, CRYPTO_AESCONTROL_AESTUNNEL0ENCRYPT_TUNNEL_1_E = 1
} |
| |
| enum | CRYPTO_AESCONTROL_AESTUNB1USESPADDEDDATAIN_Enum { CRYPTO_AESCONTROL_AESTUNB1USESPADDEDDATAIN_BLOCK_1 = 0
, CRYPTO_AESCONTROL_AESTUNB1USESPADDEDDATAIN_AFTER_PAD = 1
} |
| |
| enum | CRYPTO_AESCONTROL_AESTUNNEL1DECRYPT_Enum { CRYPTO_AESCONTROL_AESTUNNEL1DECRYPT_TUNNEL_2_E = 0
, CRYPTO_AESCONTROL_AESTUNNEL1DECRYPT_TUNNEL_2_D = 1
} |
| |
| enum | CRYPTO_AESCONTROL_NKKEY1_Enum { CRYPTO_AESCONTROL_NKKEY1_128_BITS_KEY = 0
, CRYPTO_AESCONTROL_NKKEY1_192_BITS_KEY = 1
, CRYPTO_AESCONTROL_NKKEY1_256_BITS_KEY = 2
, CRYPTO_AESCONTROL_NKKEY1_N_A = 3
} |
| |
| enum | CRYPTO_AESCONTROL_NKKEY0_Enum { CRYPTO_AESCONTROL_NKKEY0_128_BITS_KEY = 0
, CRYPTO_AESCONTROL_NKKEY0_192_BITS_KEY = 1
, CRYPTO_AESCONTROL_NKKEY0_256_BITS_KEY = 2
, CRYPTO_AESCONTROL_NKKEY0_N_A = 3
} |
| |
| enum | CRYPTO_AESCONTROL_AESTUNNELISON_Enum { CRYPTO_AESCONTROL_AESTUNNELISON_STD_NONTUNNEL = 0
, CRYPTO_AESCONTROL_AESTUNNELISON_TUNNEL = 1
} |
| |
| enum | CRYPTO_AESCONTROL_MODEKEY1_Enum {
CRYPTO_AESCONTROL_MODEKEY1_ECB = 0
, CRYPTO_AESCONTROL_MODEKEY1_CBC = 1
, CRYPTO_AESCONTROL_MODEKEY1_CTR = 2
, CRYPTO_AESCONTROL_MODEKEY1_CBC_MAC = 3
,
CRYPTO_AESCONTROL_MODEKEY1_XEX_XTS = 4
, CRYPTO_AESCONTROL_MODEKEY1_XCBC_MAC = 5
, CRYPTO_AESCONTROL_MODEKEY1_OFB = 6
, CRYPTO_AESCONTROL_MODEKEY1_CMAC = 7
} |
| |
| enum | CRYPTO_AESCONTROL_MODEKEY0_Enum {
CRYPTO_AESCONTROL_MODEKEY0_ECB = 0
, CRYPTO_AESCONTROL_MODEKEY0_CBC = 1
, CRYPTO_AESCONTROL_MODEKEY0_CTR = 2
, CRYPTO_AESCONTROL_MODEKEY0_CBCMAC = 3
,
CRYPTO_AESCONTROL_MODEKEY0_XEX_XTS = 4
, CRYPTO_AESCONTROL_MODEKEY0_XCBC_MAC = 5
, CRYPTO_AESCONTROL_MODEKEY0_OFB = 6
, CRYPTO_AESCONTROL_MODEKEY0_CMAC = 7
} |
| |
| enum | CRYPTO_AESCONTROL_DECKEY0_Enum { CRYPTO_AESCONTROL_DECKEY0_ENCRYPT = 0
, CRYPTO_AESCONTROL_DECKEY0_DECRYPT = 1
} |
| |
| enum | CRYPTO_HASHSELAESMAC_GHASHSEL_Enum { CRYPTO_HASHSELAESMAC_GHASHSEL_HASH_MOD = 0
, CRYPTO_HASHSELAESMAC_GHASHSEL_GHASH_MOD = 1
} |
| |
| enum | CRYPTO_HASHSELAESMAC_HASHSELAESMAC_Enum { CRYPTO_HASHSELAESMAC_HASHSELAESMAC_HASH_MOD = 0
, CRYPTO_HASHSELAESMAC_HASHSELAESMAC_MAC_MOD = 1
} |
| |
| enum | CRYPTO_HASHCONTROL_MODE01_Enum { CRYPTO_HASHCONTROL_MODE01_MD5 = 0
, CRYPTO_HASHCONTROL_MODE01_SHA_1 = 1
, CRYPTO_HASHCONTROL_MODE01_SHA_256 = 2
} |
| |
| enum | CRYPTO_AESCLKENABLE_EN_Enum { CRYPTO_AESCLKENABLE_EN_CLK_E = 1
, CRYPTO_AESCLKENABLE_EN_CLK_D = 0
} |
| |
| enum | CRYPTO_HASHCLKENABLE_EN_Enum { CRYPTO_HASHCLKENABLE_EN_HASH_E = 1
, CRYPTO_HASHCLKENABLE_EN_HASH_D = 0
} |
| |
| enum | CRYPTO_PKACLKENABLE_EN_Enum { CRYPTO_PKACLKENABLE_EN_PKA_E = 1
, CRYPTO_PKACLKENABLE_EN_PKA_D = 0
} |
| |
| enum | CRYPTO_DMACLKENABLE_EN_Enum { CRYPTO_DMACLKENABLE_EN_DMA_E = 1
, CRYPTO_DMACLKENABLE_EN_DMA_D = 0
} |
| |
| enum | CRYPTO_CLKSTATUS_DMACLKSTATUS_Enum { CRYPTO_CLKSTATUS_DMACLKSTATUS_DMA_E = 1
, CRYPTO_CLKSTATUS_DMACLKSTATUS_DMA_D = 0
} |
| |
| enum | CRYPTO_CLKSTATUS_CHACHACLKSTATUS_Enum { CRYPTO_CLKSTATUS_CHACHACLKSTATUS_CHACHA_E = 1
, CRYPTO_CLKSTATUS_CHACHACLKSTATUS_CHACHA_D = 0
} |
| |
| enum | CRYPTO_CLKSTATUS_PKACLKSTATUS_Enum { CRYPTO_CLKSTATUS_PKACLKSTATUS_PKA_E = 1
, CRYPTO_CLKSTATUS_PKACLKSTATUS_PKA_D = 0
} |
| |
| enum | CRYPTO_CLKSTATUS_HASHCLKSTATUS_Enum { CRYPTO_CLKSTATUS_HASHCLKSTATUS_HASH_E = 1
, CRYPTO_CLKSTATUS_HASHCLKSTATUS_HASH_D = 0
} |
| |
| enum | CRYPTO_CLKSTATUS_AESCLKSTATUS_Enum { CRYPTO_CLKSTATUS_AESCLKSTATUS_CLK_E = 1
, CRYPTO_CLKSTATUS_AESCLKSTATUS_CLK_D = 0
} |
| |
| enum | CRYPTO_CHACHACLKENABLE_EN_Enum { CRYPTO_CHACHACLKENABLE_EN_CHACHA_E = 1
, CRYPTO_CHACHACLKENABLE_EN_CHACHA_D = 0
} |
| |
| enum | CRYPTO_CRYPTOCTL_MODE_Enum {
CRYPTO_CRYPTOCTL_MODE_BYPASS = 0
, CRYPTO_CRYPTOCTL_MODE_AES = 1
, CRYPTO_CRYPTOCTL_MODE_AES_TO_HASH = 2
, CRYPTO_CRYPTOCTL_MODE_AES_AND_HASH = 3
,
CRYPTO_CRYPTOCTL_MODE_DES = 4
, CRYPTO_CRYPTOCTL_MODE_DES_TO_HASH = 5
, CRYPTO_CRYPTOCTL_MODE_DES_AND_HASH = 6
, CRYPTO_CRYPTOCTL_MODE_HASH = 7
,
CRYPTO_CRYPTOCTL_MODE_AES_MAC_AND_BYPASS = 9
, CRYPTO_CRYPTOCTL_MODE_AES_TO_HASH_AND_DOUT = 10
, CRYPTO_CRYPTOCTL_MODE_Reserved1 = 11
, CRYPTO_CRYPTOCTL_MODE_Reserved2 = 8
} |
| |
| enum | CRYPTO_CRYPTOBUSY_CRYPTOBUSY_Enum { CRYPTO_CRYPTOBUSY_CRYPTOBUSY_READY = 0
, CRYPTO_CRYPTOBUSY_CRYPTOBUSY_BUSY = 1
} |
| |
| enum | CRYPTO_HASHBUSY_HASHBUSY_Enum { CRYPTO_HASHBUSY_HASHBUSY_READY = 0
, CRYPTO_HASHBUSY_HASHBUSY_BUSY = 1
} |
| |
| enum | CRYPTO_HOSTRGFENDIAN_DINRDWBG_Enum { CRYPTO_HOSTRGFENDIAN_DINRDWBG_LE = 0
, CRYPTO_HOSTRGFENDIAN_DINRDWBG_BE = 1
} |
| |
| enum | CRYPTO_HOSTRGFENDIAN_DOUTWRWBG_Enum { CRYPTO_HOSTRGFENDIAN_DOUTWRWBG_LE = 0
, CRYPTO_HOSTRGFENDIAN_DOUTWRWBG_BE = 1
} |
| |
| enum | CRYPTO_HOSTRGFENDIAN_DINRDBG_Enum { CRYPTO_HOSTRGFENDIAN_DINRDBG_LE = 0
, CRYPTO_HOSTRGFENDIAN_DINRDBG_BE = 1
} |
| |
| enum | CRYPTO_HOSTRGFENDIAN_DOUTWRBG_Enum { CRYPTO_HOSTRGFENDIAN_DOUTWRBG_LE = 0
, CRYPTO_HOSTRGFENDIAN_DOUTWRBG_BE = 1
} |
| |
| enum | CRYPTO_HOSTCRYPTOKEYSEL_SELCRYPTOKEY_Enum {
CRYPTO_HOSTCRYPTOKEYSEL_SELCRYPTOKEY_RKEK = 0
, CRYPTO_HOSTCRYPTOKEYSEL_SELCRYPTOKEY_Krtl = 1
, CRYPTO_HOSTCRYPTOKEYSEL_SELCRYPTOKEY_KCP = 2
, CRYPTO_HOSTCRYPTOKEYSEL_SELCRYPTOKEY_KCE = 3
,
CRYPTO_HOSTCRYPTOKEYSEL_SELCRYPTOKEY_KPICV = 4
, CRYPTO_HOSTCRYPTOKEYSEL_SELCRYPTOKEY_KCEICV = 5
} |
| |
| enum | CRYPTO_DINMEMDMABUSY_DINMEMDMABUSY_Enum { CRYPTO_DINMEMDMABUSY_DINMEMDMABUSY_busy = 1
, CRYPTO_DINMEMDMABUSY_DINMEMDMABUSY_not = 0
} |
| |
| enum | CRYPTO_DINSRAMDMABUSY_BUSY_Enum { CRYPTO_DINSRAMDMABUSY_BUSY_BUSY = 1
, CRYPTO_DINSRAMDMABUSY_BUSY_NOT_BUSY = 0
} |
| |
| enum | CRYPTO_DINSRAMENDIANNESS_SRAMDINENDIANNESS_Enum { CRYPTO_DINSRAMENDIANNESS_SRAMDINENDIANNESS_BE = 1
, CRYPTO_DINSRAMENDIANNESS_SRAMDINENDIANNESS_LE = 0
} |
| |
| enum | CRYPTO_DOUTMEMDMABUSY_DOUTMEMDMABUSY_Enum { CRYPTO_DOUTMEMDMABUSY_DOUTMEMDMABUSY_BUSY = 1
, CRYPTO_DOUTMEMDMABUSY_DOUTMEMDMABUSY_NOT_BUSY = 0
} |
| |
| enum | CRYPTO_DOUTSRAMDMABUSY_BUSY_Enum { CRYPTO_DOUTSRAMDMABUSY_BUSY_DATA_SRAM = 0
, CRYPTO_DOUTSRAMDMABUSY_BUSY_DMA_BUSY = 1
} |
| |
| enum | CRYPTO_DOUTSRAMENDIANNESS_DOUTSRAMENDIANNESS_Enum { CRYPTO_DOUTSRAMENDIANNESS_DOUTSRAMENDIANNESS_BE = 1
, CRYPTO_DOUTSRAMENDIANNESS_DOUTSRAMENDIANNESS_LE = 0
} |
| |
| enum | CRYPTO_DOUTFIFOEMPTY_DOUTFIFOEMPTY_Enum { CRYPTO_DOUTFIFOEMPTY_DOUTFIFOEMPTY_FIFO_NE = 0
, CRYPTO_DOUTFIFOEMPTY_DOUTFIFOEMPTY_FIFO_EDOUT = 1
} |
| |
| enum | CRYPTO_NVMDEBUGSTATUS_NVMSM_Enum {
CRYPTO_NVMDEBUGSTATUS_NVMSM_IDLE = 0
, CRYPTO_NVMDEBUGSTATUS_NVMSM_READ_DUMMY = 1
, CRYPTO_NVMDEBUGSTATUS_NVMSM_READ_MAN_FLAG = 2
, CRYPTO_NVMDEBUGSTATUS_NVMSM_READ_OEM_FLAG = 3
,
CRYPTO_NVMDEBUGSTATUS_NVMSM_READ_GPPC = 4
, CRYPTO_NVMDEBUGSTATUS_NVMSM_DECODE = 5
, CRYPTO_NVMDEBUGSTATUS_NVMSM_OTP_LCS_VALID = 6
, CRYPTO_NVMDEBUGSTATUS_NVMSM_LCS_IS_VALID = 7
} |
| |
| enum | CRYPTO_LCSREG_LCSREG_Enum { CRYPTO_LCSREG_LCSREG_CM = 0
, CRYPTO_LCSREG_LCSREG_DM = 1
, CRYPTO_LCSREG_LCSREG_SE = 5
, CRYPTO_LCSREG_LCSREG_RMA = 7
} |
| |
| enum | DC_MODE_VSYNCPOL_Enum { DC_MODE_VSYNCPOL_VSYNC_NEG = 1
, DC_MODE_VSYNCPOL_VSYNC_POS = 0
} |
| |
| enum | DC_MODE_HSYNCPOL_Enum { DC_MODE_HSYNCPOL_HSYNC_NEG = 1
, DC_MODE_HSYNCPOL_HSYNC_POS = 0
} |
| |
| enum | DC_MODE_DEPOL_Enum { DC_MODE_DEPOL_DE_NEG = 1
, DC_MODE_DEPOL_DE_POS = 0
} |
| |
| enum | DC_MODE_PIXCLKPOL_Enum { DC_MODE_PIXCLKPOL_POL_NEG = 1
, DC_MODE_PIXCLKPOL_POL_POS = 0
} |
| |
| enum | DC_MODE_COLFMT_Enum { DC_MODE_COLFMT_YUV_EN = 1
, DC_MODE_COLFMT_RGB_EN = 0
} |
| |
| enum | DC_MODE_DISPFMT_Enum {
DC_MODE_DISPFMT_DPI = 0
, DC_MODE_DISPFMT_BYTE3 = 1
, DC_MODE_DISPFMT_BYTE4 = 2
, DC_MODE_DISPFMT_SERIAL = 3
,
DC_MODE_DISPFMT_LVDS2 = 4
, DC_MODE_DISPFMT_LVDS1 = 5
, DC_MODE_DISPFMT_YUYV = 6
, DC_MODE_DISPFMT_BT656 = 7
,
DC_MODE_DISPFMT_JDI = 8
} |
| |
| enum | DC_CLKCTRL_SECCLKDIV_Enum {
DC_CLKCTRL_SECCLKDIV_SDIV_0 = 0
, DC_CLKCTRL_SECCLKDIV_SDIV_1 = 1
, DC_CLKCTRL_SECCLKDIV_SDIV_2 = 2
, DC_CLKCTRL_SECCLKDIV_SDIV_3 = 3
,
DC_CLKCTRL_SECCLKDIV_SDIV_4 = 4
, DC_CLKCTRL_SECCLKDIV_SDIV_5 = 5
, DC_CLKCTRL_SECCLKDIV_SDIV_6 = 6
, DC_CLKCTRL_SECCLKDIV_SDIV_7 = 7
,
DC_CLKCTRL_SECCLKDIV_SDIV_8 = 8
, DC_CLKCTRL_SECCLKDIV_SDIV_9 = 9
, DC_CLKCTRL_SECCLKDIV_SDIV_10 = 10
, DC_CLKCTRL_SECCLKDIV_SDIV_11 = 11
,
DC_CLKCTRL_SECCLKDIV_SDIV_12 = 12
, DC_CLKCTRL_SECCLKDIV_SDIV_13 = 13
, DC_CLKCTRL_SECCLKDIV_SDIV_14 = 14
, DC_CLKCTRL_SECCLKDIV_SDIV_15 = 15
} |
| |
| enum | DC_CLKCTRL_DIVIDEVALUE_Enum {
DC_CLKCTRL_DIVIDEVALUE_FDIV_0 = 0
, DC_CLKCTRL_DIVIDEVALUE_FDIV_2 = 2
, DC_CLKCTRL_DIVIDEVALUE_FDIV_3 = 3
, DC_CLKCTRL_DIVIDEVALUE_FDIV_4 = 4
,
DC_CLKCTRL_DIVIDEVALUE_FDIV_5 = 5
, DC_CLKCTRL_DIVIDEVALUE_FDIV_6 = 6
, DC_CLKCTRL_DIVIDEVALUE_FDIV_7 = 7
, DC_CLKCTRL_DIVIDEVALUE_FDIV_8 = 8
,
DC_CLKCTRL_DIVIDEVALUE_FDIV_9 = 9
, DC_CLKCTRL_DIVIDEVALUE_FDIV_10 = 10
, DC_CLKCTRL_DIVIDEVALUE_FDIV_11 = 11
, DC_CLKCTRL_DIVIDEVALUE_FDIV_12 = 12
,
DC_CLKCTRL_DIVIDEVALUE_FDIV_13 = 13
, DC_CLKCTRL_DIVIDEVALUE_FDIV_14 = 14
, DC_CLKCTRL_DIVIDEVALUE_FDIV_15 = 15
, DC_CLKCTRL_DIVIDEVALUE_FDIV_16 = 16
,
DC_CLKCTRL_DIVIDEVALUE_FDIV_17 = 17
, DC_CLKCTRL_DIVIDEVALUE_FDIV_18 = 18
, DC_CLKCTRL_DIVIDEVALUE_FDIV_19 = 19
, DC_CLKCTRL_DIVIDEVALUE_FDIV_20 = 20
,
DC_CLKCTRL_DIVIDEVALUE_FDIV_21 = 21
, DC_CLKCTRL_DIVIDEVALUE_FDIV_22 = 22
, DC_CLKCTRL_DIVIDEVALUE_FDIV_23 = 23
, DC_CLKCTRL_DIVIDEVALUE_FDIV_24 = 24
,
DC_CLKCTRL_DIVIDEVALUE_FDIV_25 = 25
, DC_CLKCTRL_DIVIDEVALUE_FDIV_26 = 26
, DC_CLKCTRL_DIVIDEVALUE_FDIV_27 = 27
, DC_CLKCTRL_DIVIDEVALUE_FDIV_28 = 28
,
DC_CLKCTRL_DIVIDEVALUE_FDIV_29 = 29
, DC_CLKCTRL_DIVIDEVALUE_FDIV_30 = 30
, DC_CLKCTRL_DIVIDEVALUE_FDIV_31 = 31
} |
| |
| enum | DC_DBICFG_CSXSET_Enum { DC_DBICFG_CSXSET_CSX1 = 1
, DC_DBICFG_CSXSET_CSX0 = 0
} |
| |
| enum | DC_DBICFG_TYPEBWIDTH_Enum { DC_DBICFG_TYPEBWIDTH_INT_16 = 0
, DC_DBICFG_TYPEBWIDTH_INT_9 = 1
, DC_DBICFG_TYPEBWIDTH_INT_8 = 2
, DC_DBICFG_TYPEBWIDTH_INT_SERIAL = 3
} |
| |
| enum | DC_DBICFG_DATAWDORDER_Enum { DC_DBICFG_DATAWDORDER_WD_ORDER_OPT0 = 0
, DC_DBICFG_DATAWDORDER_WD_ORDER_OPT1 = 1
, DC_DBICFG_DATAWDORDER_WD_ORDER_OPT2 = 2
, DC_DBICFG_DATAWDORDER_WD_ORDER_OPT3 = 3
} |
| |
| enum | DC_DBICFG_DBICOLORFMT_Enum {
DC_DBICFG_DBICOLORFMT_DBI_FMT_RGB111 = 1
, DC_DBICFG_DBICOLORFMT_DBI_FMT_RGB332 = 2
, DC_DBICFG_DBICOLORFMT_DBI_FMT_RGB444 = 3
, DC_DBICFG_DBICOLORFMT_DBI_FMT_RGB565 = 5
,
DC_DBICFG_DBICOLORFMT_DBI_FMT_RGB666 = 6
, DC_DBICFG_DBICOLORFMT_DBI_FMT_RGB888 = 7
} |
| |
| enum | DC_LAYER0MODE_LAYER0DBLEND_Enum {
DC_LAYER0MODE_LAYER0DBLEND_LAYER0_DBLACK_BLEND = 0
, DC_LAYER0MODE_LAYER0DBLEND_LAYER0_DWHITE_BLEND = 1
, DC_LAYER0MODE_LAYER0DBLEND_LAYER0_DALBHAS_BLEND = 2
, DC_LAYER0MODE_LAYER0DBLEND_LAYER0_DALPHAG_BLEND = 3
,
DC_LAYER0MODE_LAYER0DBLEND_LAYER0_DALPHASG_BLEND = 4
, DC_LAYER0MODE_LAYER0DBLEND_LAYER0_DINVERT_BLEND_SRC = 5
, DC_LAYER0MODE_LAYER0DBLEND_LAYER0_DINVERT_GLOBAL_BLEND = 6
, DC_LAYER0MODE_LAYER0DBLEND_LAYER0_DINVERTSG_BLEND = 7
,
DC_LAYER0MODE_LAYER0DBLEND_LAYER0_DALPHA_BLEND = 10
, DC_LAYER0MODE_LAYER0DBLEND_LAYER0_DINVERT_BLEND_DST = 13
} |
| |
| enum | DC_LAYER0MODE_LAYER0SBLEND_Enum {
DC_LAYER0MODE_LAYER0SBLEND_LAYER0_SBLACK_BLEND = 0
, DC_LAYER0MODE_LAYER0SBLEND_LAYER0_SWHITE_BLEND = 1
, DC_LAYER0MODE_LAYER0SBLEND_LAYER0_SALBHAS_BLEND = 2
, DC_LAYER0MODE_LAYER0SBLEND_LAYER0_SALPHAG_BLEND = 3
,
DC_LAYER0MODE_LAYER0SBLEND_LAYER0_SALPHASG_BLEND = 4
, DC_LAYER0MODE_LAYER0SBLEND_LAYER0_SINVERT_BLEND_SRC = 5
, DC_LAYER0MODE_LAYER0SBLEND_LAYER0_SINVERT_GLOBAL_BLEND = 6
, DC_LAYER0MODE_LAYER0SBLEND_LAYER0_SINVERTSG_BLEND = 7
,
DC_LAYER0MODE_LAYER0SBLEND_LAYER0_SALPHA_BLEND = 10
, DC_LAYER0MODE_LAYER0SBLEND_LAYER0_SINVERT_BLEND_DST = 13
} |
| |
| enum | DC_LAYER0MODE_LAYER0COLMODE_Enum {
DC_LAYER0MODE_LAYER0COLMODE_LAYER0CM_LUTBLE = 0
, DC_LAYER0MODE_LAYER0COLMODE_LAYER0CM_RGBX5551 = 1
, DC_LAYER0MODE_LAYER0COLMODE_LAYER0CM_RGBX8888 = 2
, DC_LAYER0MODE_LAYER0COLMODE_LAYER0CM_RGB332 = 4
,
DC_LAYER0MODE_LAYER0COLMODE_LAYER0CM_RGB565 = 5
, DC_LAYER0MODE_LAYER0COLMODE_LAYER0CM_XRGB8888 = 6
, DC_LAYER0MODE_LAYER0COLMODE_LAYER0CM_L8 = 7
, DC_LAYER0MODE_LAYER0COLMODE_LAYER0CM_L1 = 8
,
DC_LAYER0MODE_LAYER0COLMODE_LAYER0CM_L4 = 9
, DC_LAYER0MODE_LAYER0COLMODE_LAYER0CM_YUYV = 10
, DC_LAYER0MODE_LAYER0COLMODE_LAYER0CM_RBG = 11
, DC_LAYER0MODE_LAYER0COLMODE_LAYER0CM_YUY2 = 12
,
DC_LAYER0MODE_LAYER0COLMODE_LAYER0CM_ABGR8888 = 13
, DC_LAYER0MODE_LAYER0COLMODE_LAYER0CM_BGRA8888 = 14
, DC_LAYER0MODE_LAYER0COLMODE_LAYER0CM_Video = 16
, DC_LAYER0MODE_LAYER0COLMODE_LAYER0CM_Trilinear = 17
} |
| |
| enum | DC_LAYER0STRIDE_LAYER0AXIFIFOTHLD_Enum { DC_LAYER0STRIDE_LAYER0AXIFIFOTHLD_LAYER0_BURST_HALF_SZ = 0
, DC_LAYER0STRIDE_LAYER0AXIFIFOTHLD_LAYER0_BURST_2 = 1
, DC_LAYER0STRIDE_LAYER0AXIFIFOTHLD_LAYER0_BURST_4 = 2
, DC_LAYER0STRIDE_LAYER0AXIFIFOTHLD_LAYER0_BURST_8 = 3
} |
| |
| enum | DC_LAYER0STRIDE_LAYER0AXIBURSTBITS_Enum {
DC_LAYER0STRIDE_LAYER0AXIBURSTBITS_LAYER0_BEATS_DEF = 0
, DC_LAYER0STRIDE_LAYER0AXIBURSTBITS_LAYER0_BEATS_2 = 1
, DC_LAYER0STRIDE_LAYER0AXIBURSTBITS_LAYER0_BEATS_4 = 2
, DC_LAYER0STRIDE_LAYER0AXIBURSTBITS_LAYER0_BEATS_8 = 3
,
DC_LAYER0STRIDE_LAYER0AXIBURSTBITS_LAYER0_BEATS_16 = 4
, DC_LAYER0STRIDE_LAYER0AXIBURSTBITS_LAYER0_BEATS_32 = 5
, DC_LAYER0STRIDE_LAYER0AXIBURSTBITS_LAYER0_BEATS_64 = 6
, DC_LAYER0STRIDE_LAYER0AXIBURSTBITS_LAYER0_BEATS_128 = 7
} |
| |
| enum | DC_LAYER1MODE_LAYER1DBLEND_Enum {
DC_LAYER1MODE_LAYER1DBLEND_LAYER1_DBLACK_BLEND = 0
, DC_LAYER1MODE_LAYER1DBLEND_LAYER1_DWHITE_BLEND = 1
, DC_LAYER1MODE_LAYER1DBLEND_LAYER1_DALBHAS_BLEND = 2
, DC_LAYER1MODE_LAYER1DBLEND_LAYER1_DALPHAG_BLEND = 3
,
DC_LAYER1MODE_LAYER1DBLEND_LAYER1_DALPHASG_BLEND = 4
, DC_LAYER1MODE_LAYER1DBLEND_LAYER1_DINVERT_BLEND_SRC = 5
, DC_LAYER1MODE_LAYER1DBLEND_LAYER1_DINVERT_GLOBAL_BLEND = 6
, DC_LAYER1MODE_LAYER1DBLEND_LAYER1_DINVERTSG_BLEND = 7
,
DC_LAYER1MODE_LAYER1DBLEND_LAYER1_DALPHA_BLEND = 10
, DC_LAYER1MODE_LAYER1DBLEND_LAYER1_DINVERT_BLEND_DST = 13
} |
| |
| enum | DC_LAYER1MODE_LAYER1SBLEND_Enum {
DC_LAYER1MODE_LAYER1SBLEND_LAYER1_SBLACK_BLEND = 0
, DC_LAYER1MODE_LAYER1SBLEND_LAYER1_SWHITE_BLEND = 1
, DC_LAYER1MODE_LAYER1SBLEND_LAYER1_SALBHAS_BLEND = 2
, DC_LAYER1MODE_LAYER1SBLEND_LAYER1_SALPHAG_BLEND = 3
,
DC_LAYER1MODE_LAYER1SBLEND_LAYER1_SALPHASG_BLEND = 4
, DC_LAYER1MODE_LAYER1SBLEND_LAYER1_SINVERT_BLEND_SRC = 5
, DC_LAYER1MODE_LAYER1SBLEND_LAYER1_SINVERT_GLOBAL_BLEND = 6
, DC_LAYER1MODE_LAYER1SBLEND_LAYER1_SINVERTSG_BLEND = 7
,
DC_LAYER1MODE_LAYER1SBLEND_LAYER1_SALPHA_BLEND = 10
, DC_LAYER1MODE_LAYER1SBLEND_LAYER1_SINVERT_BLEND_DST = 13
} |
| |
| enum | DC_LAYER1MODE_LAYER1COLORMODE_Enum {
DC_LAYER1MODE_LAYER1COLORMODE_LAYER1_LUTBLE = 0
, DC_LAYER1MODE_LAYER1COLORMODE_LAYER1_RGBX5551 = 1
, DC_LAYER1MODE_LAYER1COLORMODE_LAYER1_RGBX8888 = 2
, DC_LAYER1MODE_LAYER1COLORMODE_LAYER1_RGB332 = 4
,
DC_LAYER1MODE_LAYER1COLORMODE_LAYER1_RGB565 = 5
, DC_LAYER1MODE_LAYER1COLORMODE_LAYER1_XRGB8888 = 6
, DC_LAYER1MODE_LAYER1COLORMODE_LAYER1_L8 = 7
, DC_LAYER1MODE_LAYER1COLORMODE_LAYER1_L1 = 8
,
DC_LAYER1MODE_LAYER1COLORMODE_LAYER1_L4 = 9
, DC_LAYER1MODE_LAYER1COLORMODE_LAYER1_YUYV = 10
, DC_LAYER1MODE_LAYER1COLORMODE_LAYER1_RGB = 11
, DC_LAYER1MODE_LAYER1COLORMODE_LAYER1_YUY2 = 12
,
DC_LAYER1MODE_LAYER1COLORMODE_LAYER1_ABGR8888 = 13
, DC_LAYER1MODE_LAYER1COLORMODE_LAYER1_BGRA8888 = 14
, DC_LAYER1MODE_LAYER1COLORMODE_LAYER1_VIDEO420 = 16
, DC_LAYER1MODE_LAYER1COLORMODE_LAYER1_TRILIN420 = 17
} |
| |
| enum | DC_LAYER1STRIDE_LAYER1AXIFIFOTHLD_Enum { DC_LAYER1STRIDE_LAYER1AXIFIFOTHLD_LAYER1_BURST_HALF_SZ = 0
, DC_LAYER1STRIDE_LAYER1AXIFIFOTHLD_LAYER1_BURST_2 = 1
, DC_LAYER1STRIDE_LAYER1AXIFIFOTHLD_LAYER1_BURST_4 = 2
, DC_LAYER1STRIDE_LAYER1AXIFIFOTHLD_LAYER1_BURST_8 = 3
} |
| |
| enum | DC_LAYER1STRIDE_LAYER1AXIBURSTBITS_Enum {
DC_LAYER1STRIDE_LAYER1AXIBURSTBITS_LAYER1_BEATS_DEF = 0
, DC_LAYER1STRIDE_LAYER1AXIBURSTBITS_LAYER1_BEATS_2 = 1
, DC_LAYER1STRIDE_LAYER1AXIBURSTBITS_LAYER1_BEATS_4 = 2
, DC_LAYER1STRIDE_LAYER1AXIBURSTBITS_LAYER1_BEATS_8 = 3
,
DC_LAYER1STRIDE_LAYER1AXIBURSTBITS_LAYER1_BEATS_16 = 4
, DC_LAYER1STRIDE_LAYER1AXIBURSTBITS_LAYER1_BEATS_32 = 5
, DC_LAYER1STRIDE_LAYER1AXIBURSTBITS_LAYER1_BEATS_64 = 6
, DC_LAYER1STRIDE_LAYER1AXIBURSTBITS_LAYER1_BEATS_128 = 7
} |
| |
| enum | DC_LAYER2MODE_LAYER2DBLEND_Enum {
DC_LAYER2MODE_LAYER2DBLEND_LAYER2_DBLACK_BLEND = 0
, DC_LAYER2MODE_LAYER2DBLEND_LAYER2_DWHITE_BLEND = 1
, DC_LAYER2MODE_LAYER2DBLEND_LAYER2_DALBHAS_BLEND = 2
, DC_LAYER2MODE_LAYER2DBLEND_LAYER2_DALPHAG_BLEND = 3
,
DC_LAYER2MODE_LAYER2DBLEND_LAYER2_DALPHASG_BLEND = 4
, DC_LAYER2MODE_LAYER2DBLEND_LAYER2_DINVERT_BLEND_SRC = 5
, DC_LAYER2MODE_LAYER2DBLEND_LAYER2_DINVERT_GLOBAL_BLEND = 6
, DC_LAYER2MODE_LAYER2DBLEND_LAYER2_DINVERTSG_BLEND = 7
,
DC_LAYER2MODE_LAYER2DBLEND_LAYER2_DALPHA_BLEND = 10
, DC_LAYER2MODE_LAYER2DBLEND_LAYER2_DINVERT_BLEND_DST = 13
} |
| |
| enum | DC_LAYER2MODE_LAYER2SBLEND_Enum {
DC_LAYER2MODE_LAYER2SBLEND_LAYER2_SBLACK_BLEND = 0
, DC_LAYER2MODE_LAYER2SBLEND_LAYER2_SWHITE_BLEND = 1
, DC_LAYER2MODE_LAYER2SBLEND_LAYER2_SALBHAS_BLEND = 2
, DC_LAYER2MODE_LAYER2SBLEND_LAYER2_SALPHAG_BLEND = 3
,
DC_LAYER2MODE_LAYER2SBLEND_LAYER2_SALPHASG_BLEND = 4
, DC_LAYER2MODE_LAYER2SBLEND_LAYER2_SINVERT_BLEND_SRC = 5
, DC_LAYER2MODE_LAYER2SBLEND_LAYER2_SINVERT_GLOBAL_BLEND = 6
, DC_LAYER2MODE_LAYER2SBLEND_LAYER2_SINVERTSG_BLEND = 7
,
DC_LAYER2MODE_LAYER2SBLEND_LAYER2_SALPHA_BLEND = 10
, DC_LAYER2MODE_LAYER2SBLEND_LAYER2_SINVERT_BLEND_DST = 13
} |
| |
| enum | DC_LAYER2MODE_LAYER2COLORMODE_Enum {
DC_LAYER2MODE_LAYER2COLORMODE_LAYER2_LUTBLE = 0
, DC_LAYER2MODE_LAYER2COLORMODE_LAYER2_RGBX5551 = 1
, DC_LAYER2MODE_LAYER2COLORMODE_LAYER2_RGBX8888 = 2
, DC_LAYER2MODE_LAYER2COLORMODE_LAYER2_RGB332 = 4
,
DC_LAYER2MODE_LAYER2COLORMODE_LAYER2_RGB565 = 5
, DC_LAYER2MODE_LAYER2COLORMODE_LAYER2_XRGB8888 = 6
, DC_LAYER2MODE_LAYER2COLORMODE_LAYER2_L8 = 7
, DC_LAYER2MODE_LAYER2COLORMODE_LAYER2_L1 = 8
,
DC_LAYER2MODE_LAYER2COLORMODE_LAYER2_L4 = 9
, DC_LAYER2MODE_LAYER2COLORMODE_LAYER2_YUYV = 10
, DC_LAYER2MODE_LAYER2COLORMODE_LAYER2_RGB = 11
, DC_LAYER2MODE_LAYER2COLORMODE_LAYER2_YUY2 = 12
,
DC_LAYER2MODE_LAYER2COLORMODE_LAYER2_ABGR8888 = 13
, DC_LAYER2MODE_LAYER2COLORMODE_LAYER2_BGRA8888 = 14
, DC_LAYER2MODE_LAYER2COLORMODE_LAYER2_VIDEO420 = 16
, DC_LAYER2MODE_LAYER2COLORMODE_LAYER2_TRILIN420 = 17
} |
| |
| enum | DC_LAYER2STRIDE_LAYER2AXIFIFOTHLD_Enum { DC_LAYER2STRIDE_LAYER2AXIFIFOTHLD_LAYER2_BURST_HALF_SZ = 0
, DC_LAYER2STRIDE_LAYER2AXIFIFOTHLD_LAYER2_BURST_2 = 1
, DC_LAYER2STRIDE_LAYER2AXIFIFOTHLD_LAYER2_BURST_4 = 2
, DC_LAYER2STRIDE_LAYER2AXIFIFOTHLD_LAYER2_BURST_8 = 3
} |
| |
| enum | DC_LAYER2STRIDE_LAYER2AXIBURSTBITS_Enum {
DC_LAYER2STRIDE_LAYER2AXIBURSTBITS_LAYER2_BEATS_DEF = 0
, DC_LAYER2STRIDE_LAYER2AXIBURSTBITS_LAYER2_BEATS_2 = 1
, DC_LAYER2STRIDE_LAYER2AXIBURSTBITS_LAYER2_BEATS_4 = 2
, DC_LAYER2STRIDE_LAYER2AXIBURSTBITS_LAYER2_BEATS_8 = 3
,
DC_LAYER2STRIDE_LAYER2AXIBURSTBITS_LAYER2_BEATS_16 = 4
, DC_LAYER2STRIDE_LAYER2AXIBURSTBITS_LAYER2_BEATS_32 = 5
, DC_LAYER2STRIDE_LAYER2AXIBURSTBITS_LAYER2_BEATS_64 = 6
, DC_LAYER2STRIDE_LAYER2AXIBURSTBITS_LAYER2_BEATS_128 = 7
} |
| |
| enum | DC_LAYER3MODE_LAYER3DBLEND_Enum {
DC_LAYER3MODE_LAYER3DBLEND_LAYER3_DBLACK_BLEND = 0
, DC_LAYER3MODE_LAYER3DBLEND_LAYER3_DWHITE_BLEND = 1
, DC_LAYER3MODE_LAYER3DBLEND_LAYER3_DALBHAS_BLEND = 2
, DC_LAYER3MODE_LAYER3DBLEND_LAYER3_DALPHAG_BLEND = 3
,
DC_LAYER3MODE_LAYER3DBLEND_LAYER3_DALPHASG_BLEND = 4
, DC_LAYER3MODE_LAYER3DBLEND_LAYER3_DINVERT_BLEND_SRC = 5
, DC_LAYER3MODE_LAYER3DBLEND_LAYER3_DINVERT_GLOBAL_BLEND = 6
, DC_LAYER3MODE_LAYER3DBLEND_LAYER3_DINVERTSG_BLEND = 7
,
DC_LAYER3MODE_LAYER3DBLEND_LAYER3_DALPHA_BLEND = 10
, DC_LAYER3MODE_LAYER3DBLEND_LAYER3_DINVERT_BLEND_DST = 13
} |
| |
| enum | DC_LAYER3MODE_LAYER3SBLEND_Enum {
DC_LAYER3MODE_LAYER3SBLEND_LAYER3SBLACKBLEND = 0
, DC_LAYER3MODE_LAYER3SBLEND_LAYER3SWHITEBLEND = 1
, DC_LAYER3MODE_LAYER3SBLEND_LAYER3SALBHASBLEND = 2
, DC_LAYER3MODE_LAYER3SBLEND_LAYER3SALPHAGBLEND = 3
,
DC_LAYER3MODE_LAYER3SBLEND_LAYER3SALPHASGBLEND = 4
, DC_LAYER3MODE_LAYER3SBLEND_LAYER3_SINVERT_BLEND_SRC = 5
, DC_LAYER3MODE_LAYER3SBLEND_LAYER3SINVERTGLOBALBLEND = 6
, DC_LAYER3MODE_LAYER3SBLEND_LAYER3SINVERTSGBLEND = 7
,
DC_LAYER3MODE_LAYER3SBLEND_LAYER3SALPHABLEND = 10
, DC_LAYER3MODE_LAYER3SBLEND_LAYER3_SINVERT_BLEND_DST = 13
} |
| |
| enum | DC_LAYER3MODE_LAYER3COLORMODE_Enum {
DC_LAYER3MODE_LAYER3COLORMODE_LAYER3_LUTBLE = 0
, DC_LAYER3MODE_LAYER3COLORMODE_LAYER3_RGBX5551 = 1
, DC_LAYER3MODE_LAYER3COLORMODE_LAYER3_RGBX8888 = 2
, DC_LAYER3MODE_LAYER3COLORMODE_LAYER3_RGB332 = 4
,
DC_LAYER3MODE_LAYER3COLORMODE_LAYER3_RGB565 = 5
, DC_LAYER3MODE_LAYER3COLORMODE_LAYER3_XRGB8888 = 6
, DC_LAYER3MODE_LAYER3COLORMODE_LAYER3_L8 = 7
, DC_LAYER3MODE_LAYER3COLORMODE_LAYER3_L1 = 8
,
DC_LAYER3MODE_LAYER3COLORMODE_LAYER3_L4 = 9
, DC_LAYER3MODE_LAYER3COLORMODE_LAYER3_YUYV = 10
, DC_LAYER3MODE_LAYER3COLORMODE_LAYER3_RGB = 11
, DC_LAYER3MODE_LAYER3COLORMODE_LAYER3_YUY2 = 12
,
DC_LAYER3MODE_LAYER3COLORMODE_LAYER3_ABGR8888 = 13
, DC_LAYER3MODE_LAYER3COLORMODE_LAYER3_BGRA8888 = 14
, DC_LAYER3MODE_LAYER3COLORMODE_LAYER3_VIDEO420 = 16
, DC_LAYER3MODE_LAYER3COLORMODE_LAYER3_TRILIN42 = 17
} |
| |
| enum | DC_LAYER3STRIDE_LAYER3AXIFIFOTHLD_Enum { DC_LAYER3STRIDE_LAYER3AXIFIFOTHLD_LAYER3_BURST_HALF_SZ = 0
, DC_LAYER3STRIDE_LAYER3AXIFIFOTHLD_LAYER3_BURST_2 = 1
, DC_LAYER3STRIDE_LAYER3AXIFIFOTHLD_LAYER3_BURST_4 = 2
, DC_LAYER3STRIDE_LAYER3AXIFIFOTHLD_LAYER3_BURST_8 = 3
} |
| |
| enum | DC_LAYER3STRIDE_LAYER3AXIBURSTBITS_Enum {
DC_LAYER3STRIDE_LAYER3AXIBURSTBITS_LAYER3_BEATS_DEF = 0
, DC_LAYER3STRIDE_LAYER3AXIBURSTBITS_LAYER3_BEATS_2 = 1
, DC_LAYER3STRIDE_LAYER3AXIBURSTBITS_LAYER3_BEATS_4 = 2
, DC_LAYER3STRIDE_LAYER3AXIBURSTBITS_LAYER3_BEATS_8 = 3
,
DC_LAYER3STRIDE_LAYER3AXIBURSTBITS_LAYER3_BEATS_16 = 4
, DC_LAYER3STRIDE_LAYER3AXIBURSTBITS_LAYER3_BEATS_32 = 5
, DC_LAYER3STRIDE_LAYER3AXIBURSTBITS_LAYER3_BEATS_64 = 6
, DC_LAYER3STRIDE_LAYER3AXIBURSTBITS_LAYER3_BEATS_128 = 7
} |
| |
| enum | DC_INTERRUPT_INTTRIGGER_Enum { DC_INTERRUPT_INTTRIGGER_LEVEL = 1
, DC_INTERRUPT_INTTRIGGER_EDGE = 0
} |
| |
| enum | DSI_DEVICEREADY_ULPS_Enum { DSI_DEVICEREADY_ULPS_LOW_POWER = 2
, DSI_DEVICEREADY_ULPS_EXIT = 1
, DSI_DEVICEREADY_ULPS_This = 0
} |
| |
| enum | DSI_DEVICEREADY_READY_Enum { DSI_DEVICEREADY_READY_PROGRAMMED = 1
, DSI_DEVICEREADY_READY_READY = 0
} |
| |
| enum | DSI_DSIFUNCPRG_REGNAME_Enum { DSI_DSIFUNCPRG_REGNAME_command = 0
, DSI_DSIFUNCPRG_REGNAME_16BIT = 1
, DSI_DSIFUNCPRG_REGNAME_9BIT = 2
, DSI_DSIFUNCPRG_REGNAME_8BIT = 3
} |
| |
| enum | DSI_DSIFUNCPRG_SUPCOLVIDMODE_Enum {
DSI_DSIFUNCPRG_SUPCOLVIDMODE_FMTVMODE0 = 0
, DSI_DSIFUNCPRG_SUPCOLVIDMODE_FMTVMODE1 = 1
, DSI_DSIFUNCPRG_SUPCOLVIDMODE_FMTVMODE2 = 2
, DSI_DSIFUNCPRG_SUPCOLVIDMODE_FMTVMODE3 = 3
,
DSI_DSIFUNCPRG_SUPCOLVIDMODE_FMTVMODE4 = 4
} |
| |
| enum | DSI_DSIFUNCPRG_CHNUMCMODE_Enum { DSI_DSIFUNCPRG_CHNUMCMODE_VCCH0 = 0
, DSI_DSIFUNCPRG_CHNUMCMODE_VCCH1 = 1
, DSI_DSIFUNCPRG_CHNUMCMODE_VCCH2 = 2
, DSI_DSIFUNCPRG_CHNUMCMODE_VCCH3 = 3
} |
| |
| enum | DSI_DSIFUNCPRG_CHNUMVM_Enum { DSI_DSIFUNCPRG_CHNUMVM_VVCH0 = 0
, DSI_DSIFUNCPRG_CHNUMVM_VVCH1 = 1
, DSI_DSIFUNCPRG_CHNUMVM_VVCH2 = 2
, DSI_DSIFUNCPRG_CHNUMVM_VVCH3 = 3
} |
| |
| enum | DSI_DSIFUNCPRG_DATALANES_Enum {
DSI_DSIFUNCPRG_DATALANES_DATAL0 = 0
, DSI_DSIFUNCPRG_DATALANES_DATAL1 = 1
, DSI_DSIFUNCPRG_DATALANES_DATAL2 = 2
, DSI_DSIFUNCPRG_DATALANES_DATAL3 = 3
,
DSI_DSIFUNCPRG_DATALANES_DATAL4 = 4
} |
| |
| enum | DSI_VIDEOMODEFMT_VIDEMDFMT_Enum { DSI_VIDEOMODEFMT_VIDEMDFMT_VIDEMDFMT_0 = 0
, DSI_VIDEOMODEFMT_VIDEMDFMT_NONBURSTPULSE = 1
, DSI_VIDEOMODEFMT_VIDEMDFMT_NONBURSTEVENTS = 2
, DSI_VIDEOMODEFMT_VIDEMDFMT_BURST = 3
} |
| |
| enum | DSI_POLARITY_PBITS_Enum { DSI_POLARITY_PBITS_POLV = 0
, DSI_POLARITY_PBITS_POLH = 1
, DSI_POLARITY_PBITS_POLSD = 2
, DSI_POLARITY_PBITS_POLCM = 3
} |
| |
| enum | DSI_MIPIDIRDPIDIFF_DPIHIGH_Enum { DSI_MIPIDIRDPIDIFF_DPIHIGH_LESSTHAN = 0
, DSI_MIPIDIRDPIDIFF_DPIHIGH_GREATER = 1
} |
| |
| enum | DSI_MIPIDIRDPIDIFF_MIPIDIR_Enum { DSI_MIPIDIRDPIDIFF_MIPIDIR_CONTROL = 0
, DSI_MIPIDIRDPIDIFF_MIPIDIR_RECEIVE = 1
} |
| |
| enum | DSI_DATALANEPOLSWAP_DATALNPOLSWAP_Enum {
DSI_DATALANEPOLSWAP_DATALNPOLSWAP_LANE0 = 1
, DSI_DATALANEPOLSWAP_DATALNPOLSWAP_LANE1 = 2
, DSI_DATALANEPOLSWAP_DATALNPOLSWAP_LANE2 = 4
, DSI_DATALANEPOLSWAP_DATALNPOLSWAP_LANE3 = 8
,
DSI_DATALANEPOLSWAP_DATALNPOLSWAP_ALLLANES = 15
} |
| |
| enum | DSP_MUTEX0_MUTEX0_Enum {
DSP_MUTEX0_MUTEX0_NONE = 0
, DSP_MUTEX0_MUTEX0_CPU = 1
, DSP_MUTEX0_MUTEX0_DSP0 = 2
, DSP_MUTEX0_MUTEX0_DSP1 = 4
,
DSP_MUTEX0_MUTEX0_CLEAR = 6
, DSP_MUTEX0_MUTEX0_SET = 7
} |
| |
| enum | DSP_MUTEX1_MUTEX1_Enum {
DSP_MUTEX1_MUTEX1_NONE = 0
, DSP_MUTEX1_MUTEX1_CPU = 1
, DSP_MUTEX1_MUTEX1_DSP0 = 2
, DSP_MUTEX1_MUTEX1_DSP1 = 4
,
DSP_MUTEX1_MUTEX1_CLEAR = 6
, DSP_MUTEX1_MUTEX1_SET = 7
} |
| |
| enum | DSP_MUTEX2_MUTEX2_Enum {
DSP_MUTEX2_MUTEX2_NONE = 0
, DSP_MUTEX2_MUTEX2_CPU = 1
, DSP_MUTEX2_MUTEX2_DSP0 = 2
, DSP_MUTEX2_MUTEX2_DSP1 = 4
,
DSP_MUTEX2_MUTEX2_CLEAR = 6
, DSP_MUTEX2_MUTEX2_SET = 7
} |
| |
| enum | DSP_MUTEX3_MUTEX3_Enum {
DSP_MUTEX3_MUTEX3_NONE = 0
, DSP_MUTEX3_MUTEX3_CPU = 1
, DSP_MUTEX3_MUTEX3_DSP0 = 2
, DSP_MUTEX3_MUTEX3_DSP1 = 4
,
DSP_MUTEX3_MUTEX3_CLEAR = 6
, DSP_MUTEX3_MUTEX3_SET = 7
} |
| |
| enum | DSP_MUTEX4_MUTEX4_Enum {
DSP_MUTEX4_MUTEX4_NONE = 0
, DSP_MUTEX4_MUTEX4_CPU = 1
, DSP_MUTEX4_MUTEX4_DSP0 = 2
, DSP_MUTEX4_MUTEX4_DSP1 = 4
,
DSP_MUTEX4_MUTEX4_CLEAR = 6
, DSP_MUTEX4_MUTEX4_SET = 7
} |
| |
| enum | DSP_MUTEX5_MUTEX5_Enum {
DSP_MUTEX5_MUTEX5_NONE = 0
, DSP_MUTEX5_MUTEX5_CPU = 1
, DSP_MUTEX5_MUTEX5_DSP0 = 2
, DSP_MUTEX5_MUTEX5_DSP1 = 4
,
DSP_MUTEX5_MUTEX5_CLEAR = 6
, DSP_MUTEX5_MUTEX5_SET = 7
} |
| |
| enum | DSP_MUTEX6_MUTEX6_Enum {
DSP_MUTEX6_MUTEX6_NONE = 0
, DSP_MUTEX6_MUTEX6_CPU = 1
, DSP_MUTEX6_MUTEX6_DSP0 = 2
, DSP_MUTEX6_MUTEX6_DSP1 = 4
,
DSP_MUTEX6_MUTEX6_CLEAR = 6
, DSP_MUTEX6_MUTEX6_SET = 7
} |
| |
| enum | DSP_MUTEX7_MUTEX7_Enum {
DSP_MUTEX7_MUTEX7_NONE = 0
, DSP_MUTEX7_MUTEX7_CPU = 1
, DSP_MUTEX7_MUTEX7_DSP0 = 2
, DSP_MUTEX7_MUTEX7_DSP1 = 4
,
DSP_MUTEX7_MUTEX7_CLEAR = 6
, DSP_MUTEX7_MUTEX7_SET = 7
} |
| |
| enum | DSP_DSP0CONTROL_DSP0IDMATRIG_Enum { DSP_DSP0CONTROL_DSP0IDMATRIG_XTRIG = 3
, DSP_DSP0CONTROL_DSP0IDMATRIG_SSTEP = 2
, DSP_DSP0CONTROL_DSP0IDMATRIG_AON = 1
, DSP_DSP0CONTROL_DSP0IDMATRIG_DISABLE = 0
} |
| |
| enum | DSP_DSP1CONTROL_DSP1IDMATRIG_Enum { DSP_DSP1CONTROL_DSP1IDMATRIG_XTRIG = 3
, DSP_DSP1CONTROL_DSP1IDMATRIG_SSTEP = 2
, DSP_DSP1CONTROL_DSP1IDMATRIG_AON = 1
, DSP_DSP1CONTROL_DSP1IDMATRIG_DISABLE = 0
} |
| |
| enum | GPIO_PINCFG0_NCEPOL0_Enum { GPIO_PINCFG0_NCEPOL0_LOW = 0
, GPIO_PINCFG0_NCEPOL0_HIGH = 1
} |
| |
| enum | GPIO_PINCFG0_NCESRC0_Enum {
GPIO_PINCFG0_NCESRC0_IOM0CE0 = 0
, GPIO_PINCFG0_NCESRC0_IOM0CE1 = 1
, GPIO_PINCFG0_NCESRC0_IOM0CE2 = 2
, GPIO_PINCFG0_NCESRC0_IOM0CE3 = 3
,
GPIO_PINCFG0_NCESRC0_IOM1CE0 = 4
, GPIO_PINCFG0_NCESRC0_IOM1CE1 = 5
, GPIO_PINCFG0_NCESRC0_IOM1CE2 = 6
, GPIO_PINCFG0_NCESRC0_IOM1CE3 = 7
,
GPIO_PINCFG0_NCESRC0_IOM2CE0 = 8
, GPIO_PINCFG0_NCESRC0_IOM2CE1 = 9
, GPIO_PINCFG0_NCESRC0_IOM2CE2 = 10
, GPIO_PINCFG0_NCESRC0_IOM2CE3 = 11
,
GPIO_PINCFG0_NCESRC0_IOM3CE0 = 12
, GPIO_PINCFG0_NCESRC0_IOM3CE1 = 13
, GPIO_PINCFG0_NCESRC0_IOM3CE2 = 14
, GPIO_PINCFG0_NCESRC0_IOM3CE3 = 15
,
GPIO_PINCFG0_NCESRC0_IOM4CE0 = 16
, GPIO_PINCFG0_NCESRC0_IOM4CE1 = 17
, GPIO_PINCFG0_NCESRC0_IOM4CE2 = 18
, GPIO_PINCFG0_NCESRC0_IOM4CE3 = 19
,
GPIO_PINCFG0_NCESRC0_IOM5CE0 = 20
, GPIO_PINCFG0_NCESRC0_IOM5CE1 = 21
, GPIO_PINCFG0_NCESRC0_IOM5CE2 = 22
, GPIO_PINCFG0_NCESRC0_IOM5CE3 = 23
,
GPIO_PINCFG0_NCESRC0_IOM6CE0 = 24
, GPIO_PINCFG0_NCESRC0_IOM6CE1 = 25
, GPIO_PINCFG0_NCESRC0_IOM6CE2 = 26
, GPIO_PINCFG0_NCESRC0_IOM6CE3 = 27
,
GPIO_PINCFG0_NCESRC0_IOM7CE0 = 28
, GPIO_PINCFG0_NCESRC0_IOM7CE1 = 29
, GPIO_PINCFG0_NCESRC0_IOM7CE2 = 30
, GPIO_PINCFG0_NCESRC0_IOM7CE3 = 31
,
GPIO_PINCFG0_NCESRC0_MSPI0CEN0 = 32
, GPIO_PINCFG0_NCESRC0_MSPI0CEN1 = 33
, GPIO_PINCFG0_NCESRC0_MSPI1CEN0 = 34
, GPIO_PINCFG0_NCESRC0_MSPI1CEN1 = 35
,
GPIO_PINCFG0_NCESRC0_MSPI2CEN0 = 36
, GPIO_PINCFG0_NCESRC0_MSPI2CEN1 = 37
, GPIO_PINCFG0_NCESRC0_DC_DPI_DE = 38
, GPIO_PINCFG0_NCESRC0_DISP_CONT_CSX = 39
,
GPIO_PINCFG0_NCESRC0_DC_SPI_CS_N = 40
, GPIO_PINCFG0_NCESRC0_DC_QSPI_CS_N = 41
, GPIO_PINCFG0_NCESRC0_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG0_PULLCFG0_Enum {
GPIO_PINCFG0_PULLCFG0_DIS = 0
, GPIO_PINCFG0_PULLCFG0_PD50K = 1
, GPIO_PINCFG0_PULLCFG0_PU15K = 2
, GPIO_PINCFG0_PULLCFG0_PU6K = 3
,
GPIO_PINCFG0_PULLCFG0_PU12K = 4
, GPIO_PINCFG0_PULLCFG0_PU24K = 5
, GPIO_PINCFG0_PULLCFG0_PU50K = 6
, GPIO_PINCFG0_PULLCFG0_PU100K = 7
} |
| |
| enum | GPIO_PINCFG0_DS0_Enum { GPIO_PINCFG0_DS0_0P1X = 0
, GPIO_PINCFG0_DS0_0P5X = 1
} |
| |
| enum | GPIO_PINCFG0_OUTCFG0_Enum { GPIO_PINCFG0_OUTCFG0_DIS = 0
, GPIO_PINCFG0_OUTCFG0_PUSHPULL = 1
, GPIO_PINCFG0_OUTCFG0_OD = 2
, GPIO_PINCFG0_OUTCFG0_TS = 3
} |
| |
| enum | GPIO_PINCFG0_IRPTEN0_Enum { GPIO_PINCFG0_IRPTEN0_DIS = 0
, GPIO_PINCFG0_IRPTEN0_INTFALL = 1
, GPIO_PINCFG0_IRPTEN0_INTRISE = 2
, GPIO_PINCFG0_IRPTEN0_INTANY = 3
} |
| |
| enum | GPIO_PINCFG0_FNCSEL0_Enum {
GPIO_PINCFG0_FNCSEL0_SWTRACECLK = 0
, GPIO_PINCFG0_FNCSEL0_SLSCL = 1
, GPIO_PINCFG0_FNCSEL0_SLSCK = 2
, GPIO_PINCFG0_FNCSEL0_GPIO = 3
,
GPIO_PINCFG0_FNCSEL0_UART0TX = 4
, GPIO_PINCFG0_FNCSEL0_UART1TX = 5
, GPIO_PINCFG0_FNCSEL0_CT0 = 6
, GPIO_PINCFG0_FNCSEL0_NCE0 = 7
,
GPIO_PINCFG0_FNCSEL0_OBSBUS0 = 8
, GPIO_PINCFG0_FNCSEL0_VCMPO = 9
, GPIO_PINCFG0_FNCSEL0_RESERVED10 = 10
, GPIO_PINCFG0_FNCSEL0_FPIO = 11
,
GPIO_PINCFG0_FNCSEL0_RESERVED12 = 12
, GPIO_PINCFG0_FNCSEL0_RESERVED13 = 13
, GPIO_PINCFG0_FNCSEL0_RESERVED14 = 14
, GPIO_PINCFG0_FNCSEL0_RESERVED15 = 15
} |
| |
| enum | GPIO_PINCFG1_NCEPOL1_Enum { GPIO_PINCFG1_NCEPOL1_LOW = 0
, GPIO_PINCFG1_NCEPOL1_HIGH = 1
} |
| |
| enum | GPIO_PINCFG1_NCESRC1_Enum {
GPIO_PINCFG1_NCESRC1_IOM0CE0 = 0
, GPIO_PINCFG1_NCESRC1_IOM0CE1 = 1
, GPIO_PINCFG1_NCESRC1_IOM0CE2 = 2
, GPIO_PINCFG1_NCESRC1_IOM0CE3 = 3
,
GPIO_PINCFG1_NCESRC1_IOM1CE0 = 4
, GPIO_PINCFG1_NCESRC1_IOM1CE1 = 5
, GPIO_PINCFG1_NCESRC1_IOM1CE2 = 6
, GPIO_PINCFG1_NCESRC1_IOM1CE3 = 7
,
GPIO_PINCFG1_NCESRC1_IOM2CE0 = 8
, GPIO_PINCFG1_NCESRC1_IOM2CE1 = 9
, GPIO_PINCFG1_NCESRC1_IOM2CE2 = 10
, GPIO_PINCFG1_NCESRC1_IOM2CE3 = 11
,
GPIO_PINCFG1_NCESRC1_IOM3CE0 = 12
, GPIO_PINCFG1_NCESRC1_IOM3CE1 = 13
, GPIO_PINCFG1_NCESRC1_IOM3CE2 = 14
, GPIO_PINCFG1_NCESRC1_IOM3CE3 = 15
,
GPIO_PINCFG1_NCESRC1_IOM4CE0 = 16
, GPIO_PINCFG1_NCESRC1_IOM4CE1 = 17
, GPIO_PINCFG1_NCESRC1_IOM4CE2 = 18
, GPIO_PINCFG1_NCESRC1_IOM4CE3 = 19
,
GPIO_PINCFG1_NCESRC1_IOM5CE0 = 20
, GPIO_PINCFG1_NCESRC1_IOM5CE1 = 21
, GPIO_PINCFG1_NCESRC1_IOM5CE2 = 22
, GPIO_PINCFG1_NCESRC1_IOM5CE3 = 23
,
GPIO_PINCFG1_NCESRC1_IOM6CE0 = 24
, GPIO_PINCFG1_NCESRC1_IOM6CE1 = 25
, GPIO_PINCFG1_NCESRC1_IOM6CE2 = 26
, GPIO_PINCFG1_NCESRC1_IOM6CE3 = 27
,
GPIO_PINCFG1_NCESRC1_IOM7CE0 = 28
, GPIO_PINCFG1_NCESRC1_IOM7CE1 = 29
, GPIO_PINCFG1_NCESRC1_IOM7CE2 = 30
, GPIO_PINCFG1_NCESRC1_IOM7CE3 = 31
,
GPIO_PINCFG1_NCESRC1_MSPI0CEN0 = 32
, GPIO_PINCFG1_NCESRC1_MSPI0CEN1 = 33
, GPIO_PINCFG1_NCESRC1_MSPI1CEN0 = 34
, GPIO_PINCFG1_NCESRC1_MSPI1CEN1 = 35
,
GPIO_PINCFG1_NCESRC1_MSPI2CEN0 = 36
, GPIO_PINCFG1_NCESRC1_MSPI2CEN1 = 37
, GPIO_PINCFG1_NCESRC1_DC_DPI_DE = 38
, GPIO_PINCFG1_NCESRC1_DISP_CONT_CSX = 39
,
GPIO_PINCFG1_NCESRC1_DC_SPI_CS_N = 40
, GPIO_PINCFG1_NCESRC1_DC_QSPI_CS_N = 41
, GPIO_PINCFG1_NCESRC1_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG1_PULLCFG1_Enum {
GPIO_PINCFG1_PULLCFG1_DIS = 0
, GPIO_PINCFG1_PULLCFG1_PD50K = 1
, GPIO_PINCFG1_PULLCFG1_PU15K = 2
, GPIO_PINCFG1_PULLCFG1_PU6K = 3
,
GPIO_PINCFG1_PULLCFG1_PU12K = 4
, GPIO_PINCFG1_PULLCFG1_PU24K = 5
, GPIO_PINCFG1_PULLCFG1_PU50K = 6
, GPIO_PINCFG1_PULLCFG1_PU100K = 7
} |
| |
| enum | GPIO_PINCFG1_DS1_Enum { GPIO_PINCFG1_DS1_0P1X = 0
, GPIO_PINCFG1_DS1_0P5X = 1
} |
| |
| enum | GPIO_PINCFG1_OUTCFG1_Enum { GPIO_PINCFG1_OUTCFG1_DIS = 0
, GPIO_PINCFG1_OUTCFG1_PUSHPULL = 1
, GPIO_PINCFG1_OUTCFG1_OD = 2
, GPIO_PINCFG1_OUTCFG1_TS = 3
} |
| |
| enum | GPIO_PINCFG1_IRPTEN1_Enum { GPIO_PINCFG1_IRPTEN1_DIS = 0
, GPIO_PINCFG1_IRPTEN1_INTFALL = 1
, GPIO_PINCFG1_IRPTEN1_INTRISE = 2
, GPIO_PINCFG1_IRPTEN1_INTANY = 3
} |
| |
| enum | GPIO_PINCFG1_FNCSEL1_Enum {
GPIO_PINCFG1_FNCSEL1_SWTRACE0 = 0
, GPIO_PINCFG1_FNCSEL1_SLSDAWIR3 = 1
, GPIO_PINCFG1_FNCSEL1_SLMOSI = 2
, GPIO_PINCFG1_FNCSEL1_GPIO = 3
,
GPIO_PINCFG1_FNCSEL1_UART2TX = 4
, GPIO_PINCFG1_FNCSEL1_UART3TX = 5
, GPIO_PINCFG1_FNCSEL1_CT1 = 6
, GPIO_PINCFG1_FNCSEL1_NCE1 = 7
,
GPIO_PINCFG1_FNCSEL1_OBSBUS1 = 8
, GPIO_PINCFG1_FNCSEL1_VCMPO = 9
, GPIO_PINCFG1_FNCSEL1_RESERVED10 = 10
, GPIO_PINCFG1_FNCSEL1_FPIO = 11
,
GPIO_PINCFG1_FNCSEL1_RESERVED12 = 12
, GPIO_PINCFG1_FNCSEL1_RESERVED13 = 13
, GPIO_PINCFG1_FNCSEL1_RESERVED14 = 14
, GPIO_PINCFG1_FNCSEL1_SCANIN4 = 15
} |
| |
| enum | GPIO_PINCFG2_NCEPOL2_Enum { GPIO_PINCFG2_NCEPOL2_LOW = 0
, GPIO_PINCFG2_NCEPOL2_HIGH = 1
} |
| |
| enum | GPIO_PINCFG2_NCESRC2_Enum {
GPIO_PINCFG2_NCESRC2_IOM0CE0 = 0
, GPIO_PINCFG2_NCESRC2_IOM0CE1 = 1
, GPIO_PINCFG2_NCESRC2_IOM0CE2 = 2
, GPIO_PINCFG2_NCESRC2_IOM0CE3 = 3
,
GPIO_PINCFG2_NCESRC2_IOM1CE0 = 4
, GPIO_PINCFG2_NCESRC2_IOM1CE1 = 5
, GPIO_PINCFG2_NCESRC2_IOM1CE2 = 6
, GPIO_PINCFG2_NCESRC2_IOM1CE3 = 7
,
GPIO_PINCFG2_NCESRC2_IOM2CE0 = 8
, GPIO_PINCFG2_NCESRC2_IOM2CE1 = 9
, GPIO_PINCFG2_NCESRC2_IOM2CE2 = 10
, GPIO_PINCFG2_NCESRC2_IOM2CE3 = 11
,
GPIO_PINCFG2_NCESRC2_IOM3CE0 = 12
, GPIO_PINCFG2_NCESRC2_IOM3CE1 = 13
, GPIO_PINCFG2_NCESRC2_IOM3CE2 = 14
, GPIO_PINCFG2_NCESRC2_IOM3CE3 = 15
,
GPIO_PINCFG2_NCESRC2_IOM4CE0 = 16
, GPIO_PINCFG2_NCESRC2_IOM4CE1 = 17
, GPIO_PINCFG2_NCESRC2_IOM4CE2 = 18
, GPIO_PINCFG2_NCESRC2_IOM4CE3 = 19
,
GPIO_PINCFG2_NCESRC2_IOM5CE0 = 20
, GPIO_PINCFG2_NCESRC2_IOM5CE1 = 21
, GPIO_PINCFG2_NCESRC2_IOM5CE2 = 22
, GPIO_PINCFG2_NCESRC2_IOM5CE3 = 23
,
GPIO_PINCFG2_NCESRC2_IOM6CE0 = 24
, GPIO_PINCFG2_NCESRC2_IOM6CE1 = 25
, GPIO_PINCFG2_NCESRC2_IOM6CE2 = 26
, GPIO_PINCFG2_NCESRC2_IOM6CE3 = 27
,
GPIO_PINCFG2_NCESRC2_IOM7CE0 = 28
, GPIO_PINCFG2_NCESRC2_IOM7CE1 = 29
, GPIO_PINCFG2_NCESRC2_IOM7CE2 = 30
, GPIO_PINCFG2_NCESRC2_IOM7CE3 = 31
,
GPIO_PINCFG2_NCESRC2_MSPI0CEN0 = 32
, GPIO_PINCFG2_NCESRC2_MSPI0CEN1 = 33
, GPIO_PINCFG2_NCESRC2_MSPI1CEN0 = 34
, GPIO_PINCFG2_NCESRC2_MSPI1CEN1 = 35
,
GPIO_PINCFG2_NCESRC2_MSPI2CEN0 = 36
, GPIO_PINCFG2_NCESRC2_MSPI2CEN1 = 37
, GPIO_PINCFG2_NCESRC2_DC_DPI_DE = 38
, GPIO_PINCFG2_NCESRC2_DISP_CONT_CSX = 39
,
GPIO_PINCFG2_NCESRC2_DC_SPI_CS_N = 40
, GPIO_PINCFG2_NCESRC2_DC_QSPI_CS_N = 41
, GPIO_PINCFG2_NCESRC2_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG2_PULLCFG2_Enum {
GPIO_PINCFG2_PULLCFG2_DIS = 0
, GPIO_PINCFG2_PULLCFG2_PD50K = 1
, GPIO_PINCFG2_PULLCFG2_PU15K = 2
, GPIO_PINCFG2_PULLCFG2_PU6K = 3
,
GPIO_PINCFG2_PULLCFG2_PU12K = 4
, GPIO_PINCFG2_PULLCFG2_PU24K = 5
, GPIO_PINCFG2_PULLCFG2_PU50K = 6
, GPIO_PINCFG2_PULLCFG2_PU100K = 7
} |
| |
| enum | GPIO_PINCFG2_DS2_Enum { GPIO_PINCFG2_DS2_0P1X = 0
, GPIO_PINCFG2_DS2_0P5X = 1
} |
| |
| enum | GPIO_PINCFG2_OUTCFG2_Enum { GPIO_PINCFG2_OUTCFG2_DIS = 0
, GPIO_PINCFG2_OUTCFG2_PUSHPULL = 1
, GPIO_PINCFG2_OUTCFG2_OD = 2
, GPIO_PINCFG2_OUTCFG2_TS = 3
} |
| |
| enum | GPIO_PINCFG2_IRPTEN2_Enum { GPIO_PINCFG2_IRPTEN2_DIS = 0
, GPIO_PINCFG2_IRPTEN2_INTFALL = 1
, GPIO_PINCFG2_IRPTEN2_INTRISE = 2
, GPIO_PINCFG2_IRPTEN2_INTANY = 3
} |
| |
| enum | GPIO_PINCFG2_FNCSEL2_Enum {
GPIO_PINCFG2_FNCSEL2_SWTRACE1 = 0
, GPIO_PINCFG2_FNCSEL2_SLMISO = 1
, GPIO_PINCFG2_FNCSEL2_TRIG1 = 2
, GPIO_PINCFG2_FNCSEL2_GPIO = 3
,
GPIO_PINCFG2_FNCSEL2_UART0RX = 4
, GPIO_PINCFG2_FNCSEL2_UART1RX = 5
, GPIO_PINCFG2_FNCSEL2_CT2 = 6
, GPIO_PINCFG2_FNCSEL2_NCE2 = 7
,
GPIO_PINCFG2_FNCSEL2_OBSBUS2 = 8
, GPIO_PINCFG2_FNCSEL2_VCMPO = 9
, GPIO_PINCFG2_FNCSEL2_RESERVED10 = 10
, GPIO_PINCFG2_FNCSEL2_FPIO = 11
,
GPIO_PINCFG2_FNCSEL2_RESERVED12 = 12
, GPIO_PINCFG2_FNCSEL2_RESERVED13 = 13
, GPIO_PINCFG2_FNCSEL2_RESERVED14 = 14
, GPIO_PINCFG2_FNCSEL2_SCANRSTN = 15
} |
| |
| enum | GPIO_PINCFG3_NCEPOL3_Enum { GPIO_PINCFG3_NCEPOL3_LOW = 0
, GPIO_PINCFG3_NCEPOL3_HIGH = 1
} |
| |
| enum | GPIO_PINCFG3_NCESRC3_Enum {
GPIO_PINCFG3_NCESRC3_IOM0CE0 = 0
, GPIO_PINCFG3_NCESRC3_IOM0CE1 = 1
, GPIO_PINCFG3_NCESRC3_IOM0CE2 = 2
, GPIO_PINCFG3_NCESRC3_IOM0CE3 = 3
,
GPIO_PINCFG3_NCESRC3_IOM1CE0 = 4
, GPIO_PINCFG3_NCESRC3_IOM1CE1 = 5
, GPIO_PINCFG3_NCESRC3_IOM1CE2 = 6
, GPIO_PINCFG3_NCESRC3_IOM1CE3 = 7
,
GPIO_PINCFG3_NCESRC3_IOM2CE0 = 8
, GPIO_PINCFG3_NCESRC3_IOM2CE1 = 9
, GPIO_PINCFG3_NCESRC3_IOM2CE2 = 10
, GPIO_PINCFG3_NCESRC3_IOM2CE3 = 11
,
GPIO_PINCFG3_NCESRC3_IOM3CE0 = 12
, GPIO_PINCFG3_NCESRC3_IOM3CE1 = 13
, GPIO_PINCFG3_NCESRC3_IOM3CE2 = 14
, GPIO_PINCFG3_NCESRC3_IOM3CE3 = 15
,
GPIO_PINCFG3_NCESRC3_IOM4CE0 = 16
, GPIO_PINCFG3_NCESRC3_IOM4CE1 = 17
, GPIO_PINCFG3_NCESRC3_IOM4CE2 = 18
, GPIO_PINCFG3_NCESRC3_IOM4CE3 = 19
,
GPIO_PINCFG3_NCESRC3_IOM5CE0 = 20
, GPIO_PINCFG3_NCESRC3_IOM5CE1 = 21
, GPIO_PINCFG3_NCESRC3_IOM5CE2 = 22
, GPIO_PINCFG3_NCESRC3_IOM5CE3 = 23
,
GPIO_PINCFG3_NCESRC3_IOM6CE0 = 24
, GPIO_PINCFG3_NCESRC3_IOM6CE1 = 25
, GPIO_PINCFG3_NCESRC3_IOM6CE2 = 26
, GPIO_PINCFG3_NCESRC3_IOM6CE3 = 27
,
GPIO_PINCFG3_NCESRC3_IOM7CE0 = 28
, GPIO_PINCFG3_NCESRC3_IOM7CE1 = 29
, GPIO_PINCFG3_NCESRC3_IOM7CE2 = 30
, GPIO_PINCFG3_NCESRC3_IOM7CE3 = 31
,
GPIO_PINCFG3_NCESRC3_MSPI0CEN0 = 32
, GPIO_PINCFG3_NCESRC3_MSPI0CEN1 = 33
, GPIO_PINCFG3_NCESRC3_MSPI1CEN0 = 34
, GPIO_PINCFG3_NCESRC3_MSPI1CEN1 = 35
,
GPIO_PINCFG3_NCESRC3_MSPI2CEN0 = 36
, GPIO_PINCFG3_NCESRC3_MSPI2CEN1 = 37
, GPIO_PINCFG3_NCESRC3_DC_DPI_DE = 38
, GPIO_PINCFG3_NCESRC3_DISP_CONT_CSX = 39
,
GPIO_PINCFG3_NCESRC3_DC_SPI_CS_N = 40
, GPIO_PINCFG3_NCESRC3_DC_QSPI_CS_N = 41
, GPIO_PINCFG3_NCESRC3_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG3_PULLCFG3_Enum {
GPIO_PINCFG3_PULLCFG3_DIS = 0
, GPIO_PINCFG3_PULLCFG3_PD50K = 1
, GPIO_PINCFG3_PULLCFG3_PU15K = 2
, GPIO_PINCFG3_PULLCFG3_PU6K = 3
,
GPIO_PINCFG3_PULLCFG3_PU12K = 4
, GPIO_PINCFG3_PULLCFG3_PU24K = 5
, GPIO_PINCFG3_PULLCFG3_PU50K = 6
, GPIO_PINCFG3_PULLCFG3_PU100K = 7
} |
| |
| enum | GPIO_PINCFG3_DS3_Enum { GPIO_PINCFG3_DS3_0P1X = 0
, GPIO_PINCFG3_DS3_0P5X = 1
} |
| |
| enum | GPIO_PINCFG3_OUTCFG3_Enum { GPIO_PINCFG3_OUTCFG3_DIS = 0
, GPIO_PINCFG3_OUTCFG3_PUSHPULL = 1
, GPIO_PINCFG3_OUTCFG3_OD = 2
, GPIO_PINCFG3_OUTCFG3_TS = 3
} |
| |
| enum | GPIO_PINCFG3_IRPTEN3_Enum { GPIO_PINCFG3_IRPTEN3_DIS = 0
, GPIO_PINCFG3_IRPTEN3_INTFALL = 1
, GPIO_PINCFG3_IRPTEN3_INTRISE = 2
, GPIO_PINCFG3_IRPTEN3_INTANY = 3
} |
| |
| enum | GPIO_PINCFG3_FNCSEL3_Enum {
GPIO_PINCFG3_FNCSEL3_SWTRACE2 = 0
, GPIO_PINCFG3_FNCSEL3_SLnCE = 1
, GPIO_PINCFG3_FNCSEL3_SWO = 2
, GPIO_PINCFG3_FNCSEL3_GPIO = 3
,
GPIO_PINCFG3_FNCSEL3_UART2RX = 4
, GPIO_PINCFG3_FNCSEL3_UART3RX = 5
, GPIO_PINCFG3_FNCSEL3_CT3 = 6
, GPIO_PINCFG3_FNCSEL3_NCE3 = 7
,
GPIO_PINCFG3_FNCSEL3_OBSBUS3 = 8
, GPIO_PINCFG3_FNCSEL3_RESERVED9 = 9
, GPIO_PINCFG3_FNCSEL3_RESERVED10 = 10
, GPIO_PINCFG3_FNCSEL3_FPIO = 11
,
GPIO_PINCFG3_FNCSEL3_RESERVED12 = 12
, GPIO_PINCFG3_FNCSEL3_RESERVED13 = 13
, GPIO_PINCFG3_FNCSEL3_RESERVED14 = 14
, GPIO_PINCFG3_FNCSEL3_SCANIN5 = 15
} |
| |
| enum | GPIO_PINCFG4_NCEPOL4_Enum { GPIO_PINCFG4_NCEPOL4_LOW = 0
, GPIO_PINCFG4_NCEPOL4_HIGH = 1
} |
| |
| enum | GPIO_PINCFG4_NCESRC4_Enum {
GPIO_PINCFG4_NCESRC4_IOM0CE0 = 0
, GPIO_PINCFG4_NCESRC4_IOM0CE1 = 1
, GPIO_PINCFG4_NCESRC4_IOM0CE2 = 2
, GPIO_PINCFG4_NCESRC4_IOM0CE3 = 3
,
GPIO_PINCFG4_NCESRC4_IOM1CE0 = 4
, GPIO_PINCFG4_NCESRC4_IOM1CE1 = 5
, GPIO_PINCFG4_NCESRC4_IOM1CE2 = 6
, GPIO_PINCFG4_NCESRC4_IOM1CE3 = 7
,
GPIO_PINCFG4_NCESRC4_IOM2CE0 = 8
, GPIO_PINCFG4_NCESRC4_IOM2CE1 = 9
, GPIO_PINCFG4_NCESRC4_IOM2CE2 = 10
, GPIO_PINCFG4_NCESRC4_IOM2CE3 = 11
,
GPIO_PINCFG4_NCESRC4_IOM3CE0 = 12
, GPIO_PINCFG4_NCESRC4_IOM3CE1 = 13
, GPIO_PINCFG4_NCESRC4_IOM3CE2 = 14
, GPIO_PINCFG4_NCESRC4_IOM3CE3 = 15
,
GPIO_PINCFG4_NCESRC4_IOM4CE0 = 16
, GPIO_PINCFG4_NCESRC4_IOM4CE1 = 17
, GPIO_PINCFG4_NCESRC4_IOM4CE2 = 18
, GPIO_PINCFG4_NCESRC4_IOM4CE3 = 19
,
GPIO_PINCFG4_NCESRC4_IOM5CE0 = 20
, GPIO_PINCFG4_NCESRC4_IOM5CE1 = 21
, GPIO_PINCFG4_NCESRC4_IOM5CE2 = 22
, GPIO_PINCFG4_NCESRC4_IOM5CE3 = 23
,
GPIO_PINCFG4_NCESRC4_IOM6CE0 = 24
, GPIO_PINCFG4_NCESRC4_IOM6CE1 = 25
, GPIO_PINCFG4_NCESRC4_IOM6CE2 = 26
, GPIO_PINCFG4_NCESRC4_IOM6CE3 = 27
,
GPIO_PINCFG4_NCESRC4_IOM7CE0 = 28
, GPIO_PINCFG4_NCESRC4_IOM7CE1 = 29
, GPIO_PINCFG4_NCESRC4_IOM7CE2 = 30
, GPIO_PINCFG4_NCESRC4_IOM7CE3 = 31
,
GPIO_PINCFG4_NCESRC4_MSPI0CEN0 = 32
, GPIO_PINCFG4_NCESRC4_MSPI0CEN1 = 33
, GPIO_PINCFG4_NCESRC4_MSPI1CEN0 = 34
, GPIO_PINCFG4_NCESRC4_MSPI1CEN1 = 35
,
GPIO_PINCFG4_NCESRC4_MSPI2CEN0 = 36
, GPIO_PINCFG4_NCESRC4_MSPI2CEN1 = 37
, GPIO_PINCFG4_NCESRC4_DC_DPI_DE = 38
, GPIO_PINCFG4_NCESRC4_DISP_CONT_CSX = 39
,
GPIO_PINCFG4_NCESRC4_DC_SPI_CS_N = 40
, GPIO_PINCFG4_NCESRC4_DC_QSPI_CS_N = 41
, GPIO_PINCFG4_NCESRC4_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG4_PULLCFG4_Enum {
GPIO_PINCFG4_PULLCFG4_DIS = 0
, GPIO_PINCFG4_PULLCFG4_PD50K = 1
, GPIO_PINCFG4_PULLCFG4_PU15K = 2
, GPIO_PINCFG4_PULLCFG4_PU6K = 3
,
GPIO_PINCFG4_PULLCFG4_PU12K = 4
, GPIO_PINCFG4_PULLCFG4_PU24K = 5
, GPIO_PINCFG4_PULLCFG4_PU50K = 6
, GPIO_PINCFG4_PULLCFG4_PU100K = 7
} |
| |
| enum | GPIO_PINCFG4_DS4_Enum { GPIO_PINCFG4_DS4_0P1X = 0
, GPIO_PINCFG4_DS4_0P5X = 1
} |
| |
| enum | GPIO_PINCFG4_OUTCFG4_Enum { GPIO_PINCFG4_OUTCFG4_DIS = 0
, GPIO_PINCFG4_OUTCFG4_PUSHPULL = 1
, GPIO_PINCFG4_OUTCFG4_OD = 2
, GPIO_PINCFG4_OUTCFG4_TS = 3
} |
| |
| enum | GPIO_PINCFG4_IRPTEN4_Enum { GPIO_PINCFG4_IRPTEN4_DIS = 0
, GPIO_PINCFG4_IRPTEN4_INTFALL = 1
, GPIO_PINCFG4_IRPTEN4_INTRISE = 2
, GPIO_PINCFG4_IRPTEN4_INTANY = 3
} |
| |
| enum | GPIO_PINCFG4_FNCSEL4_Enum {
GPIO_PINCFG4_FNCSEL4_SWTRACE3 = 0
, GPIO_PINCFG4_FNCSEL4_SLINT = 1
, GPIO_PINCFG4_FNCSEL4_32KHzXT = 2
, GPIO_PINCFG4_FNCSEL4_GPIO = 3
,
GPIO_PINCFG4_FNCSEL4_UART0RTS = 4
, GPIO_PINCFG4_FNCSEL4_UART1RTS = 5
, GPIO_PINCFG4_FNCSEL4_CT4 = 6
, GPIO_PINCFG4_FNCSEL4_NCE4 = 7
,
GPIO_PINCFG4_FNCSEL4_OBSBUS4 = 8
, GPIO_PINCFG4_FNCSEL4_I2S0_SDIN = 9
, GPIO_PINCFG4_FNCSEL4_I2S1_SDIN = 10
, GPIO_PINCFG4_FNCSEL4_FPIO = 11
,
GPIO_PINCFG4_FNCSEL4_FLB_TDO = 12
, GPIO_PINCFG4_FNCSEL4_FLLOAD_DIR = 13
, GPIO_PINCFG4_FNCSEL4_MDA_TDO = 14
, GPIO_PINCFG4_FNCSEL4_OPCG_TRIG = 15
} |
| |
| enum | GPIO_PINCFG5_NCEPOL5_Enum { GPIO_PINCFG5_NCEPOL5_LOW = 0
, GPIO_PINCFG5_NCEPOL5_HIGH = 1
} |
| |
| enum | GPIO_PINCFG5_NCESRC5_Enum {
GPIO_PINCFG5_NCESRC5_IOM0CE0 = 0
, GPIO_PINCFG5_NCESRC5_IOM0CE1 = 1
, GPIO_PINCFG5_NCESRC5_IOM0CE2 = 2
, GPIO_PINCFG5_NCESRC5_IOM0CE3 = 3
,
GPIO_PINCFG5_NCESRC5_IOM1CE0 = 4
, GPIO_PINCFG5_NCESRC5_IOM1CE1 = 5
, GPIO_PINCFG5_NCESRC5_IOM1CE2 = 6
, GPIO_PINCFG5_NCESRC5_IOM1CE3 = 7
,
GPIO_PINCFG5_NCESRC5_IOM2CE0 = 8
, GPIO_PINCFG5_NCESRC5_IOM2CE1 = 9
, GPIO_PINCFG5_NCESRC5_IOM2CE2 = 10
, GPIO_PINCFG5_NCESRC5_IOM2CE3 = 11
,
GPIO_PINCFG5_NCESRC5_IOM3CE0 = 12
, GPIO_PINCFG5_NCESRC5_IOM3CE1 = 13
, GPIO_PINCFG5_NCESRC5_IOM3CE2 = 14
, GPIO_PINCFG5_NCESRC5_IOM3CE3 = 15
,
GPIO_PINCFG5_NCESRC5_IOM4CE0 = 16
, GPIO_PINCFG5_NCESRC5_IOM4CE1 = 17
, GPIO_PINCFG5_NCESRC5_IOM4CE2 = 18
, GPIO_PINCFG5_NCESRC5_IOM4CE3 = 19
,
GPIO_PINCFG5_NCESRC5_IOM5CE0 = 20
, GPIO_PINCFG5_NCESRC5_IOM5CE1 = 21
, GPIO_PINCFG5_NCESRC5_IOM5CE2 = 22
, GPIO_PINCFG5_NCESRC5_IOM5CE3 = 23
,
GPIO_PINCFG5_NCESRC5_IOM6CE0 = 24
, GPIO_PINCFG5_NCESRC5_IOM6CE1 = 25
, GPIO_PINCFG5_NCESRC5_IOM6CE2 = 26
, GPIO_PINCFG5_NCESRC5_IOM6CE3 = 27
,
GPIO_PINCFG5_NCESRC5_IOM7CE0 = 28
, GPIO_PINCFG5_NCESRC5_IOM7CE1 = 29
, GPIO_PINCFG5_NCESRC5_IOM7CE2 = 30
, GPIO_PINCFG5_NCESRC5_IOM7CE3 = 31
,
GPIO_PINCFG5_NCESRC5_MSPI0CEN0 = 32
, GPIO_PINCFG5_NCESRC5_MSPI0CEN1 = 33
, GPIO_PINCFG5_NCESRC5_MSPI1CEN0 = 34
, GPIO_PINCFG5_NCESRC5_MSPI1CEN1 = 35
,
GPIO_PINCFG5_NCESRC5_MSPI2CEN0 = 36
, GPIO_PINCFG5_NCESRC5_MSPI2CEN1 = 37
, GPIO_PINCFG5_NCESRC5_DC_DPI_DE = 38
, GPIO_PINCFG5_NCESRC5_DISP_CONT_CSX = 39
,
GPIO_PINCFG5_NCESRC5_DC_SPI_CS_N = 40
, GPIO_PINCFG5_NCESRC5_DC_QSPI_CS_N = 41
, GPIO_PINCFG5_NCESRC5_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG5_PULLCFG5_Enum {
GPIO_PINCFG5_PULLCFG5_DIS = 0
, GPIO_PINCFG5_PULLCFG5_PD50K = 1
, GPIO_PINCFG5_PULLCFG5_PU15K = 2
, GPIO_PINCFG5_PULLCFG5_PU6K = 3
,
GPIO_PINCFG5_PULLCFG5_PU12K = 4
, GPIO_PINCFG5_PULLCFG5_PU24K = 5
, GPIO_PINCFG5_PULLCFG5_PU50K = 6
, GPIO_PINCFG5_PULLCFG5_PU100K = 7
} |
| |
| enum | GPIO_PINCFG5_DS5_Enum { GPIO_PINCFG5_DS5_0P1X = 0
, GPIO_PINCFG5_DS5_0P5X = 1
, GPIO_PINCFG5_DS5_0P75X = 2
, GPIO_PINCFG5_DS5_1P0X = 3
} |
| |
| enum | GPIO_PINCFG5_OUTCFG5_Enum { GPIO_PINCFG5_OUTCFG5_DIS = 0
, GPIO_PINCFG5_OUTCFG5_PUSHPULL = 1
, GPIO_PINCFG5_OUTCFG5_OD = 2
, GPIO_PINCFG5_OUTCFG5_TS = 3
} |
| |
| enum | GPIO_PINCFG5_IRPTEN5_Enum { GPIO_PINCFG5_IRPTEN5_DIS = 0
, GPIO_PINCFG5_IRPTEN5_INTFALL = 1
, GPIO_PINCFG5_IRPTEN5_INTRISE = 2
, GPIO_PINCFG5_IRPTEN5_INTANY = 3
} |
| |
| enum | GPIO_PINCFG5_FNCSEL5_Enum {
GPIO_PINCFG5_FNCSEL5_M0SCL = 0
, GPIO_PINCFG5_FNCSEL5_M0SCK = 1
, GPIO_PINCFG5_FNCSEL5_I2S0_CLK = 2
, GPIO_PINCFG5_FNCSEL5_GPIO = 3
,
GPIO_PINCFG5_FNCSEL5_UART2RTS = 4
, GPIO_PINCFG5_FNCSEL5_UART3RTS = 5
, GPIO_PINCFG5_FNCSEL5_CT5 = 6
, GPIO_PINCFG5_FNCSEL5_NCE5 = 7
,
GPIO_PINCFG5_FNCSEL5_OBSBUS5 = 8
, GPIO_PINCFG5_FNCSEL5_RESERVED9 = 9
, GPIO_PINCFG5_FNCSEL5_I2S1_CLK = 10
, GPIO_PINCFG5_FNCSEL5_FPIO = 11
,
GPIO_PINCFG5_FNCSEL5_FLB_TDI = 12
, GPIO_PINCFG5_FNCSEL5_FLLOAD_DATA = 13
, GPIO_PINCFG5_FNCSEL5_MDA_SRST = 14
, GPIO_PINCFG5_FNCSEL5_DFT_ISO = 15
} |
| |
| enum | GPIO_PINCFG6_NCEPOL6_Enum { GPIO_PINCFG6_NCEPOL6_LOW = 0
, GPIO_PINCFG6_NCEPOL6_HIGH = 1
} |
| |
| enum | GPIO_PINCFG6_NCESRC6_Enum {
GPIO_PINCFG6_NCESRC6_IOM0CE0 = 0
, GPIO_PINCFG6_NCESRC6_IOM0CE1 = 1
, GPIO_PINCFG6_NCESRC6_IOM0CE2 = 2
, GPIO_PINCFG6_NCESRC6_IOM0CE3 = 3
,
GPIO_PINCFG6_NCESRC6_IOM1CE0 = 4
, GPIO_PINCFG6_NCESRC6_IOM1CE1 = 5
, GPIO_PINCFG6_NCESRC6_IOM1CE2 = 6
, GPIO_PINCFG6_NCESRC6_IOM1CE3 = 7
,
GPIO_PINCFG6_NCESRC6_IOM2CE0 = 8
, GPIO_PINCFG6_NCESRC6_IOM2CE1 = 9
, GPIO_PINCFG6_NCESRC6_IOM2CE2 = 10
, GPIO_PINCFG6_NCESRC6_IOM2CE3 = 11
,
GPIO_PINCFG6_NCESRC6_IOM3CE0 = 12
, GPIO_PINCFG6_NCESRC6_IOM3CE1 = 13
, GPIO_PINCFG6_NCESRC6_IOM3CE2 = 14
, GPIO_PINCFG6_NCESRC6_IOM3CE3 = 15
,
GPIO_PINCFG6_NCESRC6_IOM4CE0 = 16
, GPIO_PINCFG6_NCESRC6_IOM4CE1 = 17
, GPIO_PINCFG6_NCESRC6_IOM4CE2 = 18
, GPIO_PINCFG6_NCESRC6_IOM4CE3 = 19
,
GPIO_PINCFG6_NCESRC6_IOM5CE0 = 20
, GPIO_PINCFG6_NCESRC6_IOM5CE1 = 21
, GPIO_PINCFG6_NCESRC6_IOM5CE2 = 22
, GPIO_PINCFG6_NCESRC6_IOM5CE3 = 23
,
GPIO_PINCFG6_NCESRC6_IOM6CE0 = 24
, GPIO_PINCFG6_NCESRC6_IOM6CE1 = 25
, GPIO_PINCFG6_NCESRC6_IOM6CE2 = 26
, GPIO_PINCFG6_NCESRC6_IOM6CE3 = 27
,
GPIO_PINCFG6_NCESRC6_IOM7CE0 = 28
, GPIO_PINCFG6_NCESRC6_IOM7CE1 = 29
, GPIO_PINCFG6_NCESRC6_IOM7CE2 = 30
, GPIO_PINCFG6_NCESRC6_IOM7CE3 = 31
,
GPIO_PINCFG6_NCESRC6_MSPI0CEN0 = 32
, GPIO_PINCFG6_NCESRC6_MSPI0CEN1 = 33
, GPIO_PINCFG6_NCESRC6_MSPI1CEN0 = 34
, GPIO_PINCFG6_NCESRC6_MSPI1CEN1 = 35
,
GPIO_PINCFG6_NCESRC6_MSPI2CEN0 = 36
, GPIO_PINCFG6_NCESRC6_MSPI2CEN1 = 37
, GPIO_PINCFG6_NCESRC6_DC_DPI_DE = 38
, GPIO_PINCFG6_NCESRC6_DISP_CONT_CSX = 39
,
GPIO_PINCFG6_NCESRC6_DC_SPI_CS_N = 40
, GPIO_PINCFG6_NCESRC6_DC_QSPI_CS_N = 41
, GPIO_PINCFG6_NCESRC6_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG6_PULLCFG6_Enum {
GPIO_PINCFG6_PULLCFG6_DIS = 0
, GPIO_PINCFG6_PULLCFG6_PD50K = 1
, GPIO_PINCFG6_PULLCFG6_PU15K = 2
, GPIO_PINCFG6_PULLCFG6_PU6K = 3
,
GPIO_PINCFG6_PULLCFG6_PU12K = 4
, GPIO_PINCFG6_PULLCFG6_PU24K = 5
, GPIO_PINCFG6_PULLCFG6_PU50K = 6
, GPIO_PINCFG6_PULLCFG6_PU100K = 7
} |
| |
| enum | GPIO_PINCFG6_DS6_Enum { GPIO_PINCFG6_DS6_0P1X = 0
, GPIO_PINCFG6_DS6_0P5X = 1
, GPIO_PINCFG6_DS6_0P75X = 2
, GPIO_PINCFG6_DS6_1P0X = 3
} |
| |
| enum | GPIO_PINCFG6_OUTCFG6_Enum { GPIO_PINCFG6_OUTCFG6_DIS = 0
, GPIO_PINCFG6_OUTCFG6_PUSHPULL = 1
, GPIO_PINCFG6_OUTCFG6_OD = 2
, GPIO_PINCFG6_OUTCFG6_TS = 3
} |
| |
| enum | GPIO_PINCFG6_IRPTEN6_Enum { GPIO_PINCFG6_IRPTEN6_DIS = 0
, GPIO_PINCFG6_IRPTEN6_INTFALL = 1
, GPIO_PINCFG6_IRPTEN6_INTRISE = 2
, GPIO_PINCFG6_IRPTEN6_INTANY = 3
} |
| |
| enum | GPIO_PINCFG6_FNCSEL6_Enum {
GPIO_PINCFG6_FNCSEL6_M0SDAWIR3 = 0
, GPIO_PINCFG6_FNCSEL6_M0MOSI = 1
, GPIO_PINCFG6_FNCSEL6_I2S0_DATA = 2
, GPIO_PINCFG6_FNCSEL6_GPIO = 3
,
GPIO_PINCFG6_FNCSEL6_UART0CTS = 4
, GPIO_PINCFG6_FNCSEL6_UART1CTS = 5
, GPIO_PINCFG6_FNCSEL6_CT6 = 6
, GPIO_PINCFG6_FNCSEL6_NCE6 = 7
,
GPIO_PINCFG6_FNCSEL6_OBSBUS6 = 8
, GPIO_PINCFG6_FNCSEL6_I2S0_SDOUT = 9
, GPIO_PINCFG6_FNCSEL6_I2S1_SDOUT = 10
, GPIO_PINCFG6_FNCSEL6_FPIO = 11
,
GPIO_PINCFG6_FNCSEL6_RESERVED12 = 12
, GPIO_PINCFG6_FNCSEL6_RESERVED13 = 13
, GPIO_PINCFG6_FNCSEL6_RESERVED14 = 14
, GPIO_PINCFG6_FNCSEL6_SCANIN6 = 15
} |
| |
| enum | GPIO_PINCFG7_NCEPOL7_Enum { GPIO_PINCFG7_NCEPOL7_LOW = 0
, GPIO_PINCFG7_NCEPOL7_HIGH = 1
} |
| |
| enum | GPIO_PINCFG7_NCESRC7_Enum {
GPIO_PINCFG7_NCESRC7_IOM0CE0 = 0
, GPIO_PINCFG7_NCESRC7_IOM0CE1 = 1
, GPIO_PINCFG7_NCESRC7_IOM0CE2 = 2
, GPIO_PINCFG7_NCESRC7_IOM0CE3 = 3
,
GPIO_PINCFG7_NCESRC7_IOM1CE0 = 4
, GPIO_PINCFG7_NCESRC7_IOM1CE1 = 5
, GPIO_PINCFG7_NCESRC7_IOM1CE2 = 6
, GPIO_PINCFG7_NCESRC7_IOM1CE3 = 7
,
GPIO_PINCFG7_NCESRC7_IOM2CE0 = 8
, GPIO_PINCFG7_NCESRC7_IOM2CE1 = 9
, GPIO_PINCFG7_NCESRC7_IOM2CE2 = 10
, GPIO_PINCFG7_NCESRC7_IOM2CE3 = 11
,
GPIO_PINCFG7_NCESRC7_IOM3CE0 = 12
, GPIO_PINCFG7_NCESRC7_IOM3CE1 = 13
, GPIO_PINCFG7_NCESRC7_IOM3CE2 = 14
, GPIO_PINCFG7_NCESRC7_IOM3CE3 = 15
,
GPIO_PINCFG7_NCESRC7_IOM4CE0 = 16
, GPIO_PINCFG7_NCESRC7_IOM4CE1 = 17
, GPIO_PINCFG7_NCESRC7_IOM4CE2 = 18
, GPIO_PINCFG7_NCESRC7_IOM4CE3 = 19
,
GPIO_PINCFG7_NCESRC7_IOM5CE0 = 20
, GPIO_PINCFG7_NCESRC7_IOM5CE1 = 21
, GPIO_PINCFG7_NCESRC7_IOM5CE2 = 22
, GPIO_PINCFG7_NCESRC7_IOM5CE3 = 23
,
GPIO_PINCFG7_NCESRC7_IOM6CE0 = 24
, GPIO_PINCFG7_NCESRC7_IOM6CE1 = 25
, GPIO_PINCFG7_NCESRC7_IOM6CE2 = 26
, GPIO_PINCFG7_NCESRC7_IOM6CE3 = 27
,
GPIO_PINCFG7_NCESRC7_IOM7CE0 = 28
, GPIO_PINCFG7_NCESRC7_IOM7CE1 = 29
, GPIO_PINCFG7_NCESRC7_IOM7CE2 = 30
, GPIO_PINCFG7_NCESRC7_IOM7CE3 = 31
,
GPIO_PINCFG7_NCESRC7_MSPI0CEN0 = 32
, GPIO_PINCFG7_NCESRC7_MSPI0CEN1 = 33
, GPIO_PINCFG7_NCESRC7_MSPI1CEN0 = 34
, GPIO_PINCFG7_NCESRC7_MSPI1CEN1 = 35
,
GPIO_PINCFG7_NCESRC7_MSPI2CEN0 = 36
, GPIO_PINCFG7_NCESRC7_MSPI2CEN1 = 37
, GPIO_PINCFG7_NCESRC7_DC_DPI_DE = 38
, GPIO_PINCFG7_NCESRC7_DISP_CONT_CSX = 39
,
GPIO_PINCFG7_NCESRC7_DC_SPI_CS_N = 40
, GPIO_PINCFG7_NCESRC7_DC_QSPI_CS_N = 41
, GPIO_PINCFG7_NCESRC7_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG7_PULLCFG7_Enum {
GPIO_PINCFG7_PULLCFG7_DIS = 0
, GPIO_PINCFG7_PULLCFG7_PD50K = 1
, GPIO_PINCFG7_PULLCFG7_PU15K = 2
, GPIO_PINCFG7_PULLCFG7_PU6K = 3
,
GPIO_PINCFG7_PULLCFG7_PU12K = 4
, GPIO_PINCFG7_PULLCFG7_PU24K = 5
, GPIO_PINCFG7_PULLCFG7_PU50K = 6
, GPIO_PINCFG7_PULLCFG7_PU100K = 7
} |
| |
| enum | GPIO_PINCFG7_DS7_Enum { GPIO_PINCFG7_DS7_0P1X = 0
, GPIO_PINCFG7_DS7_0P5X = 1
, GPIO_PINCFG7_DS7_0P75X = 2
, GPIO_PINCFG7_DS7_1P0X = 3
} |
| |
| enum | GPIO_PINCFG7_OUTCFG7_Enum { GPIO_PINCFG7_OUTCFG7_DIS = 0
, GPIO_PINCFG7_OUTCFG7_PUSHPULL = 1
, GPIO_PINCFG7_OUTCFG7_OD = 2
, GPIO_PINCFG7_OUTCFG7_TS = 3
} |
| |
| enum | GPIO_PINCFG7_IRPTEN7_Enum { GPIO_PINCFG7_IRPTEN7_DIS = 0
, GPIO_PINCFG7_IRPTEN7_INTFALL = 1
, GPIO_PINCFG7_IRPTEN7_INTRISE = 2
, GPIO_PINCFG7_IRPTEN7_INTANY = 3
} |
| |
| enum | GPIO_PINCFG7_FNCSEL7_Enum {
GPIO_PINCFG7_FNCSEL7_M0MISO = 0
, GPIO_PINCFG7_FNCSEL7_TRIG0 = 1
, GPIO_PINCFG7_FNCSEL7_I2S0_WS = 2
, GPIO_PINCFG7_FNCSEL7_GPIO = 3
,
GPIO_PINCFG7_FNCSEL7_UART2CTS = 4
, GPIO_PINCFG7_FNCSEL7_UART3CTS = 5
, GPIO_PINCFG7_FNCSEL7_CT7 = 6
, GPIO_PINCFG7_FNCSEL7_NCE7 = 7
,
GPIO_PINCFG7_FNCSEL7_OBSBUS7 = 8
, GPIO_PINCFG7_FNCSEL7_RESERVED9 = 9
, GPIO_PINCFG7_FNCSEL7_I2S1_WS = 10
, GPIO_PINCFG7_FNCSEL7_FPIO = 11
,
GPIO_PINCFG7_FNCSEL7_RESERVED12 = 12
, GPIO_PINCFG7_FNCSEL7_RESERVED13 = 13
, GPIO_PINCFG7_FNCSEL7_RESERVED14 = 14
, GPIO_PINCFG7_FNCSEL7_SCANIN7 = 15
} |
| |
| enum | GPIO_PINCFG8_NCEPOL8_Enum { GPIO_PINCFG8_NCEPOL8_LOW = 0
, GPIO_PINCFG8_NCEPOL8_HIGH = 1
} |
| |
| enum | GPIO_PINCFG8_NCESRC8_Enum {
GPIO_PINCFG8_NCESRC8_IOM0CE0 = 0
, GPIO_PINCFG8_NCESRC8_IOM0CE1 = 1
, GPIO_PINCFG8_NCESRC8_IOM0CE2 = 2
, GPIO_PINCFG8_NCESRC8_IOM0CE3 = 3
,
GPIO_PINCFG8_NCESRC8_IOM1CE0 = 4
, GPIO_PINCFG8_NCESRC8_IOM1CE1 = 5
, GPIO_PINCFG8_NCESRC8_IOM1CE2 = 6
, GPIO_PINCFG8_NCESRC8_IOM1CE3 = 7
,
GPIO_PINCFG8_NCESRC8_IOM2CE0 = 8
, GPIO_PINCFG8_NCESRC8_IOM2CE1 = 9
, GPIO_PINCFG8_NCESRC8_IOM2CE2 = 10
, GPIO_PINCFG8_NCESRC8_IOM2CE3 = 11
,
GPIO_PINCFG8_NCESRC8_IOM3CE0 = 12
, GPIO_PINCFG8_NCESRC8_IOM3CE1 = 13
, GPIO_PINCFG8_NCESRC8_IOM3CE2 = 14
, GPIO_PINCFG8_NCESRC8_IOM3CE3 = 15
,
GPIO_PINCFG8_NCESRC8_IOM4CE0 = 16
, GPIO_PINCFG8_NCESRC8_IOM4CE1 = 17
, GPIO_PINCFG8_NCESRC8_IOM4CE2 = 18
, GPIO_PINCFG8_NCESRC8_IOM4CE3 = 19
,
GPIO_PINCFG8_NCESRC8_IOM5CE0 = 20
, GPIO_PINCFG8_NCESRC8_IOM5CE1 = 21
, GPIO_PINCFG8_NCESRC8_IOM5CE2 = 22
, GPIO_PINCFG8_NCESRC8_IOM5CE3 = 23
,
GPIO_PINCFG8_NCESRC8_IOM6CE0 = 24
, GPIO_PINCFG8_NCESRC8_IOM6CE1 = 25
, GPIO_PINCFG8_NCESRC8_IOM6CE2 = 26
, GPIO_PINCFG8_NCESRC8_IOM6CE3 = 27
,
GPIO_PINCFG8_NCESRC8_IOM7CE0 = 28
, GPIO_PINCFG8_NCESRC8_IOM7CE1 = 29
, GPIO_PINCFG8_NCESRC8_IOM7CE2 = 30
, GPIO_PINCFG8_NCESRC8_IOM7CE3 = 31
,
GPIO_PINCFG8_NCESRC8_MSPI0CEN0 = 32
, GPIO_PINCFG8_NCESRC8_MSPI0CEN1 = 33
, GPIO_PINCFG8_NCESRC8_MSPI1CEN0 = 34
, GPIO_PINCFG8_NCESRC8_MSPI1CEN1 = 35
,
GPIO_PINCFG8_NCESRC8_MSPI2CEN0 = 36
, GPIO_PINCFG8_NCESRC8_MSPI2CEN1 = 37
, GPIO_PINCFG8_NCESRC8_DC_DPI_DE = 38
, GPIO_PINCFG8_NCESRC8_DISP_CONT_CSX = 39
,
GPIO_PINCFG8_NCESRC8_DC_SPI_CS_N = 40
, GPIO_PINCFG8_NCESRC8_DC_QSPI_CS_N = 41
, GPIO_PINCFG8_NCESRC8_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG8_PULLCFG8_Enum {
GPIO_PINCFG8_PULLCFG8_DIS = 0
, GPIO_PINCFG8_PULLCFG8_PD50K = 1
, GPIO_PINCFG8_PULLCFG8_PU15K = 2
, GPIO_PINCFG8_PULLCFG8_PU6K = 3
,
GPIO_PINCFG8_PULLCFG8_PU12K = 4
, GPIO_PINCFG8_PULLCFG8_PU24K = 5
, GPIO_PINCFG8_PULLCFG8_PU50K = 6
, GPIO_PINCFG8_PULLCFG8_PU100K = 7
} |
| |
| enum | GPIO_PINCFG8_DS8_Enum { GPIO_PINCFG8_DS8_0P1X = 0
, GPIO_PINCFG8_DS8_0P5X = 1
, GPIO_PINCFG8_DS8_0P75X = 2
, GPIO_PINCFG8_DS8_1P0X = 3
} |
| |
| enum | GPIO_PINCFG8_OUTCFG8_Enum { GPIO_PINCFG8_OUTCFG8_DIS = 0
, GPIO_PINCFG8_OUTCFG8_PUSHPULL = 1
, GPIO_PINCFG8_OUTCFG8_OD = 2
, GPIO_PINCFG8_OUTCFG8_TS = 3
} |
| |
| enum | GPIO_PINCFG8_IRPTEN8_Enum { GPIO_PINCFG8_IRPTEN8_DIS = 0
, GPIO_PINCFG8_IRPTEN8_INTFALL = 1
, GPIO_PINCFG8_IRPTEN8_INTRISE = 2
, GPIO_PINCFG8_IRPTEN8_INTANY = 3
} |
| |
| enum | GPIO_PINCFG8_FNCSEL8_Enum {
GPIO_PINCFG8_FNCSEL8_CMPRF1 = 0
, GPIO_PINCFG8_FNCSEL8_TRIG1 = 1
, GPIO_PINCFG8_FNCSEL8_RESERVED2 = 2
, GPIO_PINCFG8_FNCSEL8_GPIO = 3
,
GPIO_PINCFG8_FNCSEL8_M1SCL = 4
, GPIO_PINCFG8_FNCSEL8_M1SCK = 5
, GPIO_PINCFG8_FNCSEL8_CT8 = 6
, GPIO_PINCFG8_FNCSEL8_NCE8 = 7
,
GPIO_PINCFG8_FNCSEL8_OBSBUS8 = 8
, GPIO_PINCFG8_FNCSEL8_RESERVED9 = 9
, GPIO_PINCFG8_FNCSEL8_RESERVED10 = 10
, GPIO_PINCFG8_FNCSEL8_FPIO = 11
,
GPIO_PINCFG8_FNCSEL8_RESERVED12 = 12
, GPIO_PINCFG8_FNCSEL8_RESERVED13 = 13
, GPIO_PINCFG8_FNCSEL8_RESERVED14 = 14
, GPIO_PINCFG8_FNCSEL8_SCANOUT4 = 15
} |
| |
| enum | GPIO_PINCFG9_NCEPOL9_Enum { GPIO_PINCFG9_NCEPOL9_LOW = 0
, GPIO_PINCFG9_NCEPOL9_HIGH = 1
} |
| |
| enum | GPIO_PINCFG9_NCESRC9_Enum {
GPIO_PINCFG9_NCESRC9_IOM0CE0 = 0
, GPIO_PINCFG9_NCESRC9_IOM0CE1 = 1
, GPIO_PINCFG9_NCESRC9_IOM0CE2 = 2
, GPIO_PINCFG9_NCESRC9_IOM0CE3 = 3
,
GPIO_PINCFG9_NCESRC9_IOM1CE0 = 4
, GPIO_PINCFG9_NCESRC9_IOM1CE1 = 5
, GPIO_PINCFG9_NCESRC9_IOM1CE2 = 6
, GPIO_PINCFG9_NCESRC9_IOM1CE3 = 7
,
GPIO_PINCFG9_NCESRC9_IOM2CE0 = 8
, GPIO_PINCFG9_NCESRC9_IOM2CE1 = 9
, GPIO_PINCFG9_NCESRC9_IOM2CE2 = 10
, GPIO_PINCFG9_NCESRC9_IOM2CE3 = 11
,
GPIO_PINCFG9_NCESRC9_IOM3CE0 = 12
, GPIO_PINCFG9_NCESRC9_IOM3CE1 = 13
, GPIO_PINCFG9_NCESRC9_IOM3CE2 = 14
, GPIO_PINCFG9_NCESRC9_IOM3CE3 = 15
,
GPIO_PINCFG9_NCESRC9_IOM4CE0 = 16
, GPIO_PINCFG9_NCESRC9_IOM4CE1 = 17
, GPIO_PINCFG9_NCESRC9_IOM4CE2 = 18
, GPIO_PINCFG9_NCESRC9_IOM4CE3 = 19
,
GPIO_PINCFG9_NCESRC9_IOM5CE0 = 20
, GPIO_PINCFG9_NCESRC9_IOM5CE1 = 21
, GPIO_PINCFG9_NCESRC9_IOM5CE2 = 22
, GPIO_PINCFG9_NCESRC9_IOM5CE3 = 23
,
GPIO_PINCFG9_NCESRC9_IOM6CE0 = 24
, GPIO_PINCFG9_NCESRC9_IOM6CE1 = 25
, GPIO_PINCFG9_NCESRC9_IOM6CE2 = 26
, GPIO_PINCFG9_NCESRC9_IOM6CE3 = 27
,
GPIO_PINCFG9_NCESRC9_IOM7CE0 = 28
, GPIO_PINCFG9_NCESRC9_IOM7CE1 = 29
, GPIO_PINCFG9_NCESRC9_IOM7CE2 = 30
, GPIO_PINCFG9_NCESRC9_IOM7CE3 = 31
,
GPIO_PINCFG9_NCESRC9_MSPI0CEN0 = 32
, GPIO_PINCFG9_NCESRC9_MSPI0CEN1 = 33
, GPIO_PINCFG9_NCESRC9_MSPI1CEN0 = 34
, GPIO_PINCFG9_NCESRC9_MSPI1CEN1 = 35
,
GPIO_PINCFG9_NCESRC9_MSPI2CEN0 = 36
, GPIO_PINCFG9_NCESRC9_MSPI2CEN1 = 37
, GPIO_PINCFG9_NCESRC9_DC_DPI_DE = 38
, GPIO_PINCFG9_NCESRC9_DISP_CONT_CSX = 39
,
GPIO_PINCFG9_NCESRC9_DC_SPI_CS_N = 40
, GPIO_PINCFG9_NCESRC9_DC_QSPI_CS_N = 41
, GPIO_PINCFG9_NCESRC9_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG9_PULLCFG9_Enum {
GPIO_PINCFG9_PULLCFG9_DIS = 0
, GPIO_PINCFG9_PULLCFG9_PD50K = 1
, GPIO_PINCFG9_PULLCFG9_PU15K = 2
, GPIO_PINCFG9_PULLCFG9_PU6K = 3
,
GPIO_PINCFG9_PULLCFG9_PU12K = 4
, GPIO_PINCFG9_PULLCFG9_PU24K = 5
, GPIO_PINCFG9_PULLCFG9_PU50K = 6
, GPIO_PINCFG9_PULLCFG9_PU100K = 7
} |
| |
| enum | GPIO_PINCFG9_DS9_Enum { GPIO_PINCFG9_DS9_0P1X = 0
, GPIO_PINCFG9_DS9_0P5X = 1
, GPIO_PINCFG9_DS9_0P75X = 2
, GPIO_PINCFG9_DS9_1P0X = 3
} |
| |
| enum | GPIO_PINCFG9_OUTCFG9_Enum { GPIO_PINCFG9_OUTCFG9_DIS = 0
, GPIO_PINCFG9_OUTCFG9_PUSHPULL = 1
, GPIO_PINCFG9_OUTCFG9_OD = 2
, GPIO_PINCFG9_OUTCFG9_TS = 3
} |
| |
| enum | GPIO_PINCFG9_IRPTEN9_Enum { GPIO_PINCFG9_IRPTEN9_DIS = 0
, GPIO_PINCFG9_IRPTEN9_INTFALL = 1
, GPIO_PINCFG9_IRPTEN9_INTRISE = 2
, GPIO_PINCFG9_IRPTEN9_INTANY = 3
} |
| |
| enum | GPIO_PINCFG9_FNCSEL9_Enum {
GPIO_PINCFG9_FNCSEL9_CMPRF0 = 0
, GPIO_PINCFG9_FNCSEL9_TRIG2 = 1
, GPIO_PINCFG9_FNCSEL9_RESERVED2 = 2
, GPIO_PINCFG9_FNCSEL9_GPIO = 3
,
GPIO_PINCFG9_FNCSEL9_M1SDAWIR3 = 4
, GPIO_PINCFG9_FNCSEL9_M1MOSI = 5
, GPIO_PINCFG9_FNCSEL9_CT9 = 6
, GPIO_PINCFG9_FNCSEL9_NCE9 = 7
,
GPIO_PINCFG9_FNCSEL9_OBSBUS9 = 8
, GPIO_PINCFG9_FNCSEL9_RESERVED9 = 9
, GPIO_PINCFG9_FNCSEL9_RESERVED10 = 10
, GPIO_PINCFG9_FNCSEL9_FPIO = 11
,
GPIO_PINCFG9_FNCSEL9_RESERVED12 = 12
, GPIO_PINCFG9_FNCSEL9_RESERVED13 = 13
, GPIO_PINCFG9_FNCSEL9_RESERVED14 = 14
, GPIO_PINCFG9_FNCSEL9_SCANOUT5 = 15
} |
| |
| enum | GPIO_PINCFG10_NCEPOL10_Enum { GPIO_PINCFG10_NCEPOL10_LOW = 0
, GPIO_PINCFG10_NCEPOL10_HIGH = 1
} |
| |
| enum | GPIO_PINCFG10_NCESRC10_Enum {
GPIO_PINCFG10_NCESRC10_IOM0CE0 = 0
, GPIO_PINCFG10_NCESRC10_IOM0CE1 = 1
, GPIO_PINCFG10_NCESRC10_IOM0CE2 = 2
, GPIO_PINCFG10_NCESRC10_IOM0CE3 = 3
,
GPIO_PINCFG10_NCESRC10_IOM1CE0 = 4
, GPIO_PINCFG10_NCESRC10_IOM1CE1 = 5
, GPIO_PINCFG10_NCESRC10_IOM1CE2 = 6
, GPIO_PINCFG10_NCESRC10_IOM1CE3 = 7
,
GPIO_PINCFG10_NCESRC10_IOM2CE0 = 8
, GPIO_PINCFG10_NCESRC10_IOM2CE1 = 9
, GPIO_PINCFG10_NCESRC10_IOM2CE2 = 10
, GPIO_PINCFG10_NCESRC10_IOM2CE3 = 11
,
GPIO_PINCFG10_NCESRC10_IOM3CE0 = 12
, GPIO_PINCFG10_NCESRC10_IOM3CE1 = 13
, GPIO_PINCFG10_NCESRC10_IOM3CE2 = 14
, GPIO_PINCFG10_NCESRC10_IOM3CE3 = 15
,
GPIO_PINCFG10_NCESRC10_IOM4CE0 = 16
, GPIO_PINCFG10_NCESRC10_IOM4CE1 = 17
, GPIO_PINCFG10_NCESRC10_IOM4CE2 = 18
, GPIO_PINCFG10_NCESRC10_IOM4CE3 = 19
,
GPIO_PINCFG10_NCESRC10_IOM5CE0 = 20
, GPIO_PINCFG10_NCESRC10_IOM5CE1 = 21
, GPIO_PINCFG10_NCESRC10_IOM5CE2 = 22
, GPIO_PINCFG10_NCESRC10_IOM5CE3 = 23
,
GPIO_PINCFG10_NCESRC10_IOM6CE0 = 24
, GPIO_PINCFG10_NCESRC10_IOM6CE1 = 25
, GPIO_PINCFG10_NCESRC10_IOM6CE2 = 26
, GPIO_PINCFG10_NCESRC10_IOM6CE3 = 27
,
GPIO_PINCFG10_NCESRC10_IOM7CE0 = 28
, GPIO_PINCFG10_NCESRC10_IOM7CE1 = 29
, GPIO_PINCFG10_NCESRC10_IOM7CE2 = 30
, GPIO_PINCFG10_NCESRC10_IOM7CE3 = 31
,
GPIO_PINCFG10_NCESRC10_MSPI0CEN0 = 32
, GPIO_PINCFG10_NCESRC10_MSPI0CEN1 = 33
, GPIO_PINCFG10_NCESRC10_MSPI1CEN0 = 34
, GPIO_PINCFG10_NCESRC10_MSPI1CEN1 = 35
,
GPIO_PINCFG10_NCESRC10_MSPI2CEN0 = 36
, GPIO_PINCFG10_NCESRC10_MSPI2CEN1 = 37
, GPIO_PINCFG10_NCESRC10_DC_DPI_DE = 38
, GPIO_PINCFG10_NCESRC10_DISP_CONT_CSX = 39
,
GPIO_PINCFG10_NCESRC10_DC_SPI_CS_N = 40
, GPIO_PINCFG10_NCESRC10_DC_QSPI_CS_N = 41
, GPIO_PINCFG10_NCESRC10_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG10_PULLCFG10_Enum {
GPIO_PINCFG10_PULLCFG10_DIS = 0
, GPIO_PINCFG10_PULLCFG10_PD50K = 1
, GPIO_PINCFG10_PULLCFG10_PU15K = 2
, GPIO_PINCFG10_PULLCFG10_PU6K = 3
,
GPIO_PINCFG10_PULLCFG10_PU12K = 4
, GPIO_PINCFG10_PULLCFG10_PU24K = 5
, GPIO_PINCFG10_PULLCFG10_PU50K = 6
, GPIO_PINCFG10_PULLCFG10_PU100K = 7
} |
| |
| enum | GPIO_PINCFG10_DS10_Enum { GPIO_PINCFG10_DS10_0P1X = 0
, GPIO_PINCFG10_DS10_0P5X = 1
, GPIO_PINCFG10_DS10_0P75X = 2
, GPIO_PINCFG10_DS10_1P0X = 3
} |
| |
| enum | GPIO_PINCFG10_OUTCFG10_Enum { GPIO_PINCFG10_OUTCFG10_DIS = 0
, GPIO_PINCFG10_OUTCFG10_PUSHPULL = 1
, GPIO_PINCFG10_OUTCFG10_OD = 2
, GPIO_PINCFG10_OUTCFG10_TS = 3
} |
| |
| enum | GPIO_PINCFG10_IRPTEN10_Enum { GPIO_PINCFG10_IRPTEN10_DIS = 0
, GPIO_PINCFG10_IRPTEN10_INTFALL = 1
, GPIO_PINCFG10_IRPTEN10_INTRISE = 2
, GPIO_PINCFG10_IRPTEN10_INTANY = 3
} |
| |
| enum | GPIO_PINCFG10_FNCSEL10_Enum {
GPIO_PINCFG10_FNCSEL10_CMPIN0 = 0
, GPIO_PINCFG10_FNCSEL10_TRIG3 = 1
, GPIO_PINCFG10_FNCSEL10_RESERVED2 = 2
, GPIO_PINCFG10_FNCSEL10_GPIO = 3
,
GPIO_PINCFG10_FNCSEL10_M1MISO = 4
, GPIO_PINCFG10_FNCSEL10_RESERVED5 = 5
, GPIO_PINCFG10_FNCSEL10_CT10 = 6
, GPIO_PINCFG10_FNCSEL10_NCE10 = 7
,
GPIO_PINCFG10_FNCSEL10_OBSBUS10 = 8
, GPIO_PINCFG10_FNCSEL10_DISP_TE = 9
, GPIO_PINCFG10_FNCSEL10_RESERVED10 = 10
, GPIO_PINCFG10_FNCSEL10_FPIO = 11
,
GPIO_PINCFG10_FNCSEL10_RESERVED12 = 12
, GPIO_PINCFG10_FNCSEL10_RESERVED13 = 13
, GPIO_PINCFG10_FNCSEL10_RESERVED14 = 14
, GPIO_PINCFG10_FNCSEL10_OPCG_LOAD = 15
} |
| |
| enum | GPIO_PINCFG11_NCEPOL11_Enum { GPIO_PINCFG11_NCEPOL11_LOW = 0
, GPIO_PINCFG11_NCEPOL11_HIGH = 1
} |
| |
| enum | GPIO_PINCFG11_NCESRC11_Enum {
GPIO_PINCFG11_NCESRC11_IOM0CE0 = 0
, GPIO_PINCFG11_NCESRC11_IOM0CE1 = 1
, GPIO_PINCFG11_NCESRC11_IOM0CE2 = 2
, GPIO_PINCFG11_NCESRC11_IOM0CE3 = 3
,
GPIO_PINCFG11_NCESRC11_IOM1CE0 = 4
, GPIO_PINCFG11_NCESRC11_IOM1CE1 = 5
, GPIO_PINCFG11_NCESRC11_IOM1CE2 = 6
, GPIO_PINCFG11_NCESRC11_IOM1CE3 = 7
,
GPIO_PINCFG11_NCESRC11_IOM2CE0 = 8
, GPIO_PINCFG11_NCESRC11_IOM2CE1 = 9
, GPIO_PINCFG11_NCESRC11_IOM2CE2 = 10
, GPIO_PINCFG11_NCESRC11_IOM2CE3 = 11
,
GPIO_PINCFG11_NCESRC11_IOM3CE0 = 12
, GPIO_PINCFG11_NCESRC11_IOM3CE1 = 13
, GPIO_PINCFG11_NCESRC11_IOM3CE2 = 14
, GPIO_PINCFG11_NCESRC11_IOM3CE3 = 15
,
GPIO_PINCFG11_NCESRC11_IOM4CE0 = 16
, GPIO_PINCFG11_NCESRC11_IOM4CE1 = 17
, GPIO_PINCFG11_NCESRC11_IOM4CE2 = 18
, GPIO_PINCFG11_NCESRC11_IOM4CE3 = 19
,
GPIO_PINCFG11_NCESRC11_IOM5CE0 = 20
, GPIO_PINCFG11_NCESRC11_IOM5CE1 = 21
, GPIO_PINCFG11_NCESRC11_IOM5CE2 = 22
, GPIO_PINCFG11_NCESRC11_IOM5CE3 = 23
,
GPIO_PINCFG11_NCESRC11_IOM6CE0 = 24
, GPIO_PINCFG11_NCESRC11_IOM6CE1 = 25
, GPIO_PINCFG11_NCESRC11_IOM6CE2 = 26
, GPIO_PINCFG11_NCESRC11_IOM6CE3 = 27
,
GPIO_PINCFG11_NCESRC11_IOM7CE0 = 28
, GPIO_PINCFG11_NCESRC11_IOM7CE1 = 29
, GPIO_PINCFG11_NCESRC11_IOM7CE2 = 30
, GPIO_PINCFG11_NCESRC11_IOM7CE3 = 31
,
GPIO_PINCFG11_NCESRC11_MSPI0CEN0 = 32
, GPIO_PINCFG11_NCESRC11_MSPI0CEN1 = 33
, GPIO_PINCFG11_NCESRC11_MSPI1CEN0 = 34
, GPIO_PINCFG11_NCESRC11_MSPI1CEN1 = 35
,
GPIO_PINCFG11_NCESRC11_MSPI2CEN0 = 36
, GPIO_PINCFG11_NCESRC11_MSPI2CEN1 = 37
, GPIO_PINCFG11_NCESRC11_DC_DPI_DE = 38
, GPIO_PINCFG11_NCESRC11_DISP_CONT_CSX = 39
,
GPIO_PINCFG11_NCESRC11_DC_SPI_CS_N = 40
, GPIO_PINCFG11_NCESRC11_DC_QSPI_CS_N = 41
, GPIO_PINCFG11_NCESRC11_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG11_PULLCFG11_Enum {
GPIO_PINCFG11_PULLCFG11_DIS = 0
, GPIO_PINCFG11_PULLCFG11_PD50K = 1
, GPIO_PINCFG11_PULLCFG11_PU15K = 2
, GPIO_PINCFG11_PULLCFG11_PU6K = 3
,
GPIO_PINCFG11_PULLCFG11_PU12K = 4
, GPIO_PINCFG11_PULLCFG11_PU24K = 5
, GPIO_PINCFG11_PULLCFG11_PU50K = 6
, GPIO_PINCFG11_PULLCFG11_PU100K = 7
} |
| |
| enum | GPIO_PINCFG11_DS11_Enum { GPIO_PINCFG11_DS11_0P1X = 0
, GPIO_PINCFG11_DS11_0P5X = 1
} |
| |
| enum | GPIO_PINCFG11_OUTCFG11_Enum { GPIO_PINCFG11_OUTCFG11_DIS = 0
, GPIO_PINCFG11_OUTCFG11_PUSHPULL = 1
, GPIO_PINCFG11_OUTCFG11_OD = 2
, GPIO_PINCFG11_OUTCFG11_TS = 3
} |
| |
| enum | GPIO_PINCFG11_IRPTEN11_Enum { GPIO_PINCFG11_IRPTEN11_DIS = 0
, GPIO_PINCFG11_IRPTEN11_INTFALL = 1
, GPIO_PINCFG11_IRPTEN11_INTRISE = 2
, GPIO_PINCFG11_IRPTEN11_INTANY = 3
} |
| |
| enum | GPIO_PINCFG11_FNCSEL11_Enum {
GPIO_PINCFG11_FNCSEL11_CMPIN1 = 0
, GPIO_PINCFG11_FNCSEL11_TRIG0 = 1
, GPIO_PINCFG11_FNCSEL11_I2S0_CLK = 2
, GPIO_PINCFG11_FNCSEL11_GPIO = 3
,
GPIO_PINCFG11_FNCSEL11_UART2RX = 4
, GPIO_PINCFG11_FNCSEL11_UART3RX = 5
, GPIO_PINCFG11_FNCSEL11_CT11 = 6
, GPIO_PINCFG11_FNCSEL11_NCE11 = 7
,
GPIO_PINCFG11_FNCSEL11_OBSBUS11 = 8
, GPIO_PINCFG11_FNCSEL11_RESERVED9 = 9
, GPIO_PINCFG11_FNCSEL11_RESERVED10 = 10
, GPIO_PINCFG11_FNCSEL11_FPIO = 11
,
GPIO_PINCFG11_FNCSEL11_FLB_TCLK = 12
, GPIO_PINCFG11_FNCSEL11_FLLOAD_ADDR = 13
, GPIO_PINCFG11_FNCSEL11_MDA_TCK = 14
, GPIO_PINCFG11_FNCSEL11_SCANIN0 = 15
} |
| |
| enum | GPIO_PINCFG12_NCEPOL12_Enum { GPIO_PINCFG12_NCEPOL12_LOW = 0
, GPIO_PINCFG12_NCEPOL12_HIGH = 1
} |
| |
| enum | GPIO_PINCFG12_NCESRC12_Enum {
GPIO_PINCFG12_NCESRC12_IOM0CE0 = 0
, GPIO_PINCFG12_NCESRC12_IOM0CE1 = 1
, GPIO_PINCFG12_NCESRC12_IOM0CE2 = 2
, GPIO_PINCFG12_NCESRC12_IOM0CE3 = 3
,
GPIO_PINCFG12_NCESRC12_IOM1CE0 = 4
, GPIO_PINCFG12_NCESRC12_IOM1CE1 = 5
, GPIO_PINCFG12_NCESRC12_IOM1CE2 = 6
, GPIO_PINCFG12_NCESRC12_IOM1CE3 = 7
,
GPIO_PINCFG12_NCESRC12_IOM2CE0 = 8
, GPIO_PINCFG12_NCESRC12_IOM2CE1 = 9
, GPIO_PINCFG12_NCESRC12_IOM2CE2 = 10
, GPIO_PINCFG12_NCESRC12_IOM2CE3 = 11
,
GPIO_PINCFG12_NCESRC12_IOM3CE0 = 12
, GPIO_PINCFG12_NCESRC12_IOM3CE1 = 13
, GPIO_PINCFG12_NCESRC12_IOM3CE2 = 14
, GPIO_PINCFG12_NCESRC12_IOM3CE3 = 15
,
GPIO_PINCFG12_NCESRC12_IOM4CE0 = 16
, GPIO_PINCFG12_NCESRC12_IOM4CE1 = 17
, GPIO_PINCFG12_NCESRC12_IOM4CE2 = 18
, GPIO_PINCFG12_NCESRC12_IOM4CE3 = 19
,
GPIO_PINCFG12_NCESRC12_IOM5CE0 = 20
, GPIO_PINCFG12_NCESRC12_IOM5CE1 = 21
, GPIO_PINCFG12_NCESRC12_IOM5CE2 = 22
, GPIO_PINCFG12_NCESRC12_IOM5CE3 = 23
,
GPIO_PINCFG12_NCESRC12_IOM6CE0 = 24
, GPIO_PINCFG12_NCESRC12_IOM6CE1 = 25
, GPIO_PINCFG12_NCESRC12_IOM6CE2 = 26
, GPIO_PINCFG12_NCESRC12_IOM6CE3 = 27
,
GPIO_PINCFG12_NCESRC12_IOM7CE0 = 28
, GPIO_PINCFG12_NCESRC12_IOM7CE1 = 29
, GPIO_PINCFG12_NCESRC12_IOM7CE2 = 30
, GPIO_PINCFG12_NCESRC12_IOM7CE3 = 31
,
GPIO_PINCFG12_NCESRC12_MSPI0CEN0 = 32
, GPIO_PINCFG12_NCESRC12_MSPI0CEN1 = 33
, GPIO_PINCFG12_NCESRC12_MSPI1CEN0 = 34
, GPIO_PINCFG12_NCESRC12_MSPI1CEN1 = 35
,
GPIO_PINCFG12_NCESRC12_MSPI2CEN0 = 36
, GPIO_PINCFG12_NCESRC12_MSPI2CEN1 = 37
, GPIO_PINCFG12_NCESRC12_DC_DPI_DE = 38
, GPIO_PINCFG12_NCESRC12_DISP_CONT_CSX = 39
,
GPIO_PINCFG12_NCESRC12_DC_SPI_CS_N = 40
, GPIO_PINCFG12_NCESRC12_DC_QSPI_CS_N = 41
, GPIO_PINCFG12_NCESRC12_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG12_PULLCFG12_Enum {
GPIO_PINCFG12_PULLCFG12_DIS = 0
, GPIO_PINCFG12_PULLCFG12_PD50K = 1
, GPIO_PINCFG12_PULLCFG12_PU15K = 2
, GPIO_PINCFG12_PULLCFG12_PU6K = 3
,
GPIO_PINCFG12_PULLCFG12_PU12K = 4
, GPIO_PINCFG12_PULLCFG12_PU24K = 5
, GPIO_PINCFG12_PULLCFG12_PU50K = 6
, GPIO_PINCFG12_PULLCFG12_PU100K = 7
} |
| |
| enum | GPIO_PINCFG12_DS12_Enum { GPIO_PINCFG12_DS12_0P1X = 0
, GPIO_PINCFG12_DS12_0P5X = 1
} |
| |
| enum | GPIO_PINCFG12_OUTCFG12_Enum { GPIO_PINCFG12_OUTCFG12_DIS = 0
, GPIO_PINCFG12_OUTCFG12_PUSHPULL = 1
, GPIO_PINCFG12_OUTCFG12_OD = 2
, GPIO_PINCFG12_OUTCFG12_TS = 3
} |
| |
| enum | GPIO_PINCFG12_IRPTEN12_Enum { GPIO_PINCFG12_IRPTEN12_DIS = 0
, GPIO_PINCFG12_IRPTEN12_INTFALL = 1
, GPIO_PINCFG12_IRPTEN12_INTRISE = 2
, GPIO_PINCFG12_IRPTEN12_INTANY = 3
} |
| |
| enum | GPIO_PINCFG12_FNCSEL12_Enum {
GPIO_PINCFG12_FNCSEL12_ADCSE7 = 0
, GPIO_PINCFG12_FNCSEL12_TRIG1 = 1
, GPIO_PINCFG12_FNCSEL12_I2S0_DATA = 2
, GPIO_PINCFG12_FNCSEL12_GPIO = 3
,
GPIO_PINCFG12_FNCSEL12_UART0TX = 4
, GPIO_PINCFG12_FNCSEL12_UART1TX = 5
, GPIO_PINCFG12_FNCSEL12_CT12 = 6
, GPIO_PINCFG12_FNCSEL12_NCE12 = 7
,
GPIO_PINCFG12_FNCSEL12_OBSBUS12 = 8
, GPIO_PINCFG12_FNCSEL12_CMPRF2 = 9
, GPIO_PINCFG12_FNCSEL12_I2S0_SDOUT = 10
, GPIO_PINCFG12_FNCSEL12_FPIO = 11
,
GPIO_PINCFG12_FNCSEL12_RESERVED12 = 12
, GPIO_PINCFG12_FNCSEL12_RESERVED13 = 13
, GPIO_PINCFG12_FNCSEL12_RESERVED14 = 14
, GPIO_PINCFG12_FNCSEL12_SCANOUT3 = 15
} |
| |
| enum | GPIO_PINCFG13_NCEPOL13_Enum { GPIO_PINCFG13_NCEPOL13_LOW = 0
, GPIO_PINCFG13_NCEPOL13_HIGH = 1
} |
| |
| enum | GPIO_PINCFG13_NCESRC13_Enum {
GPIO_PINCFG13_NCESRC13_IOM0CE0 = 0
, GPIO_PINCFG13_NCESRC13_IOM0CE1 = 1
, GPIO_PINCFG13_NCESRC13_IOM0CE2 = 2
, GPIO_PINCFG13_NCESRC13_IOM0CE3 = 3
,
GPIO_PINCFG13_NCESRC13_IOM1CE0 = 4
, GPIO_PINCFG13_NCESRC13_IOM1CE1 = 5
, GPIO_PINCFG13_NCESRC13_IOM1CE2 = 6
, GPIO_PINCFG13_NCESRC13_IOM1CE3 = 7
,
GPIO_PINCFG13_NCESRC13_IOM2CE0 = 8
, GPIO_PINCFG13_NCESRC13_IOM2CE1 = 9
, GPIO_PINCFG13_NCESRC13_IOM2CE2 = 10
, GPIO_PINCFG13_NCESRC13_IOM2CE3 = 11
,
GPIO_PINCFG13_NCESRC13_IOM3CE0 = 12
, GPIO_PINCFG13_NCESRC13_IOM3CE1 = 13
, GPIO_PINCFG13_NCESRC13_IOM3CE2 = 14
, GPIO_PINCFG13_NCESRC13_IOM3CE3 = 15
,
GPIO_PINCFG13_NCESRC13_IOM4CE0 = 16
, GPIO_PINCFG13_NCESRC13_IOM4CE1 = 17
, GPIO_PINCFG13_NCESRC13_IOM4CE2 = 18
, GPIO_PINCFG13_NCESRC13_IOM4CE3 = 19
,
GPIO_PINCFG13_NCESRC13_IOM5CE0 = 20
, GPIO_PINCFG13_NCESRC13_IOM5CE1 = 21
, GPIO_PINCFG13_NCESRC13_IOM5CE2 = 22
, GPIO_PINCFG13_NCESRC13_IOM5CE3 = 23
,
GPIO_PINCFG13_NCESRC13_IOM6CE0 = 24
, GPIO_PINCFG13_NCESRC13_IOM6CE1 = 25
, GPIO_PINCFG13_NCESRC13_IOM6CE2 = 26
, GPIO_PINCFG13_NCESRC13_IOM6CE3 = 27
,
GPIO_PINCFG13_NCESRC13_IOM7CE0 = 28
, GPIO_PINCFG13_NCESRC13_IOM7CE1 = 29
, GPIO_PINCFG13_NCESRC13_IOM7CE2 = 30
, GPIO_PINCFG13_NCESRC13_IOM7CE3 = 31
,
GPIO_PINCFG13_NCESRC13_MSPI0CEN0 = 32
, GPIO_PINCFG13_NCESRC13_MSPI0CEN1 = 33
, GPIO_PINCFG13_NCESRC13_MSPI1CEN0 = 34
, GPIO_PINCFG13_NCESRC13_MSPI1CEN1 = 35
,
GPIO_PINCFG13_NCESRC13_MSPI2CEN0 = 36
, GPIO_PINCFG13_NCESRC13_MSPI2CEN1 = 37
, GPIO_PINCFG13_NCESRC13_DC_DPI_DE = 38
, GPIO_PINCFG13_NCESRC13_DISP_CONT_CSX = 39
,
GPIO_PINCFG13_NCESRC13_DC_SPI_CS_N = 40
, GPIO_PINCFG13_NCESRC13_DC_QSPI_CS_N = 41
, GPIO_PINCFG13_NCESRC13_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG13_PULLCFG13_Enum {
GPIO_PINCFG13_PULLCFG13_DIS = 0
, GPIO_PINCFG13_PULLCFG13_PD50K = 1
, GPIO_PINCFG13_PULLCFG13_PU15K = 2
, GPIO_PINCFG13_PULLCFG13_PU6K = 3
,
GPIO_PINCFG13_PULLCFG13_PU12K = 4
, GPIO_PINCFG13_PULLCFG13_PU24K = 5
, GPIO_PINCFG13_PULLCFG13_PU50K = 6
, GPIO_PINCFG13_PULLCFG13_PU100K = 7
} |
| |
| enum | GPIO_PINCFG13_DS13_Enum { GPIO_PINCFG13_DS13_0P1X = 0
, GPIO_PINCFG13_DS13_0P5X = 1
} |
| |
| enum | GPIO_PINCFG13_OUTCFG13_Enum { GPIO_PINCFG13_OUTCFG13_DIS = 0
, GPIO_PINCFG13_OUTCFG13_PUSHPULL = 1
, GPIO_PINCFG13_OUTCFG13_OD = 2
, GPIO_PINCFG13_OUTCFG13_TS = 3
} |
| |
| enum | GPIO_PINCFG13_IRPTEN13_Enum { GPIO_PINCFG13_IRPTEN13_DIS = 0
, GPIO_PINCFG13_IRPTEN13_INTFALL = 1
, GPIO_PINCFG13_IRPTEN13_INTRISE = 2
, GPIO_PINCFG13_IRPTEN13_INTANY = 3
} |
| |
| enum | GPIO_PINCFG13_FNCSEL13_Enum {
GPIO_PINCFG13_FNCSEL13_ADCSE6 = 0
, GPIO_PINCFG13_FNCSEL13_TRIG2 = 1
, GPIO_PINCFG13_FNCSEL13_I2S0_WS = 2
, GPIO_PINCFG13_FNCSEL13_GPIO = 3
,
GPIO_PINCFG13_FNCSEL13_UART2TX = 4
, GPIO_PINCFG13_FNCSEL13_UART3TX = 5
, GPIO_PINCFG13_FNCSEL13_CT13 = 6
, GPIO_PINCFG13_FNCSEL13_NCE13 = 7
,
GPIO_PINCFG13_FNCSEL13_OBSBUS13 = 8
, GPIO_PINCFG13_FNCSEL13_RESERVED9 = 9
, GPIO_PINCFG13_FNCSEL13_RESERVED10 = 10
, GPIO_PINCFG13_FNCSEL13_FPIO = 11
,
GPIO_PINCFG13_FNCSEL13_FLB_FCLK = 12
, GPIO_PINCFG13_FNCSEL13_FLLOAD_DATA = 13
, GPIO_PINCFG13_FNCSEL13_MDA_TDI = 14
, GPIO_PINCFG13_FNCSEL13_SCANOUT0 = 15
} |
| |
| enum | GPIO_PINCFG14_NCEPOL14_Enum { GPIO_PINCFG14_NCEPOL14_LOW = 0
, GPIO_PINCFG14_NCEPOL14_HIGH = 1
} |
| |
| enum | GPIO_PINCFG14_NCESRC14_Enum {
GPIO_PINCFG14_NCESRC14_IOM0CE0 = 0
, GPIO_PINCFG14_NCESRC14_IOM0CE1 = 1
, GPIO_PINCFG14_NCESRC14_IOM0CE2 = 2
, GPIO_PINCFG14_NCESRC14_IOM0CE3 = 3
,
GPIO_PINCFG14_NCESRC14_IOM1CE0 = 4
, GPIO_PINCFG14_NCESRC14_IOM1CE1 = 5
, GPIO_PINCFG14_NCESRC14_IOM1CE2 = 6
, GPIO_PINCFG14_NCESRC14_IOM1CE3 = 7
,
GPIO_PINCFG14_NCESRC14_IOM2CE0 = 8
, GPIO_PINCFG14_NCESRC14_IOM2CE1 = 9
, GPIO_PINCFG14_NCESRC14_IOM2CE2 = 10
, GPIO_PINCFG14_NCESRC14_IOM2CE3 = 11
,
GPIO_PINCFG14_NCESRC14_IOM3CE0 = 12
, GPIO_PINCFG14_NCESRC14_IOM3CE1 = 13
, GPIO_PINCFG14_NCESRC14_IOM3CE2 = 14
, GPIO_PINCFG14_NCESRC14_IOM3CE3 = 15
,
GPIO_PINCFG14_NCESRC14_IOM4CE0 = 16
, GPIO_PINCFG14_NCESRC14_IOM4CE1 = 17
, GPIO_PINCFG14_NCESRC14_IOM4CE2 = 18
, GPIO_PINCFG14_NCESRC14_IOM4CE3 = 19
,
GPIO_PINCFG14_NCESRC14_IOM5CE0 = 20
, GPIO_PINCFG14_NCESRC14_IOM5CE1 = 21
, GPIO_PINCFG14_NCESRC14_IOM5CE2 = 22
, GPIO_PINCFG14_NCESRC14_IOM5CE3 = 23
,
GPIO_PINCFG14_NCESRC14_IOM6CE0 = 24
, GPIO_PINCFG14_NCESRC14_IOM6CE1 = 25
, GPIO_PINCFG14_NCESRC14_IOM6CE2 = 26
, GPIO_PINCFG14_NCESRC14_IOM6CE3 = 27
,
GPIO_PINCFG14_NCESRC14_IOM7CE0 = 28
, GPIO_PINCFG14_NCESRC14_IOM7CE1 = 29
, GPIO_PINCFG14_NCESRC14_IOM7CE2 = 30
, GPIO_PINCFG14_NCESRC14_IOM7CE3 = 31
,
GPIO_PINCFG14_NCESRC14_MSPI0CEN0 = 32
, GPIO_PINCFG14_NCESRC14_MSPI0CEN1 = 33
, GPIO_PINCFG14_NCESRC14_MSPI1CEN0 = 34
, GPIO_PINCFG14_NCESRC14_MSPI1CEN1 = 35
,
GPIO_PINCFG14_NCESRC14_MSPI2CEN0 = 36
, GPIO_PINCFG14_NCESRC14_MSPI2CEN1 = 37
, GPIO_PINCFG14_NCESRC14_DC_DPI_DE = 38
, GPIO_PINCFG14_NCESRC14_DISP_CONT_CSX = 39
,
GPIO_PINCFG14_NCESRC14_DC_SPI_CS_N = 40
, GPIO_PINCFG14_NCESRC14_DC_QSPI_CS_N = 41
, GPIO_PINCFG14_NCESRC14_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG14_PULLCFG14_Enum {
GPIO_PINCFG14_PULLCFG14_DIS = 0
, GPIO_PINCFG14_PULLCFG14_PD50K = 1
, GPIO_PINCFG14_PULLCFG14_PU15K = 2
, GPIO_PINCFG14_PULLCFG14_PU6K = 3
,
GPIO_PINCFG14_PULLCFG14_PU12K = 4
, GPIO_PINCFG14_PULLCFG14_PU24K = 5
, GPIO_PINCFG14_PULLCFG14_PU50K = 6
, GPIO_PINCFG14_PULLCFG14_PU100K = 7
} |
| |
| enum | GPIO_PINCFG14_DS14_Enum { GPIO_PINCFG14_DS14_0P1X = 0
, GPIO_PINCFG14_DS14_0P5X = 1
} |
| |
| enum | GPIO_PINCFG14_OUTCFG14_Enum { GPIO_PINCFG14_OUTCFG14_DIS = 0
, GPIO_PINCFG14_OUTCFG14_PUSHPULL = 1
, GPIO_PINCFG14_OUTCFG14_OD = 2
, GPIO_PINCFG14_OUTCFG14_TS = 3
} |
| |
| enum | GPIO_PINCFG14_IRPTEN14_Enum { GPIO_PINCFG14_IRPTEN14_DIS = 0
, GPIO_PINCFG14_IRPTEN14_INTFALL = 1
, GPIO_PINCFG14_IRPTEN14_INTRISE = 2
, GPIO_PINCFG14_IRPTEN14_INTANY = 3
} |
| |
| enum | GPIO_PINCFG14_FNCSEL14_Enum {
GPIO_PINCFG14_FNCSEL14_ADCSE5 = 0
, GPIO_PINCFG14_FNCSEL14_TRIG3 = 1
, GPIO_PINCFG14_FNCSEL14_RESERVED2 = 2
, GPIO_PINCFG14_FNCSEL14_GPIO = 3
,
GPIO_PINCFG14_FNCSEL14_MILLI_CLK = 4
, GPIO_PINCFG14_FNCSEL14_UART1RX = 5
, GPIO_PINCFG14_FNCSEL14_CT14 = 6
, GPIO_PINCFG14_FNCSEL14_NCE14 = 7
,
GPIO_PINCFG14_FNCSEL14_OBSBUS14 = 8
, GPIO_PINCFG14_FNCSEL14_RESERVED9 = 9
, GPIO_PINCFG14_FNCSEL14_I2S0_SDIN = 10
, GPIO_PINCFG14_FNCSEL14_FPIO = 11
,
GPIO_PINCFG14_FNCSEL14_RESERVED12 = 12
, GPIO_PINCFG14_FNCSEL14_FLLOAD_ADDR = 13
, GPIO_PINCFG14_FNCSEL14_MDA_TRSTN = 14
, GPIO_PINCFG14_FNCSEL14_SCANOUT2 = 15
} |
| |
| enum | GPIO_PINCFG15_NCEPOL15_Enum { GPIO_PINCFG15_NCEPOL15_LOW = 0
, GPIO_PINCFG15_NCEPOL15_HIGH = 1
} |
| |
| enum | GPIO_PINCFG15_NCESRC15_Enum {
GPIO_PINCFG15_NCESRC15_IOM0CE0 = 0
, GPIO_PINCFG15_NCESRC15_IOM0CE1 = 1
, GPIO_PINCFG15_NCESRC15_IOM0CE2 = 2
, GPIO_PINCFG15_NCESRC15_IOM0CE3 = 3
,
GPIO_PINCFG15_NCESRC15_IOM1CE0 = 4
, GPIO_PINCFG15_NCESRC15_IOM1CE1 = 5
, GPIO_PINCFG15_NCESRC15_IOM1CE2 = 6
, GPIO_PINCFG15_NCESRC15_IOM1CE3 = 7
,
GPIO_PINCFG15_NCESRC15_IOM2CE0 = 8
, GPIO_PINCFG15_NCESRC15_IOM2CE1 = 9
, GPIO_PINCFG15_NCESRC15_IOM2CE2 = 10
, GPIO_PINCFG15_NCESRC15_IOM2CE3 = 11
,
GPIO_PINCFG15_NCESRC15_IOM3CE0 = 12
, GPIO_PINCFG15_NCESRC15_IOM3CE1 = 13
, GPIO_PINCFG15_NCESRC15_IOM3CE2 = 14
, GPIO_PINCFG15_NCESRC15_IOM3CE3 = 15
,
GPIO_PINCFG15_NCESRC15_IOM4CE0 = 16
, GPIO_PINCFG15_NCESRC15_IOM4CE1 = 17
, GPIO_PINCFG15_NCESRC15_IOM4CE2 = 18
, GPIO_PINCFG15_NCESRC15_IOM4CE3 = 19
,
GPIO_PINCFG15_NCESRC15_IOM5CE0 = 20
, GPIO_PINCFG15_NCESRC15_IOM5CE1 = 21
, GPIO_PINCFG15_NCESRC15_IOM5CE2 = 22
, GPIO_PINCFG15_NCESRC15_IOM5CE3 = 23
,
GPIO_PINCFG15_NCESRC15_IOM6CE0 = 24
, GPIO_PINCFG15_NCESRC15_IOM6CE1 = 25
, GPIO_PINCFG15_NCESRC15_IOM6CE2 = 26
, GPIO_PINCFG15_NCESRC15_IOM6CE3 = 27
,
GPIO_PINCFG15_NCESRC15_IOM7CE0 = 28
, GPIO_PINCFG15_NCESRC15_IOM7CE1 = 29
, GPIO_PINCFG15_NCESRC15_IOM7CE2 = 30
, GPIO_PINCFG15_NCESRC15_IOM7CE3 = 31
,
GPIO_PINCFG15_NCESRC15_MSPI0CEN0 = 32
, GPIO_PINCFG15_NCESRC15_MSPI0CEN1 = 33
, GPIO_PINCFG15_NCESRC15_MSPI1CEN0 = 34
, GPIO_PINCFG15_NCESRC15_MSPI1CEN1 = 35
,
GPIO_PINCFG15_NCESRC15_MSPI2CEN0 = 36
, GPIO_PINCFG15_NCESRC15_MSPI2CEN1 = 37
, GPIO_PINCFG15_NCESRC15_DC_DPI_DE = 38
, GPIO_PINCFG15_NCESRC15_DISP_CONT_CSX = 39
,
GPIO_PINCFG15_NCESRC15_DC_SPI_CS_N = 40
, GPIO_PINCFG15_NCESRC15_DC_QSPI_CS_N = 41
, GPIO_PINCFG15_NCESRC15_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG15_PULLCFG15_Enum {
GPIO_PINCFG15_PULLCFG15_DIS = 0
, GPIO_PINCFG15_PULLCFG15_PD50K = 1
, GPIO_PINCFG15_PULLCFG15_PU15K = 2
, GPIO_PINCFG15_PULLCFG15_PU6K = 3
,
GPIO_PINCFG15_PULLCFG15_PU12K = 4
, GPIO_PINCFG15_PULLCFG15_PU24K = 5
, GPIO_PINCFG15_PULLCFG15_PU50K = 6
, GPIO_PINCFG15_PULLCFG15_PU100K = 7
} |
| |
| enum | GPIO_PINCFG15_DS15_Enum { GPIO_PINCFG15_DS15_0P1X = 0
, GPIO_PINCFG15_DS15_0P5X = 1
} |
| |
| enum | GPIO_PINCFG15_OUTCFG15_Enum { GPIO_PINCFG15_OUTCFG15_DIS = 0
, GPIO_PINCFG15_OUTCFG15_PUSHPULL = 1
, GPIO_PINCFG15_OUTCFG15_OD = 2
, GPIO_PINCFG15_OUTCFG15_TS = 3
} |
| |
| enum | GPIO_PINCFG15_IRPTEN15_Enum { GPIO_PINCFG15_IRPTEN15_DIS = 0
, GPIO_PINCFG15_IRPTEN15_INTFALL = 1
, GPIO_PINCFG15_IRPTEN15_INTRISE = 2
, GPIO_PINCFG15_IRPTEN15_INTANY = 3
} |
| |
| enum | GPIO_PINCFG15_FNCSEL15_Enum {
GPIO_PINCFG15_FNCSEL15_ADCSE4 = 0
, GPIO_PINCFG15_FNCSEL15_TRIG0 = 1
, GPIO_PINCFG15_FNCSEL15_RESERVED2 = 2
, GPIO_PINCFG15_FNCSEL15_GPIO = 3
,
GPIO_PINCFG15_FNCSEL15_MILLI_REC_DAT = 4
, GPIO_PINCFG15_FNCSEL15_UART3RX = 5
, GPIO_PINCFG15_FNCSEL15_CT15 = 6
, GPIO_PINCFG15_FNCSEL15_NCE15 = 7
,
GPIO_PINCFG15_FNCSEL15_OBSBUS15 = 8
, GPIO_PINCFG15_FNCSEL15_RESERVED9 = 9
, GPIO_PINCFG15_FNCSEL15_REFCLK_EXT = 10
, GPIO_PINCFG15_FNCSEL15_FPIO = 11
,
GPIO_PINCFG15_FNCSEL15_RESERVED12 = 12
, GPIO_PINCFG15_FNCSEL15_FLLOAD_DATA = 13
, GPIO_PINCFG15_FNCSEL15_RESERVED14 = 14
, GPIO_PINCFG15_FNCSEL15_SCANOUT1 = 15
} |
| |
| enum | GPIO_PINCFG16_NCEPOL16_Enum { GPIO_PINCFG16_NCEPOL16_LOW = 0
, GPIO_PINCFG16_NCEPOL16_HIGH = 1
} |
| |
| enum | GPIO_PINCFG16_NCESRC16_Enum {
GPIO_PINCFG16_NCESRC16_IOM0CE0 = 0
, GPIO_PINCFG16_NCESRC16_IOM0CE1 = 1
, GPIO_PINCFG16_NCESRC16_IOM0CE2 = 2
, GPIO_PINCFG16_NCESRC16_IOM0CE3 = 3
,
GPIO_PINCFG16_NCESRC16_IOM1CE0 = 4
, GPIO_PINCFG16_NCESRC16_IOM1CE1 = 5
, GPIO_PINCFG16_NCESRC16_IOM1CE2 = 6
, GPIO_PINCFG16_NCESRC16_IOM1CE3 = 7
,
GPIO_PINCFG16_NCESRC16_IOM2CE0 = 8
, GPIO_PINCFG16_NCESRC16_IOM2CE1 = 9
, GPIO_PINCFG16_NCESRC16_IOM2CE2 = 10
, GPIO_PINCFG16_NCESRC16_IOM2CE3 = 11
,
GPIO_PINCFG16_NCESRC16_IOM3CE0 = 12
, GPIO_PINCFG16_NCESRC16_IOM3CE1 = 13
, GPIO_PINCFG16_NCESRC16_IOM3CE2 = 14
, GPIO_PINCFG16_NCESRC16_IOM3CE3 = 15
,
GPIO_PINCFG16_NCESRC16_IOM4CE0 = 16
, GPIO_PINCFG16_NCESRC16_IOM4CE1 = 17
, GPIO_PINCFG16_NCESRC16_IOM4CE2 = 18
, GPIO_PINCFG16_NCESRC16_IOM4CE3 = 19
,
GPIO_PINCFG16_NCESRC16_IOM5CE0 = 20
, GPIO_PINCFG16_NCESRC16_IOM5CE1 = 21
, GPIO_PINCFG16_NCESRC16_IOM5CE2 = 22
, GPIO_PINCFG16_NCESRC16_IOM5CE3 = 23
,
GPIO_PINCFG16_NCESRC16_IOM6CE0 = 24
, GPIO_PINCFG16_NCESRC16_IOM6CE1 = 25
, GPIO_PINCFG16_NCESRC16_IOM6CE2 = 26
, GPIO_PINCFG16_NCESRC16_IOM6CE3 = 27
,
GPIO_PINCFG16_NCESRC16_IOM7CE0 = 28
, GPIO_PINCFG16_NCESRC16_IOM7CE1 = 29
, GPIO_PINCFG16_NCESRC16_IOM7CE2 = 30
, GPIO_PINCFG16_NCESRC16_IOM7CE3 = 31
,
GPIO_PINCFG16_NCESRC16_MSPI0CEN0 = 32
, GPIO_PINCFG16_NCESRC16_MSPI0CEN1 = 33
, GPIO_PINCFG16_NCESRC16_MSPI1CEN0 = 34
, GPIO_PINCFG16_NCESRC16_MSPI1CEN1 = 35
,
GPIO_PINCFG16_NCESRC16_MSPI2CEN0 = 36
, GPIO_PINCFG16_NCESRC16_MSPI2CEN1 = 37
, GPIO_PINCFG16_NCESRC16_DC_DPI_DE = 38
, GPIO_PINCFG16_NCESRC16_DISP_CONT_CSX = 39
,
GPIO_PINCFG16_NCESRC16_DC_SPI_CS_N = 40
, GPIO_PINCFG16_NCESRC16_DC_QSPI_CS_N = 41
, GPIO_PINCFG16_NCESRC16_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG16_PULLCFG16_Enum {
GPIO_PINCFG16_PULLCFG16_DIS = 0
, GPIO_PINCFG16_PULLCFG16_PD50K = 1
, GPIO_PINCFG16_PULLCFG16_PU15K = 2
, GPIO_PINCFG16_PULLCFG16_PU6K = 3
,
GPIO_PINCFG16_PULLCFG16_PU12K = 4
, GPIO_PINCFG16_PULLCFG16_PU24K = 5
, GPIO_PINCFG16_PULLCFG16_PU50K = 6
, GPIO_PINCFG16_PULLCFG16_PU100K = 7
} |
| |
| enum | GPIO_PINCFG16_DS16_Enum { GPIO_PINCFG16_DS16_0P1X = 0
, GPIO_PINCFG16_DS16_0P5X = 1
} |
| |
| enum | GPIO_PINCFG16_OUTCFG16_Enum { GPIO_PINCFG16_OUTCFG16_DIS = 0
, GPIO_PINCFG16_OUTCFG16_PUSHPULL = 1
, GPIO_PINCFG16_OUTCFG16_OD = 2
, GPIO_PINCFG16_OUTCFG16_TS = 3
} |
| |
| enum | GPIO_PINCFG16_IRPTEN16_Enum { GPIO_PINCFG16_IRPTEN16_DIS = 0
, GPIO_PINCFG16_IRPTEN16_INTFALL = 1
, GPIO_PINCFG16_IRPTEN16_INTRISE = 2
, GPIO_PINCFG16_IRPTEN16_INTANY = 3
} |
| |
| enum | GPIO_PINCFG16_FNCSEL16_Enum {
GPIO_PINCFG16_FNCSEL16_ADCSE3 = 0
, GPIO_PINCFG16_FNCSEL16_TRIG1 = 1
, GPIO_PINCFG16_FNCSEL16_I2S1_CLK = 2
, GPIO_PINCFG16_FNCSEL16_GPIO = 3
,
GPIO_PINCFG16_FNCSEL16_MILLI_PBDATA1 = 4
, GPIO_PINCFG16_FNCSEL16_UART1RTS = 5
, GPIO_PINCFG16_FNCSEL16_CT16 = 6
, GPIO_PINCFG16_FNCSEL16_NCE16 = 7
,
GPIO_PINCFG16_FNCSEL16_OBSBUS0 = 8
, GPIO_PINCFG16_FNCSEL16_RESERVED9 = 9
, GPIO_PINCFG16_FNCSEL16_RESERVED10 = 10
, GPIO_PINCFG16_FNCSEL16_FPIO = 11
,
GPIO_PINCFG16_FNCSEL16_RESERVED12 = 12
, GPIO_PINCFG16_FNCSEL16_RESERVED13 = 13
, GPIO_PINCFG16_FNCSEL16_RESERVED14 = 14
, GPIO_PINCFG16_FNCSEL16_DFT_RET = 15
} |
| |
| enum | GPIO_PINCFG17_NCEPOL17_Enum { GPIO_PINCFG17_NCEPOL17_LOW = 0
, GPIO_PINCFG17_NCEPOL17_HIGH = 1
} |
| |
| enum | GPIO_PINCFG17_NCESRC17_Enum {
GPIO_PINCFG17_NCESRC17_IOM0CE0 = 0
, GPIO_PINCFG17_NCESRC17_IOM0CE1 = 1
, GPIO_PINCFG17_NCESRC17_IOM0CE2 = 2
, GPIO_PINCFG17_NCESRC17_IOM0CE3 = 3
,
GPIO_PINCFG17_NCESRC17_IOM1CE0 = 4
, GPIO_PINCFG17_NCESRC17_IOM1CE1 = 5
, GPIO_PINCFG17_NCESRC17_IOM1CE2 = 6
, GPIO_PINCFG17_NCESRC17_IOM1CE3 = 7
,
GPIO_PINCFG17_NCESRC17_IOM2CE0 = 8
, GPIO_PINCFG17_NCESRC17_IOM2CE1 = 9
, GPIO_PINCFG17_NCESRC17_IOM2CE2 = 10
, GPIO_PINCFG17_NCESRC17_IOM2CE3 = 11
,
GPIO_PINCFG17_NCESRC17_IOM3CE0 = 12
, GPIO_PINCFG17_NCESRC17_IOM3CE1 = 13
, GPIO_PINCFG17_NCESRC17_IOM3CE2 = 14
, GPIO_PINCFG17_NCESRC17_IOM3CE3 = 15
,
GPIO_PINCFG17_NCESRC17_IOM4CE0 = 16
, GPIO_PINCFG17_NCESRC17_IOM4CE1 = 17
, GPIO_PINCFG17_NCESRC17_IOM4CE2 = 18
, GPIO_PINCFG17_NCESRC17_IOM4CE3 = 19
,
GPIO_PINCFG17_NCESRC17_IOM5CE0 = 20
, GPIO_PINCFG17_NCESRC17_IOM5CE1 = 21
, GPIO_PINCFG17_NCESRC17_IOM5CE2 = 22
, GPIO_PINCFG17_NCESRC17_IOM5CE3 = 23
,
GPIO_PINCFG17_NCESRC17_IOM6CE0 = 24
, GPIO_PINCFG17_NCESRC17_IOM6CE1 = 25
, GPIO_PINCFG17_NCESRC17_IOM6CE2 = 26
, GPIO_PINCFG17_NCESRC17_IOM6CE3 = 27
,
GPIO_PINCFG17_NCESRC17_IOM7CE0 = 28
, GPIO_PINCFG17_NCESRC17_IOM7CE1 = 29
, GPIO_PINCFG17_NCESRC17_IOM7CE2 = 30
, GPIO_PINCFG17_NCESRC17_IOM7CE3 = 31
,
GPIO_PINCFG17_NCESRC17_MSPI0CEN0 = 32
, GPIO_PINCFG17_NCESRC17_MSPI0CEN1 = 33
, GPIO_PINCFG17_NCESRC17_MSPI1CEN0 = 34
, GPIO_PINCFG17_NCESRC17_MSPI1CEN1 = 35
,
GPIO_PINCFG17_NCESRC17_MSPI2CEN0 = 36
, GPIO_PINCFG17_NCESRC17_MSPI2CEN1 = 37
, GPIO_PINCFG17_NCESRC17_DC_DPI_DE = 38
, GPIO_PINCFG17_NCESRC17_DISP_CONT_CSX = 39
,
GPIO_PINCFG17_NCESRC17_DC_SPI_CS_N = 40
, GPIO_PINCFG17_NCESRC17_DC_QSPI_CS_N = 41
, GPIO_PINCFG17_NCESRC17_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG17_PULLCFG17_Enum {
GPIO_PINCFG17_PULLCFG17_DIS = 0
, GPIO_PINCFG17_PULLCFG17_PD50K = 1
, GPIO_PINCFG17_PULLCFG17_PU15K = 2
, GPIO_PINCFG17_PULLCFG17_PU6K = 3
,
GPIO_PINCFG17_PULLCFG17_PU12K = 4
, GPIO_PINCFG17_PULLCFG17_PU24K = 5
, GPIO_PINCFG17_PULLCFG17_PU50K = 6
, GPIO_PINCFG17_PULLCFG17_PU100K = 7
} |
| |
| enum | GPIO_PINCFG17_DS17_Enum { GPIO_PINCFG17_DS17_0P1X = 0
, GPIO_PINCFG17_DS17_0P5X = 1
} |
| |
| enum | GPIO_PINCFG17_OUTCFG17_Enum { GPIO_PINCFG17_OUTCFG17_DIS = 0
, GPIO_PINCFG17_OUTCFG17_PUSHPULL = 1
, GPIO_PINCFG17_OUTCFG17_OD = 2
, GPIO_PINCFG17_OUTCFG17_TS = 3
} |
| |
| enum | GPIO_PINCFG17_IRPTEN17_Enum { GPIO_PINCFG17_IRPTEN17_DIS = 0
, GPIO_PINCFG17_IRPTEN17_INTFALL = 1
, GPIO_PINCFG17_IRPTEN17_INTRISE = 2
, GPIO_PINCFG17_IRPTEN17_INTANY = 3
} |
| |
| enum | GPIO_PINCFG17_FNCSEL17_Enum {
GPIO_PINCFG17_FNCSEL17_ADCSE2 = 0
, GPIO_PINCFG17_FNCSEL17_TRIG2 = 1
, GPIO_PINCFG17_FNCSEL17_I2S1_DATA = 2
, GPIO_PINCFG17_FNCSEL17_GPIO = 3
,
GPIO_PINCFG17_FNCSEL17_MILLI_PBDATA2 = 4
, GPIO_PINCFG17_FNCSEL17_UART3RTS = 5
, GPIO_PINCFG17_FNCSEL17_CT17 = 6
, GPIO_PINCFG17_FNCSEL17_NCE17 = 7
,
GPIO_PINCFG17_FNCSEL17_OBSBUS1 = 8
, GPIO_PINCFG17_FNCSEL17_I2S1_SDOUT = 9
, GPIO_PINCFG17_FNCSEL17_RESERVED10 = 10
, GPIO_PINCFG17_FNCSEL17_FPIO = 11
,
GPIO_PINCFG17_FNCSEL17_RESERVED12 = 12
, GPIO_PINCFG17_FNCSEL17_FLLOAD_STRB = 13
, GPIO_PINCFG17_FNCSEL17_MDA_TMS = 14
, GPIO_PINCFG17_FNCSEL17_OPCG_CLK = 15
} |
| |
| enum | GPIO_PINCFG18_NCEPOL18_Enum { GPIO_PINCFG18_NCEPOL18_LOW = 0
, GPIO_PINCFG18_NCEPOL18_HIGH = 1
} |
| |
| enum | GPIO_PINCFG18_NCESRC18_Enum {
GPIO_PINCFG18_NCESRC18_IOM0CE0 = 0
, GPIO_PINCFG18_NCESRC18_IOM0CE1 = 1
, GPIO_PINCFG18_NCESRC18_IOM0CE2 = 2
, GPIO_PINCFG18_NCESRC18_IOM0CE3 = 3
,
GPIO_PINCFG18_NCESRC18_IOM1CE0 = 4
, GPIO_PINCFG18_NCESRC18_IOM1CE1 = 5
, GPIO_PINCFG18_NCESRC18_IOM1CE2 = 6
, GPIO_PINCFG18_NCESRC18_IOM1CE3 = 7
,
GPIO_PINCFG18_NCESRC18_IOM2CE0 = 8
, GPIO_PINCFG18_NCESRC18_IOM2CE1 = 9
, GPIO_PINCFG18_NCESRC18_IOM2CE2 = 10
, GPIO_PINCFG18_NCESRC18_IOM2CE3 = 11
,
GPIO_PINCFG18_NCESRC18_IOM3CE0 = 12
, GPIO_PINCFG18_NCESRC18_IOM3CE1 = 13
, GPIO_PINCFG18_NCESRC18_IOM3CE2 = 14
, GPIO_PINCFG18_NCESRC18_IOM3CE3 = 15
,
GPIO_PINCFG18_NCESRC18_IOM4CE0 = 16
, GPIO_PINCFG18_NCESRC18_IOM4CE1 = 17
, GPIO_PINCFG18_NCESRC18_IOM4CE2 = 18
, GPIO_PINCFG18_NCESRC18_IOM4CE3 = 19
,
GPIO_PINCFG18_NCESRC18_IOM5CE0 = 20
, GPIO_PINCFG18_NCESRC18_IOM5CE1 = 21
, GPIO_PINCFG18_NCESRC18_IOM5CE2 = 22
, GPIO_PINCFG18_NCESRC18_IOM5CE3 = 23
,
GPIO_PINCFG18_NCESRC18_IOM6CE0 = 24
, GPIO_PINCFG18_NCESRC18_IOM6CE1 = 25
, GPIO_PINCFG18_NCESRC18_IOM6CE2 = 26
, GPIO_PINCFG18_NCESRC18_IOM6CE3 = 27
,
GPIO_PINCFG18_NCESRC18_IOM7CE0 = 28
, GPIO_PINCFG18_NCESRC18_IOM7CE1 = 29
, GPIO_PINCFG18_NCESRC18_IOM7CE2 = 30
, GPIO_PINCFG18_NCESRC18_IOM7CE3 = 31
,
GPIO_PINCFG18_NCESRC18_MSPI0CEN0 = 32
, GPIO_PINCFG18_NCESRC18_MSPI0CEN1 = 33
, GPIO_PINCFG18_NCESRC18_MSPI1CEN0 = 34
, GPIO_PINCFG18_NCESRC18_MSPI1CEN1 = 35
,
GPIO_PINCFG18_NCESRC18_MSPI2CEN0 = 36
, GPIO_PINCFG18_NCESRC18_MSPI2CEN1 = 37
, GPIO_PINCFG18_NCESRC18_DC_DPI_DE = 38
, GPIO_PINCFG18_NCESRC18_DISP_CONT_CSX = 39
,
GPIO_PINCFG18_NCESRC18_DC_SPI_CS_N = 40
, GPIO_PINCFG18_NCESRC18_DC_QSPI_CS_N = 41
, GPIO_PINCFG18_NCESRC18_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG18_PULLCFG18_Enum {
GPIO_PINCFG18_PULLCFG18_DIS = 0
, GPIO_PINCFG18_PULLCFG18_PD50K = 1
, GPIO_PINCFG18_PULLCFG18_PU15K = 2
, GPIO_PINCFG18_PULLCFG18_PU6K = 3
,
GPIO_PINCFG18_PULLCFG18_PU12K = 4
, GPIO_PINCFG18_PULLCFG18_PU24K = 5
, GPIO_PINCFG18_PULLCFG18_PU50K = 6
, GPIO_PINCFG18_PULLCFG18_PU100K = 7
} |
| |
| enum | GPIO_PINCFG18_DS18_Enum { GPIO_PINCFG18_DS18_0P1X = 0
, GPIO_PINCFG18_DS18_0P5X = 1
} |
| |
| enum | GPIO_PINCFG18_OUTCFG18_Enum { GPIO_PINCFG18_OUTCFG18_DIS = 0
, GPIO_PINCFG18_OUTCFG18_PUSHPULL = 1
, GPIO_PINCFG18_OUTCFG18_OD = 2
, GPIO_PINCFG18_OUTCFG18_TS = 3
} |
| |
| enum | GPIO_PINCFG18_IRPTEN18_Enum { GPIO_PINCFG18_IRPTEN18_DIS = 0
, GPIO_PINCFG18_IRPTEN18_INTFALL = 1
, GPIO_PINCFG18_IRPTEN18_INTRISE = 2
, GPIO_PINCFG18_IRPTEN18_INTANY = 3
} |
| |
| enum | GPIO_PINCFG18_FNCSEL18_Enum {
GPIO_PINCFG18_FNCSEL18_ADCSE1 = 0
, GPIO_PINCFG18_FNCSEL18_ANATEST2 = 1
, GPIO_PINCFG18_FNCSEL18_I2S1_WS = 2
, GPIO_PINCFG18_FNCSEL18_GPIO = 3
,
GPIO_PINCFG18_FNCSEL18_UART0CTS = 4
, GPIO_PINCFG18_FNCSEL18_UART1CTS = 5
, GPIO_PINCFG18_FNCSEL18_CT18 = 6
, GPIO_PINCFG18_FNCSEL18_NCE18 = 7
,
GPIO_PINCFG18_FNCSEL18_OBSBUS2 = 8
, GPIO_PINCFG18_FNCSEL18_RESERVED9 = 9
, GPIO_PINCFG18_FNCSEL18_RESERVED10 = 10
, GPIO_PINCFG18_FNCSEL18_FPIO = 11
,
GPIO_PINCFG18_FNCSEL18_FLB_TMS = 12
, GPIO_PINCFG18_FNCSEL18_FLLOAD_DATA = 13
, GPIO_PINCFG18_FNCSEL18_MDA_HFRC_EXT = 14
, GPIO_PINCFG18_FNCSEL18_SCANIN1 = 15
} |
| |
| enum | GPIO_PINCFG19_NCEPOL19_Enum { GPIO_PINCFG19_NCEPOL19_LOW = 0
, GPIO_PINCFG19_NCEPOL19_HIGH = 1
} |
| |
| enum | GPIO_PINCFG19_NCESRC19_Enum {
GPIO_PINCFG19_NCESRC19_IOM0CE0 = 0
, GPIO_PINCFG19_NCESRC19_IOM0CE1 = 1
, GPIO_PINCFG19_NCESRC19_IOM0CE2 = 2
, GPIO_PINCFG19_NCESRC19_IOM0CE3 = 3
,
GPIO_PINCFG19_NCESRC19_IOM1CE0 = 4
, GPIO_PINCFG19_NCESRC19_IOM1CE1 = 5
, GPIO_PINCFG19_NCESRC19_IOM1CE2 = 6
, GPIO_PINCFG19_NCESRC19_IOM1CE3 = 7
,
GPIO_PINCFG19_NCESRC19_IOM2CE0 = 8
, GPIO_PINCFG19_NCESRC19_IOM2CE1 = 9
, GPIO_PINCFG19_NCESRC19_IOM2CE2 = 10
, GPIO_PINCFG19_NCESRC19_IOM2CE3 = 11
,
GPIO_PINCFG19_NCESRC19_IOM3CE0 = 12
, GPIO_PINCFG19_NCESRC19_IOM3CE1 = 13
, GPIO_PINCFG19_NCESRC19_IOM3CE2 = 14
, GPIO_PINCFG19_NCESRC19_IOM3CE3 = 15
,
GPIO_PINCFG19_NCESRC19_IOM4CE0 = 16
, GPIO_PINCFG19_NCESRC19_IOM4CE1 = 17
, GPIO_PINCFG19_NCESRC19_IOM4CE2 = 18
, GPIO_PINCFG19_NCESRC19_IOM4CE3 = 19
,
GPIO_PINCFG19_NCESRC19_IOM5CE0 = 20
, GPIO_PINCFG19_NCESRC19_IOM5CE1 = 21
, GPIO_PINCFG19_NCESRC19_IOM5CE2 = 22
, GPIO_PINCFG19_NCESRC19_IOM5CE3 = 23
,
GPIO_PINCFG19_NCESRC19_IOM6CE0 = 24
, GPIO_PINCFG19_NCESRC19_IOM6CE1 = 25
, GPIO_PINCFG19_NCESRC19_IOM6CE2 = 26
, GPIO_PINCFG19_NCESRC19_IOM6CE3 = 27
,
GPIO_PINCFG19_NCESRC19_IOM7CE0 = 28
, GPIO_PINCFG19_NCESRC19_IOM7CE1 = 29
, GPIO_PINCFG19_NCESRC19_IOM7CE2 = 30
, GPIO_PINCFG19_NCESRC19_IOM7CE3 = 31
,
GPIO_PINCFG19_NCESRC19_MSPI0CEN0 = 32
, GPIO_PINCFG19_NCESRC19_MSPI0CEN1 = 33
, GPIO_PINCFG19_NCESRC19_MSPI1CEN0 = 34
, GPIO_PINCFG19_NCESRC19_MSPI1CEN1 = 35
,
GPIO_PINCFG19_NCESRC19_MSPI2CEN0 = 36
, GPIO_PINCFG19_NCESRC19_MSPI2CEN1 = 37
, GPIO_PINCFG19_NCESRC19_DC_DPI_DE = 38
, GPIO_PINCFG19_NCESRC19_DISP_CONT_CSX = 39
,
GPIO_PINCFG19_NCESRC19_DC_SPI_CS_N = 40
, GPIO_PINCFG19_NCESRC19_DC_QSPI_CS_N = 41
, GPIO_PINCFG19_NCESRC19_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG19_PULLCFG19_Enum {
GPIO_PINCFG19_PULLCFG19_DIS = 0
, GPIO_PINCFG19_PULLCFG19_PD50K = 1
, GPIO_PINCFG19_PULLCFG19_PU15K = 2
, GPIO_PINCFG19_PULLCFG19_PU6K = 3
,
GPIO_PINCFG19_PULLCFG19_PU12K = 4
, GPIO_PINCFG19_PULLCFG19_PU24K = 5
, GPIO_PINCFG19_PULLCFG19_PU50K = 6
, GPIO_PINCFG19_PULLCFG19_PU100K = 7
} |
| |
| enum | GPIO_PINCFG19_DS19_Enum { GPIO_PINCFG19_DS19_0P1X = 0
, GPIO_PINCFG19_DS19_0P5X = 1
} |
| |
| enum | GPIO_PINCFG19_OUTCFG19_Enum { GPIO_PINCFG19_OUTCFG19_DIS = 0
, GPIO_PINCFG19_OUTCFG19_PUSHPULL = 1
, GPIO_PINCFG19_OUTCFG19_OD = 2
, GPIO_PINCFG19_OUTCFG19_TS = 3
} |
| |
| enum | GPIO_PINCFG19_IRPTEN19_Enum { GPIO_PINCFG19_IRPTEN19_DIS = 0
, GPIO_PINCFG19_IRPTEN19_INTFALL = 1
, GPIO_PINCFG19_IRPTEN19_INTRISE = 2
, GPIO_PINCFG19_IRPTEN19_INTANY = 3
} |
| |
| enum | GPIO_PINCFG19_FNCSEL19_Enum {
GPIO_PINCFG19_FNCSEL19_ADCSE0 = 0
, GPIO_PINCFG19_FNCSEL19_ANATEST1 = 1
, GPIO_PINCFG19_FNCSEL19_RESERVED2 = 2
, GPIO_PINCFG19_FNCSEL19_GPIO = 3
,
GPIO_PINCFG19_FNCSEL19_UART2CTS = 4
, GPIO_PINCFG19_FNCSEL19_UART3CTS = 5
, GPIO_PINCFG19_FNCSEL19_CT19 = 6
, GPIO_PINCFG19_FNCSEL19_NCE19 = 7
,
GPIO_PINCFG19_FNCSEL19_OBSBUS3 = 8
, GPIO_PINCFG19_FNCSEL19_I2S1_SDIN = 9
, GPIO_PINCFG19_FNCSEL19_RESERVED10 = 10
, GPIO_PINCFG19_FNCSEL19_FPIO = 11
,
GPIO_PINCFG19_FNCSEL19_FLB_TRSTN = 12
, GPIO_PINCFG19_FNCSEL19_FLLOAD_ADDR = 13
, GPIO_PINCFG19_FNCSEL19_RESERVED14 = 14
, GPIO_PINCFG19_FNCSEL19_SCANIN2 = 15
} |
| |
| enum | GPIO_PINCFG20_NCEPOL20_Enum { GPIO_PINCFG20_NCEPOL20_LOW = 0
, GPIO_PINCFG20_NCEPOL20_HIGH = 1
} |
| |
| enum | GPIO_PINCFG20_NCESRC20_Enum {
GPIO_PINCFG20_NCESRC20_IOM0CE0 = 0
, GPIO_PINCFG20_NCESRC20_IOM0CE1 = 1
, GPIO_PINCFG20_NCESRC20_IOM0CE2 = 2
, GPIO_PINCFG20_NCESRC20_IOM0CE3 = 3
,
GPIO_PINCFG20_NCESRC20_IOM1CE0 = 4
, GPIO_PINCFG20_NCESRC20_IOM1CE1 = 5
, GPIO_PINCFG20_NCESRC20_IOM1CE2 = 6
, GPIO_PINCFG20_NCESRC20_IOM1CE3 = 7
,
GPIO_PINCFG20_NCESRC20_IOM2CE0 = 8
, GPIO_PINCFG20_NCESRC20_IOM2CE1 = 9
, GPIO_PINCFG20_NCESRC20_IOM2CE2 = 10
, GPIO_PINCFG20_NCESRC20_IOM2CE3 = 11
,
GPIO_PINCFG20_NCESRC20_IOM3CE0 = 12
, GPIO_PINCFG20_NCESRC20_IOM3CE1 = 13
, GPIO_PINCFG20_NCESRC20_IOM3CE2 = 14
, GPIO_PINCFG20_NCESRC20_IOM3CE3 = 15
,
GPIO_PINCFG20_NCESRC20_IOM4CE0 = 16
, GPIO_PINCFG20_NCESRC20_IOM4CE1 = 17
, GPIO_PINCFG20_NCESRC20_IOM4CE2 = 18
, GPIO_PINCFG20_NCESRC20_IOM4CE3 = 19
,
GPIO_PINCFG20_NCESRC20_IOM5CE0 = 20
, GPIO_PINCFG20_NCESRC20_IOM5CE1 = 21
, GPIO_PINCFG20_NCESRC20_IOM5CE2 = 22
, GPIO_PINCFG20_NCESRC20_IOM5CE3 = 23
,
GPIO_PINCFG20_NCESRC20_IOM6CE0 = 24
, GPIO_PINCFG20_NCESRC20_IOM6CE1 = 25
, GPIO_PINCFG20_NCESRC20_IOM6CE2 = 26
, GPIO_PINCFG20_NCESRC20_IOM6CE3 = 27
,
GPIO_PINCFG20_NCESRC20_IOM7CE0 = 28
, GPIO_PINCFG20_NCESRC20_IOM7CE1 = 29
, GPIO_PINCFG20_NCESRC20_IOM7CE2 = 30
, GPIO_PINCFG20_NCESRC20_IOM7CE3 = 31
,
GPIO_PINCFG20_NCESRC20_MSPI0CEN0 = 32
, GPIO_PINCFG20_NCESRC20_MSPI0CEN1 = 33
, GPIO_PINCFG20_NCESRC20_MSPI1CEN0 = 34
, GPIO_PINCFG20_NCESRC20_MSPI1CEN1 = 35
,
GPIO_PINCFG20_NCESRC20_MSPI2CEN0 = 36
, GPIO_PINCFG20_NCESRC20_MSPI2CEN1 = 37
, GPIO_PINCFG20_NCESRC20_DC_DPI_DE = 38
, GPIO_PINCFG20_NCESRC20_DISP_CONT_CSX = 39
,
GPIO_PINCFG20_NCESRC20_DC_SPI_CS_N = 40
, GPIO_PINCFG20_NCESRC20_DC_QSPI_CS_N = 41
, GPIO_PINCFG20_NCESRC20_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG20_PULLCFG20_Enum {
GPIO_PINCFG20_PULLCFG20_DIS = 0
, GPIO_PINCFG20_PULLCFG20_PD50K = 1
, GPIO_PINCFG20_PULLCFG20_PU15K = 2
, GPIO_PINCFG20_PULLCFG20_PU6K = 3
,
GPIO_PINCFG20_PULLCFG20_PU12K = 4
, GPIO_PINCFG20_PULLCFG20_PU24K = 5
, GPIO_PINCFG20_PULLCFG20_PU50K = 6
, GPIO_PINCFG20_PULLCFG20_PU100K = 7
} |
| |
| enum | GPIO_PINCFG20_DS20_Enum { GPIO_PINCFG20_DS20_0P1X = 0
, GPIO_PINCFG20_DS20_0P5X = 1
} |
| |
| enum | GPIO_PINCFG20_OUTCFG20_Enum { GPIO_PINCFG20_OUTCFG20_DIS = 0
, GPIO_PINCFG20_OUTCFG20_PUSHPULL = 1
, GPIO_PINCFG20_OUTCFG20_OD = 2
, GPIO_PINCFG20_OUTCFG20_TS = 3
} |
| |
| enum | GPIO_PINCFG20_IRPTEN20_Enum { GPIO_PINCFG20_IRPTEN20_DIS = 0
, GPIO_PINCFG20_IRPTEN20_INTFALL = 1
, GPIO_PINCFG20_IRPTEN20_INTRISE = 2
, GPIO_PINCFG20_IRPTEN20_INTANY = 3
} |
| |
| enum | GPIO_PINCFG20_FNCSEL20_Enum {
GPIO_PINCFG20_FNCSEL20_SWDCK = 0
, GPIO_PINCFG20_FNCSEL20_TRIG1 = 1
, GPIO_PINCFG20_FNCSEL20_RESERVED2 = 2
, GPIO_PINCFG20_FNCSEL20_GPIO = 3
,
GPIO_PINCFG20_FNCSEL20_UART0TX = 4
, GPIO_PINCFG20_FNCSEL20_UART1TX = 5
, GPIO_PINCFG20_FNCSEL20_CT20 = 6
, GPIO_PINCFG20_FNCSEL20_NCE20 = 7
,
GPIO_PINCFG20_FNCSEL20_OBSBUS4 = 8
, GPIO_PINCFG20_FNCSEL20_RESERVED9 = 9
, GPIO_PINCFG20_FNCSEL20_RESERVED10 = 10
, GPIO_PINCFG20_FNCSEL20_FPIO = 11
,
GPIO_PINCFG20_FNCSEL20_RESERVED12 = 12
, GPIO_PINCFG20_FNCSEL20_RESERVED13 = 13
, GPIO_PINCFG20_FNCSEL20_RESERVED14 = 14
, GPIO_PINCFG20_FNCSEL20_SCANCLK = 15
} |
| |
| enum | GPIO_PINCFG21_NCEPOL21_Enum { GPIO_PINCFG21_NCEPOL21_LOW = 0
, GPIO_PINCFG21_NCEPOL21_HIGH = 1
} |
| |
| enum | GPIO_PINCFG21_NCESRC21_Enum {
GPIO_PINCFG21_NCESRC21_IOM0CE0 = 0
, GPIO_PINCFG21_NCESRC21_IOM0CE1 = 1
, GPIO_PINCFG21_NCESRC21_IOM0CE2 = 2
, GPIO_PINCFG21_NCESRC21_IOM0CE3 = 3
,
GPIO_PINCFG21_NCESRC21_IOM1CE0 = 4
, GPIO_PINCFG21_NCESRC21_IOM1CE1 = 5
, GPIO_PINCFG21_NCESRC21_IOM1CE2 = 6
, GPIO_PINCFG21_NCESRC21_IOM1CE3 = 7
,
GPIO_PINCFG21_NCESRC21_IOM2CE0 = 8
, GPIO_PINCFG21_NCESRC21_IOM2CE1 = 9
, GPIO_PINCFG21_NCESRC21_IOM2CE2 = 10
, GPIO_PINCFG21_NCESRC21_IOM2CE3 = 11
,
GPIO_PINCFG21_NCESRC21_IOM3CE0 = 12
, GPIO_PINCFG21_NCESRC21_IOM3CE1 = 13
, GPIO_PINCFG21_NCESRC21_IOM3CE2 = 14
, GPIO_PINCFG21_NCESRC21_IOM3CE3 = 15
,
GPIO_PINCFG21_NCESRC21_IOM4CE0 = 16
, GPIO_PINCFG21_NCESRC21_IOM4CE1 = 17
, GPIO_PINCFG21_NCESRC21_IOM4CE2 = 18
, GPIO_PINCFG21_NCESRC21_IOM4CE3 = 19
,
GPIO_PINCFG21_NCESRC21_IOM5CE0 = 20
, GPIO_PINCFG21_NCESRC21_IOM5CE1 = 21
, GPIO_PINCFG21_NCESRC21_IOM5CE2 = 22
, GPIO_PINCFG21_NCESRC21_IOM5CE3 = 23
,
GPIO_PINCFG21_NCESRC21_IOM6CE0 = 24
, GPIO_PINCFG21_NCESRC21_IOM6CE1 = 25
, GPIO_PINCFG21_NCESRC21_IOM6CE2 = 26
, GPIO_PINCFG21_NCESRC21_IOM6CE3 = 27
,
GPIO_PINCFG21_NCESRC21_IOM7CE0 = 28
, GPIO_PINCFG21_NCESRC21_IOM7CE1 = 29
, GPIO_PINCFG21_NCESRC21_IOM7CE2 = 30
, GPIO_PINCFG21_NCESRC21_IOM7CE3 = 31
,
GPIO_PINCFG21_NCESRC21_MSPI0CEN0 = 32
, GPIO_PINCFG21_NCESRC21_MSPI0CEN1 = 33
, GPIO_PINCFG21_NCESRC21_MSPI1CEN0 = 34
, GPIO_PINCFG21_NCESRC21_MSPI1CEN1 = 35
,
GPIO_PINCFG21_NCESRC21_MSPI2CEN0 = 36
, GPIO_PINCFG21_NCESRC21_MSPI2CEN1 = 37
, GPIO_PINCFG21_NCESRC21_DC_DPI_DE = 38
, GPIO_PINCFG21_NCESRC21_DISP_CONT_CSX = 39
,
GPIO_PINCFG21_NCESRC21_DC_SPI_CS_N = 40
, GPIO_PINCFG21_NCESRC21_DC_QSPI_CS_N = 41
, GPIO_PINCFG21_NCESRC21_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG21_PULLCFG21_Enum {
GPIO_PINCFG21_PULLCFG21_DIS = 0
, GPIO_PINCFG21_PULLCFG21_PD50K = 1
, GPIO_PINCFG21_PULLCFG21_PU15K = 2
, GPIO_PINCFG21_PULLCFG21_PU6K = 3
,
GPIO_PINCFG21_PULLCFG21_PU12K = 4
, GPIO_PINCFG21_PULLCFG21_PU24K = 5
, GPIO_PINCFG21_PULLCFG21_PU50K = 6
, GPIO_PINCFG21_PULLCFG21_PU100K = 7
} |
| |
| enum | GPIO_PINCFG21_DS21_Enum { GPIO_PINCFG21_DS21_0P1X = 0
, GPIO_PINCFG21_DS21_0P5X = 1
} |
| |
| enum | GPIO_PINCFG21_OUTCFG21_Enum { GPIO_PINCFG21_OUTCFG21_DIS = 0
, GPIO_PINCFG21_OUTCFG21_PUSHPULL = 1
, GPIO_PINCFG21_OUTCFG21_OD = 2
, GPIO_PINCFG21_OUTCFG21_TS = 3
} |
| |
| enum | GPIO_PINCFG21_IRPTEN21_Enum { GPIO_PINCFG21_IRPTEN21_DIS = 0
, GPIO_PINCFG21_IRPTEN21_INTFALL = 1
, GPIO_PINCFG21_IRPTEN21_INTRISE = 2
, GPIO_PINCFG21_IRPTEN21_INTANY = 3
} |
| |
| enum | GPIO_PINCFG21_FNCSEL21_Enum {
GPIO_PINCFG21_FNCSEL21_SWDIO = 0
, GPIO_PINCFG21_FNCSEL21_TRIG2 = 1
, GPIO_PINCFG21_FNCSEL21_RESERVED2 = 2
, GPIO_PINCFG21_FNCSEL21_GPIO = 3
,
GPIO_PINCFG21_FNCSEL21_UART2TX = 4
, GPIO_PINCFG21_FNCSEL21_UART3TX = 5
, GPIO_PINCFG21_FNCSEL21_CT21 = 6
, GPIO_PINCFG21_FNCSEL21_NCE21 = 7
,
GPIO_PINCFG21_FNCSEL21_OBSBUS5 = 8
, GPIO_PINCFG21_FNCSEL21_RESERVED9 = 9
, GPIO_PINCFG21_FNCSEL21_RESERVED10 = 10
, GPIO_PINCFG21_FNCSEL21_FPIO = 11
,
GPIO_PINCFG21_FNCSEL21_RESERVED12 = 12
, GPIO_PINCFG21_FNCSEL21_RESERVED13 = 13
, GPIO_PINCFG21_FNCSEL21_RESERVED14 = 14
, GPIO_PINCFG21_FNCSEL21_SCANSHFT = 15
} |
| |
| enum | GPIO_PINCFG22_NCEPOL22_Enum { GPIO_PINCFG22_NCEPOL22_LOW = 0
, GPIO_PINCFG22_NCEPOL22_HIGH = 1
} |
| |
| enum | GPIO_PINCFG22_NCESRC22_Enum {
GPIO_PINCFG22_NCESRC22_IOM0CE0 = 0
, GPIO_PINCFG22_NCESRC22_IOM0CE1 = 1
, GPIO_PINCFG22_NCESRC22_IOM0CE2 = 2
, GPIO_PINCFG22_NCESRC22_IOM0CE3 = 3
,
GPIO_PINCFG22_NCESRC22_IOM1CE0 = 4
, GPIO_PINCFG22_NCESRC22_IOM1CE1 = 5
, GPIO_PINCFG22_NCESRC22_IOM1CE2 = 6
, GPIO_PINCFG22_NCESRC22_IOM1CE3 = 7
,
GPIO_PINCFG22_NCESRC22_IOM2CE0 = 8
, GPIO_PINCFG22_NCESRC22_IOM2CE1 = 9
, GPIO_PINCFG22_NCESRC22_IOM2CE2 = 10
, GPIO_PINCFG22_NCESRC22_IOM2CE3 = 11
,
GPIO_PINCFG22_NCESRC22_IOM3CE0 = 12
, GPIO_PINCFG22_NCESRC22_IOM3CE1 = 13
, GPIO_PINCFG22_NCESRC22_IOM3CE2 = 14
, GPIO_PINCFG22_NCESRC22_IOM3CE3 = 15
,
GPIO_PINCFG22_NCESRC22_IOM4CE0 = 16
, GPIO_PINCFG22_NCESRC22_IOM4CE1 = 17
, GPIO_PINCFG22_NCESRC22_IOM4CE2 = 18
, GPIO_PINCFG22_NCESRC22_IOM4CE3 = 19
,
GPIO_PINCFG22_NCESRC22_IOM5CE0 = 20
, GPIO_PINCFG22_NCESRC22_IOM5CE1 = 21
, GPIO_PINCFG22_NCESRC22_IOM5CE2 = 22
, GPIO_PINCFG22_NCESRC22_IOM5CE3 = 23
,
GPIO_PINCFG22_NCESRC22_IOM6CE0 = 24
, GPIO_PINCFG22_NCESRC22_IOM6CE1 = 25
, GPIO_PINCFG22_NCESRC22_IOM6CE2 = 26
, GPIO_PINCFG22_NCESRC22_IOM6CE3 = 27
,
GPIO_PINCFG22_NCESRC22_IOM7CE0 = 28
, GPIO_PINCFG22_NCESRC22_IOM7CE1 = 29
, GPIO_PINCFG22_NCESRC22_IOM7CE2 = 30
, GPIO_PINCFG22_NCESRC22_IOM7CE3 = 31
,
GPIO_PINCFG22_NCESRC22_MSPI0CEN0 = 32
, GPIO_PINCFG22_NCESRC22_MSPI0CEN1 = 33
, GPIO_PINCFG22_NCESRC22_MSPI1CEN0 = 34
, GPIO_PINCFG22_NCESRC22_MSPI1CEN1 = 35
,
GPIO_PINCFG22_NCESRC22_MSPI2CEN0 = 36
, GPIO_PINCFG22_NCESRC22_MSPI2CEN1 = 37
, GPIO_PINCFG22_NCESRC22_DC_DPI_DE = 38
, GPIO_PINCFG22_NCESRC22_DISP_CONT_CSX = 39
,
GPIO_PINCFG22_NCESRC22_DC_SPI_CS_N = 40
, GPIO_PINCFG22_NCESRC22_DC_QSPI_CS_N = 41
, GPIO_PINCFG22_NCESRC22_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG22_PULLCFG22_Enum {
GPIO_PINCFG22_PULLCFG22_DIS = 0
, GPIO_PINCFG22_PULLCFG22_PD50K = 1
, GPIO_PINCFG22_PULLCFG22_PU15K = 2
, GPIO_PINCFG22_PULLCFG22_PU6K = 3
,
GPIO_PINCFG22_PULLCFG22_PU12K = 4
, GPIO_PINCFG22_PULLCFG22_PU24K = 5
, GPIO_PINCFG22_PULLCFG22_PU50K = 6
, GPIO_PINCFG22_PULLCFG22_PU100K = 7
} |
| |
| enum | GPIO_PINCFG22_DS22_Enum { GPIO_PINCFG22_DS22_0P1X = 0
, GPIO_PINCFG22_DS22_0P5X = 1
, GPIO_PINCFG22_DS22_0P75X = 2
, GPIO_PINCFG22_DS22_1P0X = 3
} |
| |
| enum | GPIO_PINCFG22_OUTCFG22_Enum { GPIO_PINCFG22_OUTCFG22_DIS = 0
, GPIO_PINCFG22_OUTCFG22_PUSHPULL = 1
, GPIO_PINCFG22_OUTCFG22_OD = 2
, GPIO_PINCFG22_OUTCFG22_TS = 3
} |
| |
| enum | GPIO_PINCFG22_IRPTEN22_Enum { GPIO_PINCFG22_IRPTEN22_DIS = 0
, GPIO_PINCFG22_IRPTEN22_INTFALL = 1
, GPIO_PINCFG22_IRPTEN22_INTRISE = 2
, GPIO_PINCFG22_IRPTEN22_INTANY = 3
} |
| |
| enum | GPIO_PINCFG22_FNCSEL22_Enum {
GPIO_PINCFG22_FNCSEL22_M7SCL = 0
, GPIO_PINCFG22_FNCSEL22_M7SCK = 1
, GPIO_PINCFG22_FNCSEL22_SWO = 2
, GPIO_PINCFG22_FNCSEL22_GPIO = 3
,
GPIO_PINCFG22_FNCSEL22_UART0RX = 4
, GPIO_PINCFG22_FNCSEL22_UART1RX = 5
, GPIO_PINCFG22_FNCSEL22_CT22 = 6
, GPIO_PINCFG22_FNCSEL22_NCE22 = 7
,
GPIO_PINCFG22_FNCSEL22_OBSBUS6 = 8
, GPIO_PINCFG22_FNCSEL22_VCMPO = 9
, GPIO_PINCFG22_FNCSEL22_I3CM1_SCL = 10
, GPIO_PINCFG22_FNCSEL22_FPIO = 11
,
GPIO_PINCFG22_FNCSEL22_RESERVED12 = 12
, GPIO_PINCFG22_FNCSEL22_RESERVED13 = 13
, GPIO_PINCFG22_FNCSEL22_RESERVED14 = 14
, GPIO_PINCFG22_FNCSEL22_SCANIN3 = 15
} |
| |
| enum | GPIO_PINCFG23_NCEPOL23_Enum { GPIO_PINCFG23_NCEPOL23_LOW = 0
, GPIO_PINCFG23_NCEPOL23_HIGH = 1
} |
| |
| enum | GPIO_PINCFG23_NCESRC23_Enum {
GPIO_PINCFG23_NCESRC23_IOM0CE0 = 0
, GPIO_PINCFG23_NCESRC23_IOM0CE1 = 1
, GPIO_PINCFG23_NCESRC23_IOM0CE2 = 2
, GPIO_PINCFG23_NCESRC23_IOM0CE3 = 3
,
GPIO_PINCFG23_NCESRC23_IOM1CE0 = 4
, GPIO_PINCFG23_NCESRC23_IOM1CE1 = 5
, GPIO_PINCFG23_NCESRC23_IOM1CE2 = 6
, GPIO_PINCFG23_NCESRC23_IOM1CE3 = 7
,
GPIO_PINCFG23_NCESRC23_IOM2CE0 = 8
, GPIO_PINCFG23_NCESRC23_IOM2CE1 = 9
, GPIO_PINCFG23_NCESRC23_IOM2CE2 = 10
, GPIO_PINCFG23_NCESRC23_IOM2CE3 = 11
,
GPIO_PINCFG23_NCESRC23_IOM3CE0 = 12
, GPIO_PINCFG23_NCESRC23_IOM3CE1 = 13
, GPIO_PINCFG23_NCESRC23_IOM3CE2 = 14
, GPIO_PINCFG23_NCESRC23_IOM3CE3 = 15
,
GPIO_PINCFG23_NCESRC23_IOM4CE0 = 16
, GPIO_PINCFG23_NCESRC23_IOM4CE1 = 17
, GPIO_PINCFG23_NCESRC23_IOM4CE2 = 18
, GPIO_PINCFG23_NCESRC23_IOM4CE3 = 19
,
GPIO_PINCFG23_NCESRC23_IOM5CE0 = 20
, GPIO_PINCFG23_NCESRC23_IOM5CE1 = 21
, GPIO_PINCFG23_NCESRC23_IOM5CE2 = 22
, GPIO_PINCFG23_NCESRC23_IOM5CE3 = 23
,
GPIO_PINCFG23_NCESRC23_IOM6CE0 = 24
, GPIO_PINCFG23_NCESRC23_IOM6CE1 = 25
, GPIO_PINCFG23_NCESRC23_IOM6CE2 = 26
, GPIO_PINCFG23_NCESRC23_IOM6CE3 = 27
,
GPIO_PINCFG23_NCESRC23_IOM7CE0 = 28
, GPIO_PINCFG23_NCESRC23_IOM7CE1 = 29
, GPIO_PINCFG23_NCESRC23_IOM7CE2 = 30
, GPIO_PINCFG23_NCESRC23_IOM7CE3 = 31
,
GPIO_PINCFG23_NCESRC23_MSPI0CEN0 = 32
, GPIO_PINCFG23_NCESRC23_MSPI0CEN1 = 33
, GPIO_PINCFG23_NCESRC23_MSPI1CEN0 = 34
, GPIO_PINCFG23_NCESRC23_MSPI1CEN1 = 35
,
GPIO_PINCFG23_NCESRC23_MSPI2CEN0 = 36
, GPIO_PINCFG23_NCESRC23_MSPI2CEN1 = 37
, GPIO_PINCFG23_NCESRC23_DC_DPI_DE = 38
, GPIO_PINCFG23_NCESRC23_DISP_CONT_CSX = 39
,
GPIO_PINCFG23_NCESRC23_DC_SPI_CS_N = 40
, GPIO_PINCFG23_NCESRC23_DC_QSPI_CS_N = 41
, GPIO_PINCFG23_NCESRC23_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG23_PULLCFG23_Enum {
GPIO_PINCFG23_PULLCFG23_DIS = 0
, GPIO_PINCFG23_PULLCFG23_PD50K = 1
, GPIO_PINCFG23_PULLCFG23_PU15K = 2
, GPIO_PINCFG23_PULLCFG23_PU6K = 3
,
GPIO_PINCFG23_PULLCFG23_PU12K = 4
, GPIO_PINCFG23_PULLCFG23_PU24K = 5
, GPIO_PINCFG23_PULLCFG23_PU50K = 6
, GPIO_PINCFG23_PULLCFG23_PU100K = 7
} |
| |
| enum | GPIO_PINCFG23_DS23_Enum { GPIO_PINCFG23_DS23_0P1X = 0
, GPIO_PINCFG23_DS23_0P5X = 1
, GPIO_PINCFG23_DS23_0P75X = 2
, GPIO_PINCFG23_DS23_1P0X = 3
} |
| |
| enum | GPIO_PINCFG23_OUTCFG23_Enum { GPIO_PINCFG23_OUTCFG23_DIS = 0
, GPIO_PINCFG23_OUTCFG23_PUSHPULL = 1
, GPIO_PINCFG23_OUTCFG23_OD = 2
, GPIO_PINCFG23_OUTCFG23_TS = 3
} |
| |
| enum | GPIO_PINCFG23_IRPTEN23_Enum { GPIO_PINCFG23_IRPTEN23_DIS = 0
, GPIO_PINCFG23_IRPTEN23_INTFALL = 1
, GPIO_PINCFG23_IRPTEN23_INTRISE = 2
, GPIO_PINCFG23_IRPTEN23_INTANY = 3
} |
| |
| enum | GPIO_PINCFG23_FNCSEL23_Enum {
GPIO_PINCFG23_FNCSEL23_M7SDAWIR3 = 0
, GPIO_PINCFG23_FNCSEL23_M7MOSI = 1
, GPIO_PINCFG23_FNCSEL23_SWO = 2
, GPIO_PINCFG23_FNCSEL23_GPIO = 3
,
GPIO_PINCFG23_FNCSEL23_UART2RX = 4
, GPIO_PINCFG23_FNCSEL23_UART3RX = 5
, GPIO_PINCFG23_FNCSEL23_CT23 = 6
, GPIO_PINCFG23_FNCSEL23_NCE23 = 7
,
GPIO_PINCFG23_FNCSEL23_OBSBUS7 = 8
, GPIO_PINCFG23_FNCSEL23_VCMPO = 9
, GPIO_PINCFG23_FNCSEL23_I3CM1_SDA = 10
, GPIO_PINCFG23_FNCSEL23_FPIO = 11
,
GPIO_PINCFG23_FNCSEL23_RESERVED12 = 12
, GPIO_PINCFG23_FNCSEL23_RESERVED13 = 13
, GPIO_PINCFG23_FNCSEL23_RESERVED14 = 14
, GPIO_PINCFG23_FNCSEL23_SCANOUT6 = 15
} |
| |
| enum | GPIO_PINCFG24_NCEPOL24_Enum { GPIO_PINCFG24_NCEPOL24_LOW = 0
, GPIO_PINCFG24_NCEPOL24_HIGH = 1
} |
| |
| enum | GPIO_PINCFG24_NCESRC24_Enum {
GPIO_PINCFG24_NCESRC24_IOM0CE0 = 0
, GPIO_PINCFG24_NCESRC24_IOM0CE1 = 1
, GPIO_PINCFG24_NCESRC24_IOM0CE2 = 2
, GPIO_PINCFG24_NCESRC24_IOM0CE3 = 3
,
GPIO_PINCFG24_NCESRC24_IOM1CE0 = 4
, GPIO_PINCFG24_NCESRC24_IOM1CE1 = 5
, GPIO_PINCFG24_NCESRC24_IOM1CE2 = 6
, GPIO_PINCFG24_NCESRC24_IOM1CE3 = 7
,
GPIO_PINCFG24_NCESRC24_IOM2CE0 = 8
, GPIO_PINCFG24_NCESRC24_IOM2CE1 = 9
, GPIO_PINCFG24_NCESRC24_IOM2CE2 = 10
, GPIO_PINCFG24_NCESRC24_IOM2CE3 = 11
,
GPIO_PINCFG24_NCESRC24_IOM3CE0 = 12
, GPIO_PINCFG24_NCESRC24_IOM3CE1 = 13
, GPIO_PINCFG24_NCESRC24_IOM3CE2 = 14
, GPIO_PINCFG24_NCESRC24_IOM3CE3 = 15
,
GPIO_PINCFG24_NCESRC24_IOM4CE0 = 16
, GPIO_PINCFG24_NCESRC24_IOM4CE1 = 17
, GPIO_PINCFG24_NCESRC24_IOM4CE2 = 18
, GPIO_PINCFG24_NCESRC24_IOM4CE3 = 19
,
GPIO_PINCFG24_NCESRC24_IOM5CE0 = 20
, GPIO_PINCFG24_NCESRC24_IOM5CE1 = 21
, GPIO_PINCFG24_NCESRC24_IOM5CE2 = 22
, GPIO_PINCFG24_NCESRC24_IOM5CE3 = 23
,
GPIO_PINCFG24_NCESRC24_IOM6CE0 = 24
, GPIO_PINCFG24_NCESRC24_IOM6CE1 = 25
, GPIO_PINCFG24_NCESRC24_IOM6CE2 = 26
, GPIO_PINCFG24_NCESRC24_IOM6CE3 = 27
,
GPIO_PINCFG24_NCESRC24_IOM7CE0 = 28
, GPIO_PINCFG24_NCESRC24_IOM7CE1 = 29
, GPIO_PINCFG24_NCESRC24_IOM7CE2 = 30
, GPIO_PINCFG24_NCESRC24_IOM7CE3 = 31
,
GPIO_PINCFG24_NCESRC24_MSPI0CEN0 = 32
, GPIO_PINCFG24_NCESRC24_MSPI0CEN1 = 33
, GPIO_PINCFG24_NCESRC24_MSPI1CEN0 = 34
, GPIO_PINCFG24_NCESRC24_MSPI1CEN1 = 35
,
GPIO_PINCFG24_NCESRC24_MSPI2CEN0 = 36
, GPIO_PINCFG24_NCESRC24_MSPI2CEN1 = 37
, GPIO_PINCFG24_NCESRC24_DC_DPI_DE = 38
, GPIO_PINCFG24_NCESRC24_DISP_CONT_CSX = 39
,
GPIO_PINCFG24_NCESRC24_DC_SPI_CS_N = 40
, GPIO_PINCFG24_NCESRC24_DC_QSPI_CS_N = 41
, GPIO_PINCFG24_NCESRC24_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG24_PULLCFG24_Enum {
GPIO_PINCFG24_PULLCFG24_DIS = 0
, GPIO_PINCFG24_PULLCFG24_PD50K = 1
, GPIO_PINCFG24_PULLCFG24_PU15K = 2
, GPIO_PINCFG24_PULLCFG24_PU6K = 3
,
GPIO_PINCFG24_PULLCFG24_PU12K = 4
, GPIO_PINCFG24_PULLCFG24_PU24K = 5
, GPIO_PINCFG24_PULLCFG24_PU50K = 6
, GPIO_PINCFG24_PULLCFG24_PU100K = 7
} |
| |
| enum | GPIO_PINCFG24_DS24_Enum { GPIO_PINCFG24_DS24_0P1X = 0
, GPIO_PINCFG24_DS24_0P5X = 1
, GPIO_PINCFG24_DS24_0P75X = 2
, GPIO_PINCFG24_DS24_1P0X = 3
} |
| |
| enum | GPIO_PINCFG24_OUTCFG24_Enum { GPIO_PINCFG24_OUTCFG24_DIS = 0
, GPIO_PINCFG24_OUTCFG24_PUSHPULL = 1
, GPIO_PINCFG24_OUTCFG24_OD = 2
, GPIO_PINCFG24_OUTCFG24_TS = 3
} |
| |
| enum | GPIO_PINCFG24_IRPTEN24_Enum { GPIO_PINCFG24_IRPTEN24_DIS = 0
, GPIO_PINCFG24_IRPTEN24_INTFALL = 1
, GPIO_PINCFG24_IRPTEN24_INTRISE = 2
, GPIO_PINCFG24_IRPTEN24_INTANY = 3
} |
| |
| enum | GPIO_PINCFG24_FNCSEL24_Enum {
GPIO_PINCFG24_FNCSEL24_M7MISO = 0
, GPIO_PINCFG24_FNCSEL24_TRIG3 = 1
, GPIO_PINCFG24_FNCSEL24_SWO = 2
, GPIO_PINCFG24_FNCSEL24_GPIO = 3
,
GPIO_PINCFG24_FNCSEL24_UART0RTS = 4
, GPIO_PINCFG24_FNCSEL24_UART1RTS = 5
, GPIO_PINCFG24_FNCSEL24_CT24 = 6
, GPIO_PINCFG24_FNCSEL24_NCE24 = 7
,
GPIO_PINCFG24_FNCSEL24_OBSBUS8 = 8
, GPIO_PINCFG24_FNCSEL24_RESERVED9 = 9
, GPIO_PINCFG24_FNCSEL24_RESERVED10 = 10
, GPIO_PINCFG24_FNCSEL24_FPIO = 11
,
GPIO_PINCFG24_FNCSEL24_RESERVED12 = 12
, GPIO_PINCFG24_FNCSEL24_RESERVED13 = 13
, GPIO_PINCFG24_FNCSEL24_RESERVED14 = 14
, GPIO_PINCFG24_FNCSEL24_SCANOUT7 = 15
} |
| |
| enum | GPIO_PINCFG25_NCEPOL25_Enum { GPIO_PINCFG25_NCEPOL25_LOW = 0
, GPIO_PINCFG25_NCEPOL25_HIGH = 1
} |
| |
| enum | GPIO_PINCFG25_NCESRC25_Enum {
GPIO_PINCFG25_NCESRC25_IOM0CE0 = 0
, GPIO_PINCFG25_NCESRC25_IOM0CE1 = 1
, GPIO_PINCFG25_NCESRC25_IOM0CE2 = 2
, GPIO_PINCFG25_NCESRC25_IOM0CE3 = 3
,
GPIO_PINCFG25_NCESRC25_IOM1CE0 = 4
, GPIO_PINCFG25_NCESRC25_IOM1CE1 = 5
, GPIO_PINCFG25_NCESRC25_IOM1CE2 = 6
, GPIO_PINCFG25_NCESRC25_IOM1CE3 = 7
,
GPIO_PINCFG25_NCESRC25_IOM2CE0 = 8
, GPIO_PINCFG25_NCESRC25_IOM2CE1 = 9
, GPIO_PINCFG25_NCESRC25_IOM2CE2 = 10
, GPIO_PINCFG25_NCESRC25_IOM2CE3 = 11
,
GPIO_PINCFG25_NCESRC25_IOM3CE0 = 12
, GPIO_PINCFG25_NCESRC25_IOM3CE1 = 13
, GPIO_PINCFG25_NCESRC25_IOM3CE2 = 14
, GPIO_PINCFG25_NCESRC25_IOM3CE3 = 15
,
GPIO_PINCFG25_NCESRC25_IOM4CE0 = 16
, GPIO_PINCFG25_NCESRC25_IOM4CE1 = 17
, GPIO_PINCFG25_NCESRC25_IOM4CE2 = 18
, GPIO_PINCFG25_NCESRC25_IOM4CE3 = 19
,
GPIO_PINCFG25_NCESRC25_IOM5CE0 = 20
, GPIO_PINCFG25_NCESRC25_IOM5CE1 = 21
, GPIO_PINCFG25_NCESRC25_IOM5CE2 = 22
, GPIO_PINCFG25_NCESRC25_IOM5CE3 = 23
,
GPIO_PINCFG25_NCESRC25_IOM6CE0 = 24
, GPIO_PINCFG25_NCESRC25_IOM6CE1 = 25
, GPIO_PINCFG25_NCESRC25_IOM6CE2 = 26
, GPIO_PINCFG25_NCESRC25_IOM6CE3 = 27
,
GPIO_PINCFG25_NCESRC25_IOM7CE0 = 28
, GPIO_PINCFG25_NCESRC25_IOM7CE1 = 29
, GPIO_PINCFG25_NCESRC25_IOM7CE2 = 30
, GPIO_PINCFG25_NCESRC25_IOM7CE3 = 31
,
GPIO_PINCFG25_NCESRC25_MSPI0CEN0 = 32
, GPIO_PINCFG25_NCESRC25_MSPI0CEN1 = 33
, GPIO_PINCFG25_NCESRC25_MSPI1CEN0 = 34
, GPIO_PINCFG25_NCESRC25_MSPI1CEN1 = 35
,
GPIO_PINCFG25_NCESRC25_MSPI2CEN0 = 36
, GPIO_PINCFG25_NCESRC25_MSPI2CEN1 = 37
, GPIO_PINCFG25_NCESRC25_DC_DPI_DE = 38
, GPIO_PINCFG25_NCESRC25_DISP_CONT_CSX = 39
,
GPIO_PINCFG25_NCESRC25_DC_SPI_CS_N = 40
, GPIO_PINCFG25_NCESRC25_DC_QSPI_CS_N = 41
, GPIO_PINCFG25_NCESRC25_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG25_PULLCFG25_Enum {
GPIO_PINCFG25_PULLCFG25_DIS = 0
, GPIO_PINCFG25_PULLCFG25_PD50K = 1
, GPIO_PINCFG25_PULLCFG25_PU15K = 2
, GPIO_PINCFG25_PULLCFG25_PU6K = 3
,
GPIO_PINCFG25_PULLCFG25_PU12K = 4
, GPIO_PINCFG25_PULLCFG25_PU24K = 5
, GPIO_PINCFG25_PULLCFG25_PU50K = 6
, GPIO_PINCFG25_PULLCFG25_PU100K = 7
} |
| |
| enum | GPIO_PINCFG25_DS25_Enum { GPIO_PINCFG25_DS25_0P1X = 0
, GPIO_PINCFG25_DS25_0P5X = 1
, GPIO_PINCFG25_DS25_0P75X = 2
, GPIO_PINCFG25_DS25_1P0X = 3
} |
| |
| enum | GPIO_PINCFG25_OUTCFG25_Enum { GPIO_PINCFG25_OUTCFG25_DIS = 0
, GPIO_PINCFG25_OUTCFG25_PUSHPULL = 1
, GPIO_PINCFG25_OUTCFG25_OD = 2
, GPIO_PINCFG25_OUTCFG25_TS = 3
} |
| |
| enum | GPIO_PINCFG25_IRPTEN25_Enum { GPIO_PINCFG25_IRPTEN25_DIS = 0
, GPIO_PINCFG25_IRPTEN25_INTFALL = 1
, GPIO_PINCFG25_IRPTEN25_INTRISE = 2
, GPIO_PINCFG25_IRPTEN25_INTANY = 3
} |
| |
| enum | GPIO_PINCFG25_FNCSEL25_Enum {
GPIO_PINCFG25_FNCSEL25_M2SCL = 0
, GPIO_PINCFG25_FNCSEL25_M2SCK = 1
, GPIO_PINCFG25_FNCSEL25_RESERVED2 = 2
, GPIO_PINCFG25_FNCSEL25_GPIO = 3
,
GPIO_PINCFG25_FNCSEL25_LFRC_EXT = 4
, GPIO_PINCFG25_FNCSEL25_DSP_TMS = 5
, GPIO_PINCFG25_FNCSEL25_CT25 = 6
, GPIO_PINCFG25_FNCSEL25_NCE25 = 7
,
GPIO_PINCFG25_FNCSEL25_OBSBUS9 = 8
, GPIO_PINCFG25_FNCSEL25_RESERVED9 = 9
, GPIO_PINCFG25_FNCSEL25_RESERVED10 = 10
, GPIO_PINCFG25_FNCSEL25_FPIO = 11
,
GPIO_PINCFG25_FNCSEL25_RESERVED12 = 12
, GPIO_PINCFG25_FNCSEL25_RESERVED13 = 13
, GPIO_PINCFG25_FNCSEL25_RESERVED14 = 14
, GPIO_PINCFG25_FNCSEL25_SCANIN8 = 15
} |
| |
| enum | GPIO_PINCFG26_NCEPOL26_Enum { GPIO_PINCFG26_NCEPOL26_LOW = 0
, GPIO_PINCFG26_NCEPOL26_HIGH = 1
} |
| |
| enum | GPIO_PINCFG26_NCESRC26_Enum {
GPIO_PINCFG26_NCESRC26_IOM0CE0 = 0
, GPIO_PINCFG26_NCESRC26_IOM0CE1 = 1
, GPIO_PINCFG26_NCESRC26_IOM0CE2 = 2
, GPIO_PINCFG26_NCESRC26_IOM0CE3 = 3
,
GPIO_PINCFG26_NCESRC26_IOM1CE0 = 4
, GPIO_PINCFG26_NCESRC26_IOM1CE1 = 5
, GPIO_PINCFG26_NCESRC26_IOM1CE2 = 6
, GPIO_PINCFG26_NCESRC26_IOM1CE3 = 7
,
GPIO_PINCFG26_NCESRC26_IOM2CE0 = 8
, GPIO_PINCFG26_NCESRC26_IOM2CE1 = 9
, GPIO_PINCFG26_NCESRC26_IOM2CE2 = 10
, GPIO_PINCFG26_NCESRC26_IOM2CE3 = 11
,
GPIO_PINCFG26_NCESRC26_IOM3CE0 = 12
, GPIO_PINCFG26_NCESRC26_IOM3CE1 = 13
, GPIO_PINCFG26_NCESRC26_IOM3CE2 = 14
, GPIO_PINCFG26_NCESRC26_IOM3CE3 = 15
,
GPIO_PINCFG26_NCESRC26_IOM4CE0 = 16
, GPIO_PINCFG26_NCESRC26_IOM4CE1 = 17
, GPIO_PINCFG26_NCESRC26_IOM4CE2 = 18
, GPIO_PINCFG26_NCESRC26_IOM4CE3 = 19
,
GPIO_PINCFG26_NCESRC26_IOM5CE0 = 20
, GPIO_PINCFG26_NCESRC26_IOM5CE1 = 21
, GPIO_PINCFG26_NCESRC26_IOM5CE2 = 22
, GPIO_PINCFG26_NCESRC26_IOM5CE3 = 23
,
GPIO_PINCFG26_NCESRC26_IOM6CE0 = 24
, GPIO_PINCFG26_NCESRC26_IOM6CE1 = 25
, GPIO_PINCFG26_NCESRC26_IOM6CE2 = 26
, GPIO_PINCFG26_NCESRC26_IOM6CE3 = 27
,
GPIO_PINCFG26_NCESRC26_IOM7CE0 = 28
, GPIO_PINCFG26_NCESRC26_IOM7CE1 = 29
, GPIO_PINCFG26_NCESRC26_IOM7CE2 = 30
, GPIO_PINCFG26_NCESRC26_IOM7CE3 = 31
,
GPIO_PINCFG26_NCESRC26_MSPI0CEN0 = 32
, GPIO_PINCFG26_NCESRC26_MSPI0CEN1 = 33
, GPIO_PINCFG26_NCESRC26_MSPI1CEN0 = 34
, GPIO_PINCFG26_NCESRC26_MSPI1CEN1 = 35
,
GPIO_PINCFG26_NCESRC26_MSPI2CEN0 = 36
, GPIO_PINCFG26_NCESRC26_MSPI2CEN1 = 37
, GPIO_PINCFG26_NCESRC26_DC_DPI_DE = 38
, GPIO_PINCFG26_NCESRC26_DISP_CONT_CSX = 39
,
GPIO_PINCFG26_NCESRC26_DC_SPI_CS_N = 40
, GPIO_PINCFG26_NCESRC26_DC_QSPI_CS_N = 41
, GPIO_PINCFG26_NCESRC26_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG26_PULLCFG26_Enum {
GPIO_PINCFG26_PULLCFG26_DIS = 0
, GPIO_PINCFG26_PULLCFG26_PD50K = 1
, GPIO_PINCFG26_PULLCFG26_PU15K = 2
, GPIO_PINCFG26_PULLCFG26_PU6K = 3
,
GPIO_PINCFG26_PULLCFG26_PU12K = 4
, GPIO_PINCFG26_PULLCFG26_PU24K = 5
, GPIO_PINCFG26_PULLCFG26_PU50K = 6
, GPIO_PINCFG26_PULLCFG26_PU100K = 7
} |
| |
| enum | GPIO_PINCFG26_DS26_Enum { GPIO_PINCFG26_DS26_0P1X = 0
, GPIO_PINCFG26_DS26_0P5X = 1
, GPIO_PINCFG26_DS26_0P75X = 2
, GPIO_PINCFG26_DS26_1P0X = 3
} |
| |
| enum | GPIO_PINCFG26_OUTCFG26_Enum { GPIO_PINCFG26_OUTCFG26_DIS = 0
, GPIO_PINCFG26_OUTCFG26_PUSHPULL = 1
, GPIO_PINCFG26_OUTCFG26_OD = 2
, GPIO_PINCFG26_OUTCFG26_TS = 3
} |
| |
| enum | GPIO_PINCFG26_IRPTEN26_Enum { GPIO_PINCFG26_IRPTEN26_DIS = 0
, GPIO_PINCFG26_IRPTEN26_INTFALL = 1
, GPIO_PINCFG26_IRPTEN26_INTRISE = 2
, GPIO_PINCFG26_IRPTEN26_INTANY = 3
} |
| |
| enum | GPIO_PINCFG26_FNCSEL26_Enum {
GPIO_PINCFG26_FNCSEL26_M2SDAWIR3 = 0
, GPIO_PINCFG26_FNCSEL26_M2MOSI = 1
, GPIO_PINCFG26_FNCSEL26_RESERVED2 = 2
, GPIO_PINCFG26_FNCSEL26_GPIO = 3
,
GPIO_PINCFG26_FNCSEL26_HFRC_EXT = 4
, GPIO_PINCFG26_FNCSEL26_RESERVED5 = 5
, GPIO_PINCFG26_FNCSEL26_CT26 = 6
, GPIO_PINCFG26_FNCSEL26_NCE26 = 7
,
GPIO_PINCFG26_FNCSEL26_OBSBUS10 = 8
, GPIO_PINCFG26_FNCSEL26_VCMPO = 9
, GPIO_PINCFG26_FNCSEL26_RESERVED10 = 10
, GPIO_PINCFG26_FNCSEL26_FPIO = 11
,
GPIO_PINCFG26_FNCSEL26_RESERVED12 = 12
, GPIO_PINCFG26_FNCSEL26_RESERVED13 = 13
, GPIO_PINCFG26_FNCSEL26_RESERVED14 = 14
, GPIO_PINCFG26_FNCSEL26_SCANIN9 = 15
} |
| |
| enum | GPIO_PINCFG27_NCEPOL27_Enum { GPIO_PINCFG27_NCEPOL27_LOW = 0
, GPIO_PINCFG27_NCEPOL27_HIGH = 1
} |
| |
| enum | GPIO_PINCFG27_NCESRC27_Enum {
GPIO_PINCFG27_NCESRC27_IOM0CE0 = 0
, GPIO_PINCFG27_NCESRC27_IOM0CE1 = 1
, GPIO_PINCFG27_NCESRC27_IOM0CE2 = 2
, GPIO_PINCFG27_NCESRC27_IOM0CE3 = 3
,
GPIO_PINCFG27_NCESRC27_IOM1CE0 = 4
, GPIO_PINCFG27_NCESRC27_IOM1CE1 = 5
, GPIO_PINCFG27_NCESRC27_IOM1CE2 = 6
, GPIO_PINCFG27_NCESRC27_IOM1CE3 = 7
,
GPIO_PINCFG27_NCESRC27_IOM2CE0 = 8
, GPIO_PINCFG27_NCESRC27_IOM2CE1 = 9
, GPIO_PINCFG27_NCESRC27_IOM2CE2 = 10
, GPIO_PINCFG27_NCESRC27_IOM2CE3 = 11
,
GPIO_PINCFG27_NCESRC27_IOM3CE0 = 12
, GPIO_PINCFG27_NCESRC27_IOM3CE1 = 13
, GPIO_PINCFG27_NCESRC27_IOM3CE2 = 14
, GPIO_PINCFG27_NCESRC27_IOM3CE3 = 15
,
GPIO_PINCFG27_NCESRC27_IOM4CE0 = 16
, GPIO_PINCFG27_NCESRC27_IOM4CE1 = 17
, GPIO_PINCFG27_NCESRC27_IOM4CE2 = 18
, GPIO_PINCFG27_NCESRC27_IOM4CE3 = 19
,
GPIO_PINCFG27_NCESRC27_IOM5CE0 = 20
, GPIO_PINCFG27_NCESRC27_IOM5CE1 = 21
, GPIO_PINCFG27_NCESRC27_IOM5CE2 = 22
, GPIO_PINCFG27_NCESRC27_IOM5CE3 = 23
,
GPIO_PINCFG27_NCESRC27_IOM6CE0 = 24
, GPIO_PINCFG27_NCESRC27_IOM6CE1 = 25
, GPIO_PINCFG27_NCESRC27_IOM6CE2 = 26
, GPIO_PINCFG27_NCESRC27_IOM6CE3 = 27
,
GPIO_PINCFG27_NCESRC27_IOM7CE0 = 28
, GPIO_PINCFG27_NCESRC27_IOM7CE1 = 29
, GPIO_PINCFG27_NCESRC27_IOM7CE2 = 30
, GPIO_PINCFG27_NCESRC27_IOM7CE3 = 31
,
GPIO_PINCFG27_NCESRC27_MSPI0CEN0 = 32
, GPIO_PINCFG27_NCESRC27_MSPI0CEN1 = 33
, GPIO_PINCFG27_NCESRC27_MSPI1CEN0 = 34
, GPIO_PINCFG27_NCESRC27_MSPI1CEN1 = 35
,
GPIO_PINCFG27_NCESRC27_MSPI2CEN0 = 36
, GPIO_PINCFG27_NCESRC27_MSPI2CEN1 = 37
, GPIO_PINCFG27_NCESRC27_DC_DPI_DE = 38
, GPIO_PINCFG27_NCESRC27_DISP_CONT_CSX = 39
,
GPIO_PINCFG27_NCESRC27_DC_SPI_CS_N = 40
, GPIO_PINCFG27_NCESRC27_DC_QSPI_CS_N = 41
, GPIO_PINCFG27_NCESRC27_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG27_PULLCFG27_Enum {
GPIO_PINCFG27_PULLCFG27_DIS = 0
, GPIO_PINCFG27_PULLCFG27_PD50K = 1
, GPIO_PINCFG27_PULLCFG27_PU15K = 2
, GPIO_PINCFG27_PULLCFG27_PU6K = 3
,
GPIO_PINCFG27_PULLCFG27_PU12K = 4
, GPIO_PINCFG27_PULLCFG27_PU24K = 5
, GPIO_PINCFG27_PULLCFG27_PU50K = 6
, GPIO_PINCFG27_PULLCFG27_PU100K = 7
} |
| |
| enum | GPIO_PINCFG27_DS27_Enum { GPIO_PINCFG27_DS27_0P1X = 0
, GPIO_PINCFG27_DS27_0P5X = 1
, GPIO_PINCFG27_DS27_0P75X = 2
, GPIO_PINCFG27_DS27_1P0X = 3
} |
| |
| enum | GPIO_PINCFG27_OUTCFG27_Enum { GPIO_PINCFG27_OUTCFG27_DIS = 0
, GPIO_PINCFG27_OUTCFG27_PUSHPULL = 1
, GPIO_PINCFG27_OUTCFG27_OD = 2
, GPIO_PINCFG27_OUTCFG27_TS = 3
} |
| |
| enum | GPIO_PINCFG27_IRPTEN27_Enum { GPIO_PINCFG27_IRPTEN27_DIS = 0
, GPIO_PINCFG27_IRPTEN27_INTFALL = 1
, GPIO_PINCFG27_IRPTEN27_INTRISE = 2
, GPIO_PINCFG27_IRPTEN27_INTANY = 3
} |
| |
| enum | GPIO_PINCFG27_FNCSEL27_Enum {
GPIO_PINCFG27_FNCSEL27_M2MISO = 0
, GPIO_PINCFG27_FNCSEL27_TRIG0 = 1
, GPIO_PINCFG27_FNCSEL27_RESERVED2 = 2
, GPIO_PINCFG27_FNCSEL27_GPIO = 3
,
GPIO_PINCFG27_FNCSEL27_XT_EXT = 4
, GPIO_PINCFG27_FNCSEL27_DSP_TCK = 5
, GPIO_PINCFG27_FNCSEL27_CT27 = 6
, GPIO_PINCFG27_FNCSEL27_NCE27 = 7
,
GPIO_PINCFG27_FNCSEL27_OBSBUS11 = 8
, GPIO_PINCFG27_FNCSEL27_I2S0_SDIN = 9
, GPIO_PINCFG27_FNCSEL27_RESERVED10 = 10
, GPIO_PINCFG27_FNCSEL27_FPIO = 11
,
GPIO_PINCFG27_FNCSEL27_RESERVED12 = 12
, GPIO_PINCFG27_FNCSEL27_RESERVED13 = 13
, GPIO_PINCFG27_FNCSEL27_RESERVED14 = 14
, GPIO_PINCFG27_FNCSEL27_SCANIN10 = 15
} |
| |
| enum | GPIO_PINCFG28_NCEPOL28_Enum { GPIO_PINCFG28_NCEPOL28_LOW = 0
, GPIO_PINCFG28_NCEPOL28_HIGH = 1
} |
| |
| enum | GPIO_PINCFG28_NCESRC28_Enum {
GPIO_PINCFG28_NCESRC28_IOM0CE0 = 0
, GPIO_PINCFG28_NCESRC28_IOM0CE1 = 1
, GPIO_PINCFG28_NCESRC28_IOM0CE2 = 2
, GPIO_PINCFG28_NCESRC28_IOM0CE3 = 3
,
GPIO_PINCFG28_NCESRC28_IOM1CE0 = 4
, GPIO_PINCFG28_NCESRC28_IOM1CE1 = 5
, GPIO_PINCFG28_NCESRC28_IOM1CE2 = 6
, GPIO_PINCFG28_NCESRC28_IOM1CE3 = 7
,
GPIO_PINCFG28_NCESRC28_IOM2CE0 = 8
, GPIO_PINCFG28_NCESRC28_IOM2CE1 = 9
, GPIO_PINCFG28_NCESRC28_IOM2CE2 = 10
, GPIO_PINCFG28_NCESRC28_IOM2CE3 = 11
,
GPIO_PINCFG28_NCESRC28_IOM3CE0 = 12
, GPIO_PINCFG28_NCESRC28_IOM3CE1 = 13
, GPIO_PINCFG28_NCESRC28_IOM3CE2 = 14
, GPIO_PINCFG28_NCESRC28_IOM3CE3 = 15
,
GPIO_PINCFG28_NCESRC28_IOM4CE0 = 16
, GPIO_PINCFG28_NCESRC28_IOM4CE1 = 17
, GPIO_PINCFG28_NCESRC28_IOM4CE2 = 18
, GPIO_PINCFG28_NCESRC28_IOM4CE3 = 19
,
GPIO_PINCFG28_NCESRC28_IOM5CE0 = 20
, GPIO_PINCFG28_NCESRC28_IOM5CE1 = 21
, GPIO_PINCFG28_NCESRC28_IOM5CE2 = 22
, GPIO_PINCFG28_NCESRC28_IOM5CE3 = 23
,
GPIO_PINCFG28_NCESRC28_IOM6CE0 = 24
, GPIO_PINCFG28_NCESRC28_IOM6CE1 = 25
, GPIO_PINCFG28_NCESRC28_IOM6CE2 = 26
, GPIO_PINCFG28_NCESRC28_IOM6CE3 = 27
,
GPIO_PINCFG28_NCESRC28_IOM7CE0 = 28
, GPIO_PINCFG28_NCESRC28_IOM7CE1 = 29
, GPIO_PINCFG28_NCESRC28_IOM7CE2 = 30
, GPIO_PINCFG28_NCESRC28_IOM7CE3 = 31
,
GPIO_PINCFG28_NCESRC28_MSPI0CEN0 = 32
, GPIO_PINCFG28_NCESRC28_MSPI0CEN1 = 33
, GPIO_PINCFG28_NCESRC28_MSPI1CEN0 = 34
, GPIO_PINCFG28_NCESRC28_MSPI1CEN1 = 35
,
GPIO_PINCFG28_NCESRC28_MSPI2CEN0 = 36
, GPIO_PINCFG28_NCESRC28_MSPI2CEN1 = 37
, GPIO_PINCFG28_NCESRC28_DC_DPI_DE = 38
, GPIO_PINCFG28_NCESRC28_DISP_CONT_CSX = 39
,
GPIO_PINCFG28_NCESRC28_DC_SPI_CS_N = 40
, GPIO_PINCFG28_NCESRC28_DC_QSPI_CS_N = 41
, GPIO_PINCFG28_NCESRC28_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG28_PULLCFG28_Enum {
GPIO_PINCFG28_PULLCFG28_DIS = 0
, GPIO_PINCFG28_PULLCFG28_PD50K = 1
, GPIO_PINCFG28_PULLCFG28_PU15K = 2
, GPIO_PINCFG28_PULLCFG28_PU6K = 3
,
GPIO_PINCFG28_PULLCFG28_PU12K = 4
, GPIO_PINCFG28_PULLCFG28_PU24K = 5
, GPIO_PINCFG28_PULLCFG28_PU50K = 6
, GPIO_PINCFG28_PULLCFG28_PU100K = 7
} |
| |
| enum | GPIO_PINCFG28_DS28_Enum { GPIO_PINCFG28_DS28_0P1X = 0
, GPIO_PINCFG28_DS28_0P5X = 1
} |
| |
| enum | GPIO_PINCFG28_OUTCFG28_Enum { GPIO_PINCFG28_OUTCFG28_DIS = 0
, GPIO_PINCFG28_OUTCFG28_PUSHPULL = 1
, GPIO_PINCFG28_OUTCFG28_OD = 2
, GPIO_PINCFG28_OUTCFG28_TS = 3
} |
| |
| enum | GPIO_PINCFG28_IRPTEN28_Enum { GPIO_PINCFG28_IRPTEN28_DIS = 0
, GPIO_PINCFG28_IRPTEN28_INTFALL = 1
, GPIO_PINCFG28_IRPTEN28_INTRISE = 2
, GPIO_PINCFG28_IRPTEN28_INTANY = 3
} |
| |
| enum | GPIO_PINCFG28_FNCSEL28_Enum {
GPIO_PINCFG28_FNCSEL28_SWO = 0
, GPIO_PINCFG28_FNCSEL28_VCMPO = 1
, GPIO_PINCFG28_FNCSEL28_I2S0_CLK = 2
, GPIO_PINCFG28_FNCSEL28_GPIO = 3
,
GPIO_PINCFG28_FNCSEL28_UART2CTS = 4
, GPIO_PINCFG28_FNCSEL28_DSP_TDO = 5
, GPIO_PINCFG28_FNCSEL28_CT28 = 6
, GPIO_PINCFG28_FNCSEL28_NCE28 = 7
,
GPIO_PINCFG28_FNCSEL28_OBSBUS12 = 8
, GPIO_PINCFG28_FNCSEL28_RESERVED9 = 9
, GPIO_PINCFG28_FNCSEL28_RESERVED10 = 10
, GPIO_PINCFG28_FNCSEL28_FPIO = 11
,
GPIO_PINCFG28_FNCSEL28_RESERVED12 = 12
, GPIO_PINCFG28_FNCSEL28_RESERVED13 = 13
, GPIO_PINCFG28_FNCSEL28_RESERVED14 = 14
, GPIO_PINCFG28_FNCSEL28_CME = 15
} |
| |
| enum | GPIO_PINCFG29_VSSPWRSWEN29_Enum { GPIO_PINCFG29_VSSPWRSWEN29_DIS = 0
, GPIO_PINCFG29_VSSPWRSWEN29_EN = 1
} |
| |
| enum | GPIO_PINCFG29_NCEPOL29_Enum { GPIO_PINCFG29_NCEPOL29_LOW = 0
, GPIO_PINCFG29_NCEPOL29_HIGH = 1
} |
| |
| enum | GPIO_PINCFG29_NCESRC29_Enum {
GPIO_PINCFG29_NCESRC29_IOM0CE0 = 0
, GPIO_PINCFG29_NCESRC29_IOM0CE1 = 1
, GPIO_PINCFG29_NCESRC29_IOM0CE2 = 2
, GPIO_PINCFG29_NCESRC29_IOM0CE3 = 3
,
GPIO_PINCFG29_NCESRC29_IOM1CE0 = 4
, GPIO_PINCFG29_NCESRC29_IOM1CE1 = 5
, GPIO_PINCFG29_NCESRC29_IOM1CE2 = 6
, GPIO_PINCFG29_NCESRC29_IOM1CE3 = 7
,
GPIO_PINCFG29_NCESRC29_IOM2CE0 = 8
, GPIO_PINCFG29_NCESRC29_IOM2CE1 = 9
, GPIO_PINCFG29_NCESRC29_IOM2CE2 = 10
, GPIO_PINCFG29_NCESRC29_IOM2CE3 = 11
,
GPIO_PINCFG29_NCESRC29_IOM3CE0 = 12
, GPIO_PINCFG29_NCESRC29_IOM3CE1 = 13
, GPIO_PINCFG29_NCESRC29_IOM3CE2 = 14
, GPIO_PINCFG29_NCESRC29_IOM3CE3 = 15
,
GPIO_PINCFG29_NCESRC29_IOM4CE0 = 16
, GPIO_PINCFG29_NCESRC29_IOM4CE1 = 17
, GPIO_PINCFG29_NCESRC29_IOM4CE2 = 18
, GPIO_PINCFG29_NCESRC29_IOM4CE3 = 19
,
GPIO_PINCFG29_NCESRC29_IOM5CE0 = 20
, GPIO_PINCFG29_NCESRC29_IOM5CE1 = 21
, GPIO_PINCFG29_NCESRC29_IOM5CE2 = 22
, GPIO_PINCFG29_NCESRC29_IOM5CE3 = 23
,
GPIO_PINCFG29_NCESRC29_IOM6CE0 = 24
, GPIO_PINCFG29_NCESRC29_IOM6CE1 = 25
, GPIO_PINCFG29_NCESRC29_IOM6CE2 = 26
, GPIO_PINCFG29_NCESRC29_IOM6CE3 = 27
,
GPIO_PINCFG29_NCESRC29_IOM7CE0 = 28
, GPIO_PINCFG29_NCESRC29_IOM7CE1 = 29
, GPIO_PINCFG29_NCESRC29_IOM7CE2 = 30
, GPIO_PINCFG29_NCESRC29_IOM7CE3 = 31
,
GPIO_PINCFG29_NCESRC29_MSPI0CEN0 = 32
, GPIO_PINCFG29_NCESRC29_MSPI0CEN1 = 33
, GPIO_PINCFG29_NCESRC29_MSPI1CEN0 = 34
, GPIO_PINCFG29_NCESRC29_MSPI1CEN1 = 35
,
GPIO_PINCFG29_NCESRC29_MSPI2CEN0 = 36
, GPIO_PINCFG29_NCESRC29_MSPI2CEN1 = 37
, GPIO_PINCFG29_NCESRC29_DC_DPI_DE = 38
, GPIO_PINCFG29_NCESRC29_DISP_CONT_CSX = 39
,
GPIO_PINCFG29_NCESRC29_DC_SPI_CS_N = 40
, GPIO_PINCFG29_NCESRC29_DC_QSPI_CS_N = 41
, GPIO_PINCFG29_NCESRC29_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG29_PULLCFG29_Enum {
GPIO_PINCFG29_PULLCFG29_DIS = 0
, GPIO_PINCFG29_PULLCFG29_PD50K = 1
, GPIO_PINCFG29_PULLCFG29_PU15K = 2
, GPIO_PINCFG29_PULLCFG29_PU6K = 3
,
GPIO_PINCFG29_PULLCFG29_PU12K = 4
, GPIO_PINCFG29_PULLCFG29_PU24K = 5
, GPIO_PINCFG29_PULLCFG29_PU50K = 6
, GPIO_PINCFG29_PULLCFG29_PU100K = 7
} |
| |
| enum | GPIO_PINCFG29_DS29_Enum { GPIO_PINCFG29_DS29_0P1X = 0
, GPIO_PINCFG29_DS29_0P5X = 1
} |
| |
| enum | GPIO_PINCFG29_OUTCFG29_Enum { GPIO_PINCFG29_OUTCFG29_DIS = 0
, GPIO_PINCFG29_OUTCFG29_PUSHPULL = 1
, GPIO_PINCFG29_OUTCFG29_OD = 2
, GPIO_PINCFG29_OUTCFG29_TS = 3
} |
| |
| enum | GPIO_PINCFG29_IRPTEN29_Enum { GPIO_PINCFG29_IRPTEN29_DIS = 0
, GPIO_PINCFG29_IRPTEN29_INTFALL = 1
, GPIO_PINCFG29_IRPTEN29_INTRISE = 2
, GPIO_PINCFG29_IRPTEN29_INTANY = 3
} |
| |
| enum | GPIO_PINCFG29_FNCSEL29_Enum {
GPIO_PINCFG29_FNCSEL29_TRIG0 = 0
, GPIO_PINCFG29_FNCSEL29_VCMPO = 1
, GPIO_PINCFG29_FNCSEL29_I2S0_DATA = 2
, GPIO_PINCFG29_FNCSEL29_GPIO = 3
,
GPIO_PINCFG29_FNCSEL29_UART1CTS = 4
, GPIO_PINCFG29_FNCSEL29_DSP_TRSTN = 5
, GPIO_PINCFG29_FNCSEL29_CT29 = 6
, GPIO_PINCFG29_FNCSEL29_NCE29 = 7
,
GPIO_PINCFG29_FNCSEL29_OBSBUS13 = 8
, GPIO_PINCFG29_FNCSEL29_I2S0_SDOUT = 9
, GPIO_PINCFG29_FNCSEL29_RESERVED10 = 10
, GPIO_PINCFG29_FNCSEL29_FPIO = 11
,
GPIO_PINCFG29_FNCSEL29_RESERVED12 = 12
, GPIO_PINCFG29_FNCSEL29_RESERVED13 = 13
, GPIO_PINCFG29_FNCSEL29_RESERVED14 = 14
, GPIO_PINCFG29_FNCSEL29_CMLE = 15
} |
| |
| enum | GPIO_PINCFG30_VDDPWRSWEN30_Enum { GPIO_PINCFG30_VDDPWRSWEN30_DIS = 0
, GPIO_PINCFG30_VDDPWRSWEN30_EN = 1
} |
| |
| enum | GPIO_PINCFG30_NCEPOL30_Enum { GPIO_PINCFG30_NCEPOL30_LOW = 0
, GPIO_PINCFG30_NCEPOL30_HIGH = 1
} |
| |
| enum | GPIO_PINCFG30_NCESRC30_Enum {
GPIO_PINCFG30_NCESRC30_IOM0CE0 = 0
, GPIO_PINCFG30_NCESRC30_IOM0CE1 = 1
, GPIO_PINCFG30_NCESRC30_IOM0CE2 = 2
, GPIO_PINCFG30_NCESRC30_IOM0CE3 = 3
,
GPIO_PINCFG30_NCESRC30_IOM1CE0 = 4
, GPIO_PINCFG30_NCESRC30_IOM1CE1 = 5
, GPIO_PINCFG30_NCESRC30_IOM1CE2 = 6
, GPIO_PINCFG30_NCESRC30_IOM1CE3 = 7
,
GPIO_PINCFG30_NCESRC30_IOM2CE0 = 8
, GPIO_PINCFG30_NCESRC30_IOM2CE1 = 9
, GPIO_PINCFG30_NCESRC30_IOM2CE2 = 10
, GPIO_PINCFG30_NCESRC30_IOM2CE3 = 11
,
GPIO_PINCFG30_NCESRC30_IOM3CE0 = 12
, GPIO_PINCFG30_NCESRC30_IOM3CE1 = 13
, GPIO_PINCFG30_NCESRC30_IOM3CE2 = 14
, GPIO_PINCFG30_NCESRC30_IOM3CE3 = 15
,
GPIO_PINCFG30_NCESRC30_IOM4CE0 = 16
, GPIO_PINCFG30_NCESRC30_IOM4CE1 = 17
, GPIO_PINCFG30_NCESRC30_IOM4CE2 = 18
, GPIO_PINCFG30_NCESRC30_IOM4CE3 = 19
,
GPIO_PINCFG30_NCESRC30_IOM5CE0 = 20
, GPIO_PINCFG30_NCESRC30_IOM5CE1 = 21
, GPIO_PINCFG30_NCESRC30_IOM5CE2 = 22
, GPIO_PINCFG30_NCESRC30_IOM5CE3 = 23
,
GPIO_PINCFG30_NCESRC30_IOM6CE0 = 24
, GPIO_PINCFG30_NCESRC30_IOM6CE1 = 25
, GPIO_PINCFG30_NCESRC30_IOM6CE2 = 26
, GPIO_PINCFG30_NCESRC30_IOM6CE3 = 27
,
GPIO_PINCFG30_NCESRC30_IOM7CE0 = 28
, GPIO_PINCFG30_NCESRC30_IOM7CE1 = 29
, GPIO_PINCFG30_NCESRC30_IOM7CE2 = 30
, GPIO_PINCFG30_NCESRC30_IOM7CE3 = 31
,
GPIO_PINCFG30_NCESRC30_MSPI0CEN0 = 32
, GPIO_PINCFG30_NCESRC30_MSPI0CEN1 = 33
, GPIO_PINCFG30_NCESRC30_MSPI1CEN0 = 34
, GPIO_PINCFG30_NCESRC30_MSPI1CEN1 = 35
,
GPIO_PINCFG30_NCESRC30_MSPI2CEN0 = 36
, GPIO_PINCFG30_NCESRC30_MSPI2CEN1 = 37
, GPIO_PINCFG30_NCESRC30_DC_DPI_DE = 38
, GPIO_PINCFG30_NCESRC30_DISP_CONT_CSX = 39
,
GPIO_PINCFG30_NCESRC30_DC_SPI_CS_N = 40
, GPIO_PINCFG30_NCESRC30_DC_QSPI_CS_N = 41
, GPIO_PINCFG30_NCESRC30_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG30_PULLCFG30_Enum {
GPIO_PINCFG30_PULLCFG30_DIS = 0
, GPIO_PINCFG30_PULLCFG30_PD50K = 1
, GPIO_PINCFG30_PULLCFG30_PU15K = 2
, GPIO_PINCFG30_PULLCFG30_PU6K = 3
,
GPIO_PINCFG30_PULLCFG30_PU12K = 4
, GPIO_PINCFG30_PULLCFG30_PU24K = 5
, GPIO_PINCFG30_PULLCFG30_PU50K = 6
, GPIO_PINCFG30_PULLCFG30_PU100K = 7
} |
| |
| enum | GPIO_PINCFG30_DS30_Enum { GPIO_PINCFG30_DS30_0P1X = 0
, GPIO_PINCFG30_DS30_0P5X = 1
} |
| |
| enum | GPIO_PINCFG30_OUTCFG30_Enum { GPIO_PINCFG30_OUTCFG30_DIS = 0
, GPIO_PINCFG30_OUTCFG30_PUSHPULL = 1
, GPIO_PINCFG30_OUTCFG30_OD = 2
, GPIO_PINCFG30_OUTCFG30_TS = 3
} |
| |
| enum | GPIO_PINCFG30_IRPTEN30_Enum { GPIO_PINCFG30_IRPTEN30_DIS = 0
, GPIO_PINCFG30_IRPTEN30_INTFALL = 1
, GPIO_PINCFG30_IRPTEN30_INTRISE = 2
, GPIO_PINCFG30_IRPTEN30_INTANY = 3
} |
| |
| enum | GPIO_PINCFG30_FNCSEL30_Enum {
GPIO_PINCFG30_FNCSEL30_TRIG1 = 0
, GPIO_PINCFG30_FNCSEL30_VCMPO = 1
, GPIO_PINCFG30_FNCSEL30_I2S0_WS = 2
, GPIO_PINCFG30_FNCSEL30_GPIO = 3
,
GPIO_PINCFG30_FNCSEL30_UART0TX = 4
, GPIO_PINCFG30_FNCSEL30_DSP_TDI = 5
, GPIO_PINCFG30_FNCSEL30_CT30 = 6
, GPIO_PINCFG30_FNCSEL30_NCE30 = 7
,
GPIO_PINCFG30_FNCSEL30_OBSBUS14 = 8
, GPIO_PINCFG30_FNCSEL30_RESERVED9 = 9
, GPIO_PINCFG30_FNCSEL30_RESERVED10 = 10
, GPIO_PINCFG30_FNCSEL30_FPIO = 11
,
GPIO_PINCFG30_FNCSEL30_RESERVED12 = 12
, GPIO_PINCFG30_FNCSEL30_RESERVED13 = 13
, GPIO_PINCFG30_FNCSEL30_RESERVED14 = 14
, GPIO_PINCFG30_FNCSEL30_SCANOUT8 = 15
} |
| |
| enum | GPIO_PINCFG31_NCEPOL31_Enum { GPIO_PINCFG31_NCEPOL31_LOW = 0
, GPIO_PINCFG31_NCEPOL31_HIGH = 1
} |
| |
| enum | GPIO_PINCFG31_NCESRC31_Enum {
GPIO_PINCFG31_NCESRC31_IOM0CE0 = 0
, GPIO_PINCFG31_NCESRC31_IOM0CE1 = 1
, GPIO_PINCFG31_NCESRC31_IOM0CE2 = 2
, GPIO_PINCFG31_NCESRC31_IOM0CE3 = 3
,
GPIO_PINCFG31_NCESRC31_IOM1CE0 = 4
, GPIO_PINCFG31_NCESRC31_IOM1CE1 = 5
, GPIO_PINCFG31_NCESRC31_IOM1CE2 = 6
, GPIO_PINCFG31_NCESRC31_IOM1CE3 = 7
,
GPIO_PINCFG31_NCESRC31_IOM2CE0 = 8
, GPIO_PINCFG31_NCESRC31_IOM2CE1 = 9
, GPIO_PINCFG31_NCESRC31_IOM2CE2 = 10
, GPIO_PINCFG31_NCESRC31_IOM2CE3 = 11
,
GPIO_PINCFG31_NCESRC31_IOM3CE0 = 12
, GPIO_PINCFG31_NCESRC31_IOM3CE1 = 13
, GPIO_PINCFG31_NCESRC31_IOM3CE2 = 14
, GPIO_PINCFG31_NCESRC31_IOM3CE3 = 15
,
GPIO_PINCFG31_NCESRC31_IOM4CE0 = 16
, GPIO_PINCFG31_NCESRC31_IOM4CE1 = 17
, GPIO_PINCFG31_NCESRC31_IOM4CE2 = 18
, GPIO_PINCFG31_NCESRC31_IOM4CE3 = 19
,
GPIO_PINCFG31_NCESRC31_IOM5CE0 = 20
, GPIO_PINCFG31_NCESRC31_IOM5CE1 = 21
, GPIO_PINCFG31_NCESRC31_IOM5CE2 = 22
, GPIO_PINCFG31_NCESRC31_IOM5CE3 = 23
,
GPIO_PINCFG31_NCESRC31_IOM6CE0 = 24
, GPIO_PINCFG31_NCESRC31_IOM6CE1 = 25
, GPIO_PINCFG31_NCESRC31_IOM6CE2 = 26
, GPIO_PINCFG31_NCESRC31_IOM6CE3 = 27
,
GPIO_PINCFG31_NCESRC31_IOM7CE0 = 28
, GPIO_PINCFG31_NCESRC31_IOM7CE1 = 29
, GPIO_PINCFG31_NCESRC31_IOM7CE2 = 30
, GPIO_PINCFG31_NCESRC31_IOM7CE3 = 31
,
GPIO_PINCFG31_NCESRC31_MSPI0CEN0 = 32
, GPIO_PINCFG31_NCESRC31_MSPI0CEN1 = 33
, GPIO_PINCFG31_NCESRC31_MSPI1CEN0 = 34
, GPIO_PINCFG31_NCESRC31_MSPI1CEN1 = 35
,
GPIO_PINCFG31_NCESRC31_MSPI2CEN0 = 36
, GPIO_PINCFG31_NCESRC31_MSPI2CEN1 = 37
, GPIO_PINCFG31_NCESRC31_DC_DPI_DE = 38
, GPIO_PINCFG31_NCESRC31_DISP_CONT_CSX = 39
,
GPIO_PINCFG31_NCESRC31_DC_SPI_CS_N = 40
, GPIO_PINCFG31_NCESRC31_DC_QSPI_CS_N = 41
, GPIO_PINCFG31_NCESRC31_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG31_PULLCFG31_Enum {
GPIO_PINCFG31_PULLCFG31_DIS = 0
, GPIO_PINCFG31_PULLCFG31_PD50K = 1
, GPIO_PINCFG31_PULLCFG31_PU15K = 2
, GPIO_PINCFG31_PULLCFG31_PU6K = 3
,
GPIO_PINCFG31_PULLCFG31_PU12K = 4
, GPIO_PINCFG31_PULLCFG31_PU24K = 5
, GPIO_PINCFG31_PULLCFG31_PU50K = 6
, GPIO_PINCFG31_PULLCFG31_PU100K = 7
} |
| |
| enum | GPIO_PINCFG31_DS31_Enum { GPIO_PINCFG31_DS31_0P1X = 0
, GPIO_PINCFG31_DS31_0P5X = 1
, GPIO_PINCFG31_DS31_0P75X = 2
, GPIO_PINCFG31_DS31_1P0X = 3
} |
| |
| enum | GPIO_PINCFG31_OUTCFG31_Enum { GPIO_PINCFG31_OUTCFG31_DIS = 0
, GPIO_PINCFG31_OUTCFG31_PUSHPULL = 1
, GPIO_PINCFG31_OUTCFG31_OD = 2
, GPIO_PINCFG31_OUTCFG31_TS = 3
} |
| |
| enum | GPIO_PINCFG31_IRPTEN31_Enum { GPIO_PINCFG31_IRPTEN31_DIS = 0
, GPIO_PINCFG31_IRPTEN31_INTFALL = 1
, GPIO_PINCFG31_IRPTEN31_INTRISE = 2
, GPIO_PINCFG31_IRPTEN31_INTANY = 3
} |
| |
| enum | GPIO_PINCFG31_FNCSEL31_Enum {
GPIO_PINCFG31_FNCSEL31_M3SCL = 0
, GPIO_PINCFG31_FNCSEL31_M3SCK = 1
, GPIO_PINCFG31_FNCSEL31_RESERVED2 = 2
, GPIO_PINCFG31_FNCSEL31_GPIO = 3
,
GPIO_PINCFG31_FNCSEL31_UART2TX = 4
, GPIO_PINCFG31_FNCSEL31_RESERVED5 = 5
, GPIO_PINCFG31_FNCSEL31_CT31 = 6
, GPIO_PINCFG31_FNCSEL31_NCE31 = 7
,
GPIO_PINCFG31_FNCSEL31_OBSBUS15 = 8
, GPIO_PINCFG31_FNCSEL31_VCMPO = 9
, GPIO_PINCFG31_FNCSEL31_RESERVED10 = 10
, GPIO_PINCFG31_FNCSEL31_FPIO = 11
,
GPIO_PINCFG31_FNCSEL31_RESERVED12 = 12
, GPIO_PINCFG31_FNCSEL31_RESERVED13 = 13
, GPIO_PINCFG31_FNCSEL31_RESERVED14 = 14
, GPIO_PINCFG31_FNCSEL31_SCANOUT9 = 15
} |
| |
| enum | GPIO_PINCFG32_NCEPOL32_Enum { GPIO_PINCFG32_NCEPOL32_LOW = 0
, GPIO_PINCFG32_NCEPOL32_HIGH = 1
} |
| |
| enum | GPIO_PINCFG32_NCESRC32_Enum {
GPIO_PINCFG32_NCESRC32_IOM0CE0 = 0
, GPIO_PINCFG32_NCESRC32_IOM0CE1 = 1
, GPIO_PINCFG32_NCESRC32_IOM0CE2 = 2
, GPIO_PINCFG32_NCESRC32_IOM0CE3 = 3
,
GPIO_PINCFG32_NCESRC32_IOM1CE0 = 4
, GPIO_PINCFG32_NCESRC32_IOM1CE1 = 5
, GPIO_PINCFG32_NCESRC32_IOM1CE2 = 6
, GPIO_PINCFG32_NCESRC32_IOM1CE3 = 7
,
GPIO_PINCFG32_NCESRC32_IOM2CE0 = 8
, GPIO_PINCFG32_NCESRC32_IOM2CE1 = 9
, GPIO_PINCFG32_NCESRC32_IOM2CE2 = 10
, GPIO_PINCFG32_NCESRC32_IOM2CE3 = 11
,
GPIO_PINCFG32_NCESRC32_IOM3CE0 = 12
, GPIO_PINCFG32_NCESRC32_IOM3CE1 = 13
, GPIO_PINCFG32_NCESRC32_IOM3CE2 = 14
, GPIO_PINCFG32_NCESRC32_IOM3CE3 = 15
,
GPIO_PINCFG32_NCESRC32_IOM4CE0 = 16
, GPIO_PINCFG32_NCESRC32_IOM4CE1 = 17
, GPIO_PINCFG32_NCESRC32_IOM4CE2 = 18
, GPIO_PINCFG32_NCESRC32_IOM4CE3 = 19
,
GPIO_PINCFG32_NCESRC32_IOM5CE0 = 20
, GPIO_PINCFG32_NCESRC32_IOM5CE1 = 21
, GPIO_PINCFG32_NCESRC32_IOM5CE2 = 22
, GPIO_PINCFG32_NCESRC32_IOM5CE3 = 23
,
GPIO_PINCFG32_NCESRC32_IOM6CE0 = 24
, GPIO_PINCFG32_NCESRC32_IOM6CE1 = 25
, GPIO_PINCFG32_NCESRC32_IOM6CE2 = 26
, GPIO_PINCFG32_NCESRC32_IOM6CE3 = 27
,
GPIO_PINCFG32_NCESRC32_IOM7CE0 = 28
, GPIO_PINCFG32_NCESRC32_IOM7CE1 = 29
, GPIO_PINCFG32_NCESRC32_IOM7CE2 = 30
, GPIO_PINCFG32_NCESRC32_IOM7CE3 = 31
,
GPIO_PINCFG32_NCESRC32_MSPI0CEN0 = 32
, GPIO_PINCFG32_NCESRC32_MSPI0CEN1 = 33
, GPIO_PINCFG32_NCESRC32_MSPI1CEN0 = 34
, GPIO_PINCFG32_NCESRC32_MSPI1CEN1 = 35
,
GPIO_PINCFG32_NCESRC32_MSPI2CEN0 = 36
, GPIO_PINCFG32_NCESRC32_MSPI2CEN1 = 37
, GPIO_PINCFG32_NCESRC32_DC_DPI_DE = 38
, GPIO_PINCFG32_NCESRC32_DISP_CONT_CSX = 39
,
GPIO_PINCFG32_NCESRC32_DC_SPI_CS_N = 40
, GPIO_PINCFG32_NCESRC32_DC_QSPI_CS_N = 41
, GPIO_PINCFG32_NCESRC32_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG32_PULLCFG32_Enum {
GPIO_PINCFG32_PULLCFG32_DIS = 0
, GPIO_PINCFG32_PULLCFG32_PD50K = 1
, GPIO_PINCFG32_PULLCFG32_PU15K = 2
, GPIO_PINCFG32_PULLCFG32_PU6K = 3
,
GPIO_PINCFG32_PULLCFG32_PU12K = 4
, GPIO_PINCFG32_PULLCFG32_PU24K = 5
, GPIO_PINCFG32_PULLCFG32_PU50K = 6
, GPIO_PINCFG32_PULLCFG32_PU100K = 7
} |
| |
| enum | GPIO_PINCFG32_DS32_Enum { GPIO_PINCFG32_DS32_0P1X = 0
, GPIO_PINCFG32_DS32_0P5X = 1
, GPIO_PINCFG32_DS32_0P75X = 2
, GPIO_PINCFG32_DS32_1P0X = 3
} |
| |
| enum | GPIO_PINCFG32_OUTCFG32_Enum { GPIO_PINCFG32_OUTCFG32_DIS = 0
, GPIO_PINCFG32_OUTCFG32_PUSHPULL = 1
, GPIO_PINCFG32_OUTCFG32_OD = 2
, GPIO_PINCFG32_OUTCFG32_TS = 3
} |
| |
| enum | GPIO_PINCFG32_IRPTEN32_Enum { GPIO_PINCFG32_IRPTEN32_DIS = 0
, GPIO_PINCFG32_IRPTEN32_INTFALL = 1
, GPIO_PINCFG32_IRPTEN32_INTRISE = 2
, GPIO_PINCFG32_IRPTEN32_INTANY = 3
} |
| |
| enum | GPIO_PINCFG32_FNCSEL32_Enum {
GPIO_PINCFG32_FNCSEL32_M3SDAWIR3 = 0
, GPIO_PINCFG32_FNCSEL32_M3MOSI = 1
, GPIO_PINCFG32_FNCSEL32_RESERVED2 = 2
, GPIO_PINCFG32_FNCSEL32_GPIO = 3
,
GPIO_PINCFG32_FNCSEL32_UART0RX = 4
, GPIO_PINCFG32_FNCSEL32_RESERVED5 = 5
, GPIO_PINCFG32_FNCSEL32_CT32 = 6
, GPIO_PINCFG32_FNCSEL32_NCE32 = 7
,
GPIO_PINCFG32_FNCSEL32_OBSBUS0 = 8
, GPIO_PINCFG32_FNCSEL32_RESERVED9 = 9
, GPIO_PINCFG32_FNCSEL32_RESERVED10 = 10
, GPIO_PINCFG32_FNCSEL32_FPIO = 11
,
GPIO_PINCFG32_FNCSEL32_RESERVED12 = 12
, GPIO_PINCFG32_FNCSEL32_RESERVED13 = 13
, GPIO_PINCFG32_FNCSEL32_RESERVED14 = 14
, GPIO_PINCFG32_FNCSEL32_LPG_ENABLE = 15
} |
| |
| enum | GPIO_PINCFG33_NCEPOL33_Enum { GPIO_PINCFG33_NCEPOL33_LOW = 0
, GPIO_PINCFG33_NCEPOL33_HIGH = 1
} |
| |
| enum | GPIO_PINCFG33_NCESRC33_Enum {
GPIO_PINCFG33_NCESRC33_IOM0CE0 = 0
, GPIO_PINCFG33_NCESRC33_IOM0CE1 = 1
, GPIO_PINCFG33_NCESRC33_IOM0CE2 = 2
, GPIO_PINCFG33_NCESRC33_IOM0CE3 = 3
,
GPIO_PINCFG33_NCESRC33_IOM1CE0 = 4
, GPIO_PINCFG33_NCESRC33_IOM1CE1 = 5
, GPIO_PINCFG33_NCESRC33_IOM1CE2 = 6
, GPIO_PINCFG33_NCESRC33_IOM1CE3 = 7
,
GPIO_PINCFG33_NCESRC33_IOM2CE0 = 8
, GPIO_PINCFG33_NCESRC33_IOM2CE1 = 9
, GPIO_PINCFG33_NCESRC33_IOM2CE2 = 10
, GPIO_PINCFG33_NCESRC33_IOM2CE3 = 11
,
GPIO_PINCFG33_NCESRC33_IOM3CE0 = 12
, GPIO_PINCFG33_NCESRC33_IOM3CE1 = 13
, GPIO_PINCFG33_NCESRC33_IOM3CE2 = 14
, GPIO_PINCFG33_NCESRC33_IOM3CE3 = 15
,
GPIO_PINCFG33_NCESRC33_IOM4CE0 = 16
, GPIO_PINCFG33_NCESRC33_IOM4CE1 = 17
, GPIO_PINCFG33_NCESRC33_IOM4CE2 = 18
, GPIO_PINCFG33_NCESRC33_IOM4CE3 = 19
,
GPIO_PINCFG33_NCESRC33_IOM5CE0 = 20
, GPIO_PINCFG33_NCESRC33_IOM5CE1 = 21
, GPIO_PINCFG33_NCESRC33_IOM5CE2 = 22
, GPIO_PINCFG33_NCESRC33_IOM5CE3 = 23
,
GPIO_PINCFG33_NCESRC33_IOM6CE0 = 24
, GPIO_PINCFG33_NCESRC33_IOM6CE1 = 25
, GPIO_PINCFG33_NCESRC33_IOM6CE2 = 26
, GPIO_PINCFG33_NCESRC33_IOM6CE3 = 27
,
GPIO_PINCFG33_NCESRC33_IOM7CE0 = 28
, GPIO_PINCFG33_NCESRC33_IOM7CE1 = 29
, GPIO_PINCFG33_NCESRC33_IOM7CE2 = 30
, GPIO_PINCFG33_NCESRC33_IOM7CE3 = 31
,
GPIO_PINCFG33_NCESRC33_MSPI0CEN0 = 32
, GPIO_PINCFG33_NCESRC33_MSPI0CEN1 = 33
, GPIO_PINCFG33_NCESRC33_MSPI1CEN0 = 34
, GPIO_PINCFG33_NCESRC33_MSPI1CEN1 = 35
,
GPIO_PINCFG33_NCESRC33_MSPI2CEN0 = 36
, GPIO_PINCFG33_NCESRC33_MSPI2CEN1 = 37
, GPIO_PINCFG33_NCESRC33_DC_DPI_DE = 38
, GPIO_PINCFG33_NCESRC33_DISP_CONT_CSX = 39
,
GPIO_PINCFG33_NCESRC33_DC_SPI_CS_N = 40
, GPIO_PINCFG33_NCESRC33_DC_QSPI_CS_N = 41
, GPIO_PINCFG33_NCESRC33_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG33_PULLCFG33_Enum {
GPIO_PINCFG33_PULLCFG33_DIS = 0
, GPIO_PINCFG33_PULLCFG33_PD50K = 1
, GPIO_PINCFG33_PULLCFG33_PU15K = 2
, GPIO_PINCFG33_PULLCFG33_PU6K = 3
,
GPIO_PINCFG33_PULLCFG33_PU12K = 4
, GPIO_PINCFG33_PULLCFG33_PU24K = 5
, GPIO_PINCFG33_PULLCFG33_PU50K = 6
, GPIO_PINCFG33_PULLCFG33_PU100K = 7
} |
| |
| enum | GPIO_PINCFG33_DS33_Enum { GPIO_PINCFG33_DS33_0P1X = 0
, GPIO_PINCFG33_DS33_0P5X = 1
, GPIO_PINCFG33_DS33_0P75X = 2
, GPIO_PINCFG33_DS33_1P0X = 3
} |
| |
| enum | GPIO_PINCFG33_OUTCFG33_Enum { GPIO_PINCFG33_OUTCFG33_DIS = 0
, GPIO_PINCFG33_OUTCFG33_PUSHPULL = 1
, GPIO_PINCFG33_OUTCFG33_OD = 2
, GPIO_PINCFG33_OUTCFG33_TS = 3
} |
| |
| enum | GPIO_PINCFG33_IRPTEN33_Enum { GPIO_PINCFG33_IRPTEN33_DIS = 0
, GPIO_PINCFG33_IRPTEN33_INTFALL = 1
, GPIO_PINCFG33_IRPTEN33_INTRISE = 2
, GPIO_PINCFG33_IRPTEN33_INTANY = 3
} |
| |
| enum | GPIO_PINCFG33_FNCSEL33_Enum {
GPIO_PINCFG33_FNCSEL33_M3MISO = 0
, GPIO_PINCFG33_FNCSEL33_CLKOUT = 1
, GPIO_PINCFG33_FNCSEL33_RESERVED2 = 2
, GPIO_PINCFG33_FNCSEL33_GPIO = 3
,
GPIO_PINCFG33_FNCSEL33_UART2RX = 4
, GPIO_PINCFG33_FNCSEL33_RESERVED5 = 5
, GPIO_PINCFG33_FNCSEL33_CT33 = 6
, GPIO_PINCFG33_FNCSEL33_NCE33 = 7
,
GPIO_PINCFG33_FNCSEL33_OBSBUS1 = 8
, GPIO_PINCFG33_FNCSEL33_DISP_TE = 9
, GPIO_PINCFG33_FNCSEL33_RESERVED10 = 10
, GPIO_PINCFG33_FNCSEL33_FPIO = 11
,
GPIO_PINCFG33_FNCSEL33_RESERVED12 = 12
, GPIO_PINCFG33_FNCSEL33_RESERVED13 = 13
, GPIO_PINCFG33_FNCSEL33_RESERVED14 = 14
, GPIO_PINCFG33_FNCSEL33_LPG_LOAD = 15
} |
| |
| enum | GPIO_PINCFG34_NCEPOL34_Enum { GPIO_PINCFG34_NCEPOL34_LOW = 0
, GPIO_PINCFG34_NCEPOL34_HIGH = 1
} |
| |
| enum | GPIO_PINCFG34_NCESRC34_Enum {
GPIO_PINCFG34_NCESRC34_IOM0CE0 = 0
, GPIO_PINCFG34_NCESRC34_IOM0CE1 = 1
, GPIO_PINCFG34_NCESRC34_IOM0CE2 = 2
, GPIO_PINCFG34_NCESRC34_IOM0CE3 = 3
,
GPIO_PINCFG34_NCESRC34_IOM1CE0 = 4
, GPIO_PINCFG34_NCESRC34_IOM1CE1 = 5
, GPIO_PINCFG34_NCESRC34_IOM1CE2 = 6
, GPIO_PINCFG34_NCESRC34_IOM1CE3 = 7
,
GPIO_PINCFG34_NCESRC34_IOM2CE0 = 8
, GPIO_PINCFG34_NCESRC34_IOM2CE1 = 9
, GPIO_PINCFG34_NCESRC34_IOM2CE2 = 10
, GPIO_PINCFG34_NCESRC34_IOM2CE3 = 11
,
GPIO_PINCFG34_NCESRC34_IOM3CE0 = 12
, GPIO_PINCFG34_NCESRC34_IOM3CE1 = 13
, GPIO_PINCFG34_NCESRC34_IOM3CE2 = 14
, GPIO_PINCFG34_NCESRC34_IOM3CE3 = 15
,
GPIO_PINCFG34_NCESRC34_IOM4CE0 = 16
, GPIO_PINCFG34_NCESRC34_IOM4CE1 = 17
, GPIO_PINCFG34_NCESRC34_IOM4CE2 = 18
, GPIO_PINCFG34_NCESRC34_IOM4CE3 = 19
,
GPIO_PINCFG34_NCESRC34_IOM5CE0 = 20
, GPIO_PINCFG34_NCESRC34_IOM5CE1 = 21
, GPIO_PINCFG34_NCESRC34_IOM5CE2 = 22
, GPIO_PINCFG34_NCESRC34_IOM5CE3 = 23
,
GPIO_PINCFG34_NCESRC34_IOM6CE0 = 24
, GPIO_PINCFG34_NCESRC34_IOM6CE1 = 25
, GPIO_PINCFG34_NCESRC34_IOM6CE2 = 26
, GPIO_PINCFG34_NCESRC34_IOM6CE3 = 27
,
GPIO_PINCFG34_NCESRC34_IOM7CE0 = 28
, GPIO_PINCFG34_NCESRC34_IOM7CE1 = 29
, GPIO_PINCFG34_NCESRC34_IOM7CE2 = 30
, GPIO_PINCFG34_NCESRC34_IOM7CE3 = 31
,
GPIO_PINCFG34_NCESRC34_MSPI0CEN0 = 32
, GPIO_PINCFG34_NCESRC34_MSPI0CEN1 = 33
, GPIO_PINCFG34_NCESRC34_MSPI1CEN0 = 34
, GPIO_PINCFG34_NCESRC34_MSPI1CEN1 = 35
,
GPIO_PINCFG34_NCESRC34_MSPI2CEN0 = 36
, GPIO_PINCFG34_NCESRC34_MSPI2CEN1 = 37
, GPIO_PINCFG34_NCESRC34_DC_DPI_DE = 38
, GPIO_PINCFG34_NCESRC34_DISP_CONT_CSX = 39
,
GPIO_PINCFG34_NCESRC34_DC_SPI_CS_N = 40
, GPIO_PINCFG34_NCESRC34_DC_QSPI_CS_N = 41
, GPIO_PINCFG34_NCESRC34_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG34_PULLCFG34_Enum {
GPIO_PINCFG34_PULLCFG34_DIS = 0
, GPIO_PINCFG34_PULLCFG34_PD50K = 1
, GPIO_PINCFG34_PULLCFG34_PU15K = 2
, GPIO_PINCFG34_PULLCFG34_PU6K = 3
,
GPIO_PINCFG34_PULLCFG34_PU12K = 4
, GPIO_PINCFG34_PULLCFG34_PU24K = 5
, GPIO_PINCFG34_PULLCFG34_PU50K = 6
, GPIO_PINCFG34_PULLCFG34_PU100K = 7
} |
| |
| enum | GPIO_PINCFG34_DS34_Enum { GPIO_PINCFG34_DS34_0P1X = 0
, GPIO_PINCFG34_DS34_0P5X = 1
, GPIO_PINCFG34_DS34_0P75X = 2
, GPIO_PINCFG34_DS34_1P0X = 3
} |
| |
| enum | GPIO_PINCFG34_OUTCFG34_Enum { GPIO_PINCFG34_OUTCFG34_DIS = 0
, GPIO_PINCFG34_OUTCFG34_PUSHPULL = 1
, GPIO_PINCFG34_OUTCFG34_OD = 2
, GPIO_PINCFG34_OUTCFG34_TS = 3
} |
| |
| enum | GPIO_PINCFG34_IRPTEN34_Enum { GPIO_PINCFG34_IRPTEN34_DIS = 0
, GPIO_PINCFG34_IRPTEN34_INTFALL = 1
, GPIO_PINCFG34_IRPTEN34_INTRISE = 2
, GPIO_PINCFG34_IRPTEN34_INTANY = 3
} |
| |
| enum | GPIO_PINCFG34_FNCSEL34_Enum {
GPIO_PINCFG34_FNCSEL34_M4SCL = 0
, GPIO_PINCFG34_FNCSEL34_M4SCK = 1
, GPIO_PINCFG34_FNCSEL34_SWO = 2
, GPIO_PINCFG34_FNCSEL34_GPIO = 3
,
GPIO_PINCFG34_FNCSEL34_UART0TX = 4
, GPIO_PINCFG34_FNCSEL34_RESERVED5 = 5
, GPIO_PINCFG34_FNCSEL34_CT34 = 6
, GPIO_PINCFG34_FNCSEL34_NCE34 = 7
,
GPIO_PINCFG34_FNCSEL34_OBSBUS2 = 8
, GPIO_PINCFG34_FNCSEL34_VCMPO = 9
, GPIO_PINCFG34_FNCSEL34_RESERVED10 = 10
, GPIO_PINCFG34_FNCSEL34_FPIO = 11
,
GPIO_PINCFG34_FNCSEL34_RESERVED12 = 12
, GPIO_PINCFG34_FNCSEL34_RESERVED13 = 13
, GPIO_PINCFG34_FNCSEL34_RESERVED14 = 14
, GPIO_PINCFG34_FNCSEL34_RESERVED15 = 15
} |
| |
| enum | GPIO_PINCFG35_NCEPOL35_Enum { GPIO_PINCFG35_NCEPOL35_LOW = 0
, GPIO_PINCFG35_NCEPOL35_HIGH = 1
} |
| |
| enum | GPIO_PINCFG35_NCESRC35_Enum {
GPIO_PINCFG35_NCESRC35_IOM0CE0 = 0
, GPIO_PINCFG35_NCESRC35_IOM0CE1 = 1
, GPIO_PINCFG35_NCESRC35_IOM0CE2 = 2
, GPIO_PINCFG35_NCESRC35_IOM0CE3 = 3
,
GPIO_PINCFG35_NCESRC35_IOM1CE0 = 4
, GPIO_PINCFG35_NCESRC35_IOM1CE1 = 5
, GPIO_PINCFG35_NCESRC35_IOM1CE2 = 6
, GPIO_PINCFG35_NCESRC35_IOM1CE3 = 7
,
GPIO_PINCFG35_NCESRC35_IOM2CE0 = 8
, GPIO_PINCFG35_NCESRC35_IOM2CE1 = 9
, GPIO_PINCFG35_NCESRC35_IOM2CE2 = 10
, GPIO_PINCFG35_NCESRC35_IOM2CE3 = 11
,
GPIO_PINCFG35_NCESRC35_IOM3CE0 = 12
, GPIO_PINCFG35_NCESRC35_IOM3CE1 = 13
, GPIO_PINCFG35_NCESRC35_IOM3CE2 = 14
, GPIO_PINCFG35_NCESRC35_IOM3CE3 = 15
,
GPIO_PINCFG35_NCESRC35_IOM4CE0 = 16
, GPIO_PINCFG35_NCESRC35_IOM4CE1 = 17
, GPIO_PINCFG35_NCESRC35_IOM4CE2 = 18
, GPIO_PINCFG35_NCESRC35_IOM4CE3 = 19
,
GPIO_PINCFG35_NCESRC35_IOM5CE0 = 20
, GPIO_PINCFG35_NCESRC35_IOM5CE1 = 21
, GPIO_PINCFG35_NCESRC35_IOM5CE2 = 22
, GPIO_PINCFG35_NCESRC35_IOM5CE3 = 23
,
GPIO_PINCFG35_NCESRC35_IOM6CE0 = 24
, GPIO_PINCFG35_NCESRC35_IOM6CE1 = 25
, GPIO_PINCFG35_NCESRC35_IOM6CE2 = 26
, GPIO_PINCFG35_NCESRC35_IOM6CE3 = 27
,
GPIO_PINCFG35_NCESRC35_IOM7CE0 = 28
, GPIO_PINCFG35_NCESRC35_IOM7CE1 = 29
, GPIO_PINCFG35_NCESRC35_IOM7CE2 = 30
, GPIO_PINCFG35_NCESRC35_IOM7CE3 = 31
,
GPIO_PINCFG35_NCESRC35_MSPI0CEN0 = 32
, GPIO_PINCFG35_NCESRC35_MSPI0CEN1 = 33
, GPIO_PINCFG35_NCESRC35_MSPI1CEN0 = 34
, GPIO_PINCFG35_NCESRC35_MSPI1CEN1 = 35
,
GPIO_PINCFG35_NCESRC35_MSPI2CEN0 = 36
, GPIO_PINCFG35_NCESRC35_MSPI2CEN1 = 37
, GPIO_PINCFG35_NCESRC35_DC_DPI_DE = 38
, GPIO_PINCFG35_NCESRC35_DISP_CONT_CSX = 39
,
GPIO_PINCFG35_NCESRC35_DC_SPI_CS_N = 40
, GPIO_PINCFG35_NCESRC35_DC_QSPI_CS_N = 41
, GPIO_PINCFG35_NCESRC35_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG35_PULLCFG35_Enum {
GPIO_PINCFG35_PULLCFG35_DIS = 0
, GPIO_PINCFG35_PULLCFG35_PD50K = 1
, GPIO_PINCFG35_PULLCFG35_PU15K = 2
, GPIO_PINCFG35_PULLCFG35_PU6K = 3
,
GPIO_PINCFG35_PULLCFG35_PU12K = 4
, GPIO_PINCFG35_PULLCFG35_PU24K = 5
, GPIO_PINCFG35_PULLCFG35_PU50K = 6
, GPIO_PINCFG35_PULLCFG35_PU100K = 7
} |
| |
| enum | GPIO_PINCFG35_DS35_Enum { GPIO_PINCFG35_DS35_0P1X = 0
, GPIO_PINCFG35_DS35_0P5X = 1
, GPIO_PINCFG35_DS35_0P75X = 2
, GPIO_PINCFG35_DS35_1P0X = 3
} |
| |
| enum | GPIO_PINCFG35_OUTCFG35_Enum { GPIO_PINCFG35_OUTCFG35_DIS = 0
, GPIO_PINCFG35_OUTCFG35_PUSHPULL = 1
, GPIO_PINCFG35_OUTCFG35_OD = 2
, GPIO_PINCFG35_OUTCFG35_TS = 3
} |
| |
| enum | GPIO_PINCFG35_IRPTEN35_Enum { GPIO_PINCFG35_IRPTEN35_DIS = 0
, GPIO_PINCFG35_IRPTEN35_INTFALL = 1
, GPIO_PINCFG35_IRPTEN35_INTRISE = 2
, GPIO_PINCFG35_IRPTEN35_INTANY = 3
} |
| |
| enum | GPIO_PINCFG35_FNCSEL35_Enum {
GPIO_PINCFG35_FNCSEL35_M4SDAWIR3 = 0
, GPIO_PINCFG35_FNCSEL35_M4MOSI = 1
, GPIO_PINCFG35_FNCSEL35_SWO = 2
, GPIO_PINCFG35_FNCSEL35_GPIO = 3
,
GPIO_PINCFG35_FNCSEL35_UART2TX = 4
, GPIO_PINCFG35_FNCSEL35_UART3TX = 5
, GPIO_PINCFG35_FNCSEL35_CT35 = 6
, GPIO_PINCFG35_FNCSEL35_NCE35 = 7
,
GPIO_PINCFG35_FNCSEL35_OBSBUS3 = 8
, GPIO_PINCFG35_FNCSEL35_VCMPO = 9
, GPIO_PINCFG35_FNCSEL35_RESERVED10 = 10
, GPIO_PINCFG35_FNCSEL35_FPIO = 11
,
GPIO_PINCFG35_FNCSEL35_RESERVED12 = 12
, GPIO_PINCFG35_FNCSEL35_RESERVED13 = 13
, GPIO_PINCFG35_FNCSEL35_RESERVED14 = 14
, GPIO_PINCFG35_FNCSEL35_RESERVED15 = 15
} |
| |
| enum | GPIO_PINCFG36_NCEPOL36_Enum { GPIO_PINCFG36_NCEPOL36_LOW = 0
, GPIO_PINCFG36_NCEPOL36_HIGH = 1
} |
| |
| enum | GPIO_PINCFG36_NCESRC36_Enum {
GPIO_PINCFG36_NCESRC36_IOM0CE0 = 0
, GPIO_PINCFG36_NCESRC36_IOM0CE1 = 1
, GPIO_PINCFG36_NCESRC36_IOM0CE2 = 2
, GPIO_PINCFG36_NCESRC36_IOM0CE3 = 3
,
GPIO_PINCFG36_NCESRC36_IOM1CE0 = 4
, GPIO_PINCFG36_NCESRC36_IOM1CE1 = 5
, GPIO_PINCFG36_NCESRC36_IOM1CE2 = 6
, GPIO_PINCFG36_NCESRC36_IOM1CE3 = 7
,
GPIO_PINCFG36_NCESRC36_IOM2CE0 = 8
, GPIO_PINCFG36_NCESRC36_IOM2CE1 = 9
, GPIO_PINCFG36_NCESRC36_IOM2CE2 = 10
, GPIO_PINCFG36_NCESRC36_IOM2CE3 = 11
,
GPIO_PINCFG36_NCESRC36_IOM3CE0 = 12
, GPIO_PINCFG36_NCESRC36_IOM3CE1 = 13
, GPIO_PINCFG36_NCESRC36_IOM3CE2 = 14
, GPIO_PINCFG36_NCESRC36_IOM3CE3 = 15
,
GPIO_PINCFG36_NCESRC36_IOM4CE0 = 16
, GPIO_PINCFG36_NCESRC36_IOM4CE1 = 17
, GPIO_PINCFG36_NCESRC36_IOM4CE2 = 18
, GPIO_PINCFG36_NCESRC36_IOM4CE3 = 19
,
GPIO_PINCFG36_NCESRC36_IOM5CE0 = 20
, GPIO_PINCFG36_NCESRC36_IOM5CE1 = 21
, GPIO_PINCFG36_NCESRC36_IOM5CE2 = 22
, GPIO_PINCFG36_NCESRC36_IOM5CE3 = 23
,
GPIO_PINCFG36_NCESRC36_IOM6CE0 = 24
, GPIO_PINCFG36_NCESRC36_IOM6CE1 = 25
, GPIO_PINCFG36_NCESRC36_IOM6CE2 = 26
, GPIO_PINCFG36_NCESRC36_IOM6CE3 = 27
,
GPIO_PINCFG36_NCESRC36_IOM7CE0 = 28
, GPIO_PINCFG36_NCESRC36_IOM7CE1 = 29
, GPIO_PINCFG36_NCESRC36_IOM7CE2 = 30
, GPIO_PINCFG36_NCESRC36_IOM7CE3 = 31
,
GPIO_PINCFG36_NCESRC36_MSPI0CEN0 = 32
, GPIO_PINCFG36_NCESRC36_MSPI0CEN1 = 33
, GPIO_PINCFG36_NCESRC36_MSPI1CEN0 = 34
, GPIO_PINCFG36_NCESRC36_MSPI1CEN1 = 35
,
GPIO_PINCFG36_NCESRC36_MSPI2CEN0 = 36
, GPIO_PINCFG36_NCESRC36_MSPI2CEN1 = 37
, GPIO_PINCFG36_NCESRC36_DC_DPI_DE = 38
, GPIO_PINCFG36_NCESRC36_DISP_CONT_CSX = 39
,
GPIO_PINCFG36_NCESRC36_DC_SPI_CS_N = 40
, GPIO_PINCFG36_NCESRC36_DC_QSPI_CS_N = 41
, GPIO_PINCFG36_NCESRC36_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG36_PULLCFG36_Enum {
GPIO_PINCFG36_PULLCFG36_DIS = 0
, GPIO_PINCFG36_PULLCFG36_PD50K = 1
, GPIO_PINCFG36_PULLCFG36_PU15K = 2
, GPIO_PINCFG36_PULLCFG36_PU6K = 3
,
GPIO_PINCFG36_PULLCFG36_PU12K = 4
, GPIO_PINCFG36_PULLCFG36_PU24K = 5
, GPIO_PINCFG36_PULLCFG36_PU50K = 6
, GPIO_PINCFG36_PULLCFG36_PU100K = 7
} |
| |
| enum | GPIO_PINCFG36_DS36_Enum { GPIO_PINCFG36_DS36_0P1X = 0
, GPIO_PINCFG36_DS36_0P5X = 1
, GPIO_PINCFG36_DS36_0P75X = 2
, GPIO_PINCFG36_DS36_1P0X = 3
} |
| |
| enum | GPIO_PINCFG36_OUTCFG36_Enum { GPIO_PINCFG36_OUTCFG36_DIS = 0
, GPIO_PINCFG36_OUTCFG36_PUSHPULL = 1
, GPIO_PINCFG36_OUTCFG36_OD = 2
, GPIO_PINCFG36_OUTCFG36_TS = 3
} |
| |
| enum | GPIO_PINCFG36_IRPTEN36_Enum { GPIO_PINCFG36_IRPTEN36_DIS = 0
, GPIO_PINCFG36_IRPTEN36_INTFALL = 1
, GPIO_PINCFG36_IRPTEN36_INTRISE = 2
, GPIO_PINCFG36_IRPTEN36_INTANY = 3
} |
| |
| enum | GPIO_PINCFG36_FNCSEL36_Enum {
GPIO_PINCFG36_FNCSEL36_M4MISO = 0
, GPIO_PINCFG36_FNCSEL36_TRIG0 = 1
, GPIO_PINCFG36_FNCSEL36_SWO = 2
, GPIO_PINCFG36_FNCSEL36_GPIO = 3
,
GPIO_PINCFG36_FNCSEL36_UART0RX = 4
, GPIO_PINCFG36_FNCSEL36_UART1RX = 5
, GPIO_PINCFG36_FNCSEL36_CT36 = 6
, GPIO_PINCFG36_FNCSEL36_NCE36 = 7
,
GPIO_PINCFG36_FNCSEL36_OBSBUS4 = 8
, GPIO_PINCFG36_FNCSEL36_RESERVED9 = 9
, GPIO_PINCFG36_FNCSEL36_RESERVED10 = 10
, GPIO_PINCFG36_FNCSEL36_FPIO = 11
,
GPIO_PINCFG36_FNCSEL36_RESERVED12 = 12
, GPIO_PINCFG36_FNCSEL36_RESERVED13 = 13
, GPIO_PINCFG36_FNCSEL36_RESERVED14 = 14
, GPIO_PINCFG36_FNCSEL36_RESERVED15 = 15
} |
| |
| enum | GPIO_PINCFG37_NCEPOL37_Enum { GPIO_PINCFG37_NCEPOL37_LOW = 0
, GPIO_PINCFG37_NCEPOL37_HIGH = 1
} |
| |
| enum | GPIO_PINCFG37_NCESRC37_Enum {
GPIO_PINCFG37_NCESRC37_IOM0CE0 = 0
, GPIO_PINCFG37_NCESRC37_IOM0CE1 = 1
, GPIO_PINCFG37_NCESRC37_IOM0CE2 = 2
, GPIO_PINCFG37_NCESRC37_IOM0CE3 = 3
,
GPIO_PINCFG37_NCESRC37_IOM1CE0 = 4
, GPIO_PINCFG37_NCESRC37_IOM1CE1 = 5
, GPIO_PINCFG37_NCESRC37_IOM1CE2 = 6
, GPIO_PINCFG37_NCESRC37_IOM1CE3 = 7
,
GPIO_PINCFG37_NCESRC37_IOM2CE0 = 8
, GPIO_PINCFG37_NCESRC37_IOM2CE1 = 9
, GPIO_PINCFG37_NCESRC37_IOM2CE2 = 10
, GPIO_PINCFG37_NCESRC37_IOM2CE3 = 11
,
GPIO_PINCFG37_NCESRC37_IOM3CE0 = 12
, GPIO_PINCFG37_NCESRC37_IOM3CE1 = 13
, GPIO_PINCFG37_NCESRC37_IOM3CE2 = 14
, GPIO_PINCFG37_NCESRC37_IOM3CE3 = 15
,
GPIO_PINCFG37_NCESRC37_IOM4CE0 = 16
, GPIO_PINCFG37_NCESRC37_IOM4CE1 = 17
, GPIO_PINCFG37_NCESRC37_IOM4CE2 = 18
, GPIO_PINCFG37_NCESRC37_IOM4CE3 = 19
,
GPIO_PINCFG37_NCESRC37_IOM5CE0 = 20
, GPIO_PINCFG37_NCESRC37_IOM5CE1 = 21
, GPIO_PINCFG37_NCESRC37_IOM5CE2 = 22
, GPIO_PINCFG37_NCESRC37_IOM5CE3 = 23
,
GPIO_PINCFG37_NCESRC37_IOM6CE0 = 24
, GPIO_PINCFG37_NCESRC37_IOM6CE1 = 25
, GPIO_PINCFG37_NCESRC37_IOM6CE2 = 26
, GPIO_PINCFG37_NCESRC37_IOM6CE3 = 27
,
GPIO_PINCFG37_NCESRC37_IOM7CE0 = 28
, GPIO_PINCFG37_NCESRC37_IOM7CE1 = 29
, GPIO_PINCFG37_NCESRC37_IOM7CE2 = 30
, GPIO_PINCFG37_NCESRC37_IOM7CE3 = 31
,
GPIO_PINCFG37_NCESRC37_MSPI0CEN0 = 32
, GPIO_PINCFG37_NCESRC37_MSPI0CEN1 = 33
, GPIO_PINCFG37_NCESRC37_MSPI1CEN0 = 34
, GPIO_PINCFG37_NCESRC37_MSPI1CEN1 = 35
,
GPIO_PINCFG37_NCESRC37_MSPI2CEN0 = 36
, GPIO_PINCFG37_NCESRC37_MSPI2CEN1 = 37
, GPIO_PINCFG37_NCESRC37_DC_DPI_DE = 38
, GPIO_PINCFG37_NCESRC37_DISP_CONT_CSX = 39
,
GPIO_PINCFG37_NCESRC37_DC_SPI_CS_N = 40
, GPIO_PINCFG37_NCESRC37_DC_QSPI_CS_N = 41
, GPIO_PINCFG37_NCESRC37_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG37_PULLCFG37_Enum {
GPIO_PINCFG37_PULLCFG37_DIS = 0
, GPIO_PINCFG37_PULLCFG37_PD50K = 1
, GPIO_PINCFG37_PULLCFG37_PU15K = 2
, GPIO_PINCFG37_PULLCFG37_PU6K = 3
,
GPIO_PINCFG37_PULLCFG37_PU12K = 4
, GPIO_PINCFG37_PULLCFG37_PU24K = 5
, GPIO_PINCFG37_PULLCFG37_PU50K = 6
, GPIO_PINCFG37_PULLCFG37_PU100K = 7
} |
| |
| enum | GPIO_PINCFG37_DS37_Enum { GPIO_PINCFG37_DS37_0P1X = 0
, GPIO_PINCFG37_DS37_0P5X = 1
, GPIO_PINCFG37_DS37_0P75X = 2
, GPIO_PINCFG37_DS37_1P0X = 3
} |
| |
| enum | GPIO_PINCFG37_OUTCFG37_Enum { GPIO_PINCFG37_OUTCFG37_DIS = 0
, GPIO_PINCFG37_OUTCFG37_PUSHPULL = 1
, GPIO_PINCFG37_OUTCFG37_OD = 2
, GPIO_PINCFG37_OUTCFG37_TS = 3
} |
| |
| enum | GPIO_PINCFG37_IRPTEN37_Enum { GPIO_PINCFG37_IRPTEN37_DIS = 0
, GPIO_PINCFG37_IRPTEN37_INTFALL = 1
, GPIO_PINCFG37_IRPTEN37_INTRISE = 2
, GPIO_PINCFG37_IRPTEN37_INTANY = 3
} |
| |
| enum | GPIO_PINCFG37_FNCSEL37_Enum {
GPIO_PINCFG37_FNCSEL37_MSPI1_0 = 0
, GPIO_PINCFG37_FNCSEL37_TRIG1 = 1
, GPIO_PINCFG37_FNCSEL37_32KHzXT = 2
, GPIO_PINCFG37_FNCSEL37_GPIO = 3
,
GPIO_PINCFG37_FNCSEL37_UART2RX = 4
, GPIO_PINCFG37_FNCSEL37_DISP_D15 = 5
, GPIO_PINCFG37_FNCSEL37_CT37 = 6
, GPIO_PINCFG37_FNCSEL37_NCE37 = 7
,
GPIO_PINCFG37_FNCSEL37_OBSBUS5 = 8
, GPIO_PINCFG37_FNCSEL37_RESERVED9 = 9
, GPIO_PINCFG37_FNCSEL37_RESERVED10 = 10
, GPIO_PINCFG37_FNCSEL37_FPIO = 11
,
GPIO_PINCFG37_FNCSEL37_RESERVED12 = 12
, GPIO_PINCFG37_FNCSEL37_RESERVED13 = 13
, GPIO_PINCFG37_FNCSEL37_RESERVED14 = 14
, GPIO_PINCFG37_FNCSEL37_RESERVED15 = 15
} |
| |
| enum | GPIO_PINCFG38_NCEPOL38_Enum { GPIO_PINCFG38_NCEPOL38_LOW = 0
, GPIO_PINCFG38_NCEPOL38_HIGH = 1
} |
| |
| enum | GPIO_PINCFG38_NCESRC38_Enum {
GPIO_PINCFG38_NCESRC38_IOM0CE0 = 0
, GPIO_PINCFG38_NCESRC38_IOM0CE1 = 1
, GPIO_PINCFG38_NCESRC38_IOM0CE2 = 2
, GPIO_PINCFG38_NCESRC38_IOM0CE3 = 3
,
GPIO_PINCFG38_NCESRC38_IOM1CE0 = 4
, GPIO_PINCFG38_NCESRC38_IOM1CE1 = 5
, GPIO_PINCFG38_NCESRC38_IOM1CE2 = 6
, GPIO_PINCFG38_NCESRC38_IOM1CE3 = 7
,
GPIO_PINCFG38_NCESRC38_IOM2CE0 = 8
, GPIO_PINCFG38_NCESRC38_IOM2CE1 = 9
, GPIO_PINCFG38_NCESRC38_IOM2CE2 = 10
, GPIO_PINCFG38_NCESRC38_IOM2CE3 = 11
,
GPIO_PINCFG38_NCESRC38_IOM3CE0 = 12
, GPIO_PINCFG38_NCESRC38_IOM3CE1 = 13
, GPIO_PINCFG38_NCESRC38_IOM3CE2 = 14
, GPIO_PINCFG38_NCESRC38_IOM3CE3 = 15
,
GPIO_PINCFG38_NCESRC38_IOM4CE0 = 16
, GPIO_PINCFG38_NCESRC38_IOM4CE1 = 17
, GPIO_PINCFG38_NCESRC38_IOM4CE2 = 18
, GPIO_PINCFG38_NCESRC38_IOM4CE3 = 19
,
GPIO_PINCFG38_NCESRC38_IOM5CE0 = 20
, GPIO_PINCFG38_NCESRC38_IOM5CE1 = 21
, GPIO_PINCFG38_NCESRC38_IOM5CE2 = 22
, GPIO_PINCFG38_NCESRC38_IOM5CE3 = 23
,
GPIO_PINCFG38_NCESRC38_IOM6CE0 = 24
, GPIO_PINCFG38_NCESRC38_IOM6CE1 = 25
, GPIO_PINCFG38_NCESRC38_IOM6CE2 = 26
, GPIO_PINCFG38_NCESRC38_IOM6CE3 = 27
,
GPIO_PINCFG38_NCESRC38_IOM7CE0 = 28
, GPIO_PINCFG38_NCESRC38_IOM7CE1 = 29
, GPIO_PINCFG38_NCESRC38_IOM7CE2 = 30
, GPIO_PINCFG38_NCESRC38_IOM7CE3 = 31
,
GPIO_PINCFG38_NCESRC38_MSPI0CEN0 = 32
, GPIO_PINCFG38_NCESRC38_MSPI0CEN1 = 33
, GPIO_PINCFG38_NCESRC38_MSPI1CEN0 = 34
, GPIO_PINCFG38_NCESRC38_MSPI1CEN1 = 35
,
GPIO_PINCFG38_NCESRC38_MSPI2CEN0 = 36
, GPIO_PINCFG38_NCESRC38_MSPI2CEN1 = 37
, GPIO_PINCFG38_NCESRC38_DC_DPI_DE = 38
, GPIO_PINCFG38_NCESRC38_DISP_CONT_CSX = 39
,
GPIO_PINCFG38_NCESRC38_DC_SPI_CS_N = 40
, GPIO_PINCFG38_NCESRC38_DC_QSPI_CS_N = 41
, GPIO_PINCFG38_NCESRC38_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG38_PULLCFG38_Enum {
GPIO_PINCFG38_PULLCFG38_DIS = 0
, GPIO_PINCFG38_PULLCFG38_PD50K = 1
, GPIO_PINCFG38_PULLCFG38_PU15K = 2
, GPIO_PINCFG38_PULLCFG38_PU6K = 3
,
GPIO_PINCFG38_PULLCFG38_PU12K = 4
, GPIO_PINCFG38_PULLCFG38_PU24K = 5
, GPIO_PINCFG38_PULLCFG38_PU50K = 6
, GPIO_PINCFG38_PULLCFG38_PU100K = 7
} |
| |
| enum | GPIO_PINCFG38_DS38_Enum { GPIO_PINCFG38_DS38_0P1X = 0
, GPIO_PINCFG38_DS38_0P5X = 1
, GPIO_PINCFG38_DS38_0P75X = 2
, GPIO_PINCFG38_DS38_1P0X = 3
} |
| |
| enum | GPIO_PINCFG38_OUTCFG38_Enum { GPIO_PINCFG38_OUTCFG38_DIS = 0
, GPIO_PINCFG38_OUTCFG38_PUSHPULL = 1
, GPIO_PINCFG38_OUTCFG38_OD = 2
, GPIO_PINCFG38_OUTCFG38_TS = 3
} |
| |
| enum | GPIO_PINCFG38_IRPTEN38_Enum { GPIO_PINCFG38_IRPTEN38_DIS = 0
, GPIO_PINCFG38_IRPTEN38_INTFALL = 1
, GPIO_PINCFG38_IRPTEN38_INTRISE = 2
, GPIO_PINCFG38_IRPTEN38_INTANY = 3
} |
| |
| enum | GPIO_PINCFG38_FNCSEL38_Enum {
GPIO_PINCFG38_FNCSEL38_MSPI1_1 = 0
, GPIO_PINCFG38_FNCSEL38_TRIG2 = 1
, GPIO_PINCFG38_FNCSEL38_SWTRACECLK = 2
, GPIO_PINCFG38_FNCSEL38_GPIO = 3
,
GPIO_PINCFG38_FNCSEL38_UART0RTS = 4
, GPIO_PINCFG38_FNCSEL38_DISP_D16 = 5
, GPIO_PINCFG38_FNCSEL38_CT38 = 6
, GPIO_PINCFG38_FNCSEL38_NCE38 = 7
,
GPIO_PINCFG38_FNCSEL38_OBSBUS6 = 8
, GPIO_PINCFG38_FNCSEL38_RESERVED9 = 9
, GPIO_PINCFG38_FNCSEL38_RESERVED10 = 10
, GPIO_PINCFG38_FNCSEL38_FPIO = 11
,
GPIO_PINCFG38_FNCSEL38_RESERVED12 = 12
, GPIO_PINCFG38_FNCSEL38_RESERVED13 = 13
, GPIO_PINCFG38_FNCSEL38_RESERVED14 = 14
, GPIO_PINCFG38_FNCSEL38_RESERVED15 = 15
} |
| |
| enum | GPIO_PINCFG39_NCEPOL39_Enum { GPIO_PINCFG39_NCEPOL39_LOW = 0
, GPIO_PINCFG39_NCEPOL39_HIGH = 1
} |
| |
| enum | GPIO_PINCFG39_NCESRC39_Enum {
GPIO_PINCFG39_NCESRC39_IOM0CE0 = 0
, GPIO_PINCFG39_NCESRC39_IOM0CE1 = 1
, GPIO_PINCFG39_NCESRC39_IOM0CE2 = 2
, GPIO_PINCFG39_NCESRC39_IOM0CE3 = 3
,
GPIO_PINCFG39_NCESRC39_IOM1CE0 = 4
, GPIO_PINCFG39_NCESRC39_IOM1CE1 = 5
, GPIO_PINCFG39_NCESRC39_IOM1CE2 = 6
, GPIO_PINCFG39_NCESRC39_IOM1CE3 = 7
,
GPIO_PINCFG39_NCESRC39_IOM2CE0 = 8
, GPIO_PINCFG39_NCESRC39_IOM2CE1 = 9
, GPIO_PINCFG39_NCESRC39_IOM2CE2 = 10
, GPIO_PINCFG39_NCESRC39_IOM2CE3 = 11
,
GPIO_PINCFG39_NCESRC39_IOM3CE0 = 12
, GPIO_PINCFG39_NCESRC39_IOM3CE1 = 13
, GPIO_PINCFG39_NCESRC39_IOM3CE2 = 14
, GPIO_PINCFG39_NCESRC39_IOM3CE3 = 15
,
GPIO_PINCFG39_NCESRC39_IOM4CE0 = 16
, GPIO_PINCFG39_NCESRC39_IOM4CE1 = 17
, GPIO_PINCFG39_NCESRC39_IOM4CE2 = 18
, GPIO_PINCFG39_NCESRC39_IOM4CE3 = 19
,
GPIO_PINCFG39_NCESRC39_IOM5CE0 = 20
, GPIO_PINCFG39_NCESRC39_IOM5CE1 = 21
, GPIO_PINCFG39_NCESRC39_IOM5CE2 = 22
, GPIO_PINCFG39_NCESRC39_IOM5CE3 = 23
,
GPIO_PINCFG39_NCESRC39_IOM6CE0 = 24
, GPIO_PINCFG39_NCESRC39_IOM6CE1 = 25
, GPIO_PINCFG39_NCESRC39_IOM6CE2 = 26
, GPIO_PINCFG39_NCESRC39_IOM6CE3 = 27
,
GPIO_PINCFG39_NCESRC39_IOM7CE0 = 28
, GPIO_PINCFG39_NCESRC39_IOM7CE1 = 29
, GPIO_PINCFG39_NCESRC39_IOM7CE2 = 30
, GPIO_PINCFG39_NCESRC39_IOM7CE3 = 31
,
GPIO_PINCFG39_NCESRC39_MSPI0CEN0 = 32
, GPIO_PINCFG39_NCESRC39_MSPI0CEN1 = 33
, GPIO_PINCFG39_NCESRC39_MSPI1CEN0 = 34
, GPIO_PINCFG39_NCESRC39_MSPI1CEN1 = 35
,
GPIO_PINCFG39_NCESRC39_MSPI2CEN0 = 36
, GPIO_PINCFG39_NCESRC39_MSPI2CEN1 = 37
, GPIO_PINCFG39_NCESRC39_DC_DPI_DE = 38
, GPIO_PINCFG39_NCESRC39_DISP_CONT_CSX = 39
,
GPIO_PINCFG39_NCESRC39_DC_SPI_CS_N = 40
, GPIO_PINCFG39_NCESRC39_DC_QSPI_CS_N = 41
, GPIO_PINCFG39_NCESRC39_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG39_PULLCFG39_Enum {
GPIO_PINCFG39_PULLCFG39_DIS = 0
, GPIO_PINCFG39_PULLCFG39_PD50K = 1
, GPIO_PINCFG39_PULLCFG39_PU15K = 2
, GPIO_PINCFG39_PULLCFG39_PU6K = 3
,
GPIO_PINCFG39_PULLCFG39_PU12K = 4
, GPIO_PINCFG39_PULLCFG39_PU24K = 5
, GPIO_PINCFG39_PULLCFG39_PU50K = 6
, GPIO_PINCFG39_PULLCFG39_PU100K = 7
} |
| |
| enum | GPIO_PINCFG39_DS39_Enum { GPIO_PINCFG39_DS39_0P1X = 0
, GPIO_PINCFG39_DS39_0P5X = 1
, GPIO_PINCFG39_DS39_0P75X = 2
, GPIO_PINCFG39_DS39_1P0X = 3
} |
| |
| enum | GPIO_PINCFG39_OUTCFG39_Enum { GPIO_PINCFG39_OUTCFG39_DIS = 0
, GPIO_PINCFG39_OUTCFG39_PUSHPULL = 1
, GPIO_PINCFG39_OUTCFG39_OD = 2
, GPIO_PINCFG39_OUTCFG39_TS = 3
} |
| |
| enum | GPIO_PINCFG39_IRPTEN39_Enum { GPIO_PINCFG39_IRPTEN39_DIS = 0
, GPIO_PINCFG39_IRPTEN39_INTFALL = 1
, GPIO_PINCFG39_IRPTEN39_INTRISE = 2
, GPIO_PINCFG39_IRPTEN39_INTANY = 3
} |
| |
| enum | GPIO_PINCFG39_FNCSEL39_Enum {
GPIO_PINCFG39_FNCSEL39_MSPI1_2 = 0
, GPIO_PINCFG39_FNCSEL39_TRIG3 = 1
, GPIO_PINCFG39_FNCSEL39_SWTRACE0 = 2
, GPIO_PINCFG39_FNCSEL39_GPIO = 3
,
GPIO_PINCFG39_FNCSEL39_UART2RTS = 4
, GPIO_PINCFG39_FNCSEL39_DISP_D17 = 5
, GPIO_PINCFG39_FNCSEL39_CT39 = 6
, GPIO_PINCFG39_FNCSEL39_NCE39 = 7
,
GPIO_PINCFG39_FNCSEL39_OBSBUS7 = 8
, GPIO_PINCFG39_FNCSEL39_RESERVED9 = 9
, GPIO_PINCFG39_FNCSEL39_RESERVED10 = 10
, GPIO_PINCFG39_FNCSEL39_FPIO = 11
,
GPIO_PINCFG39_FNCSEL39_RESERVED12 = 12
, GPIO_PINCFG39_FNCSEL39_RESERVED13 = 13
, GPIO_PINCFG39_FNCSEL39_RESERVED14 = 14
, GPIO_PINCFG39_FNCSEL39_RESERVED15 = 15
} |
| |
| enum | GPIO_PINCFG40_NCEPOL40_Enum { GPIO_PINCFG40_NCEPOL40_LOW = 0
, GPIO_PINCFG40_NCEPOL40_HIGH = 1
} |
| |
| enum | GPIO_PINCFG40_NCESRC40_Enum {
GPIO_PINCFG40_NCESRC40_IOM0CE0 = 0
, GPIO_PINCFG40_NCESRC40_IOM0CE1 = 1
, GPIO_PINCFG40_NCESRC40_IOM0CE2 = 2
, GPIO_PINCFG40_NCESRC40_IOM0CE3 = 3
,
GPIO_PINCFG40_NCESRC40_IOM1CE0 = 4
, GPIO_PINCFG40_NCESRC40_IOM1CE1 = 5
, GPIO_PINCFG40_NCESRC40_IOM1CE2 = 6
, GPIO_PINCFG40_NCESRC40_IOM1CE3 = 7
,
GPIO_PINCFG40_NCESRC40_IOM2CE0 = 8
, GPIO_PINCFG40_NCESRC40_IOM2CE1 = 9
, GPIO_PINCFG40_NCESRC40_IOM2CE2 = 10
, GPIO_PINCFG40_NCESRC40_IOM2CE3 = 11
,
GPIO_PINCFG40_NCESRC40_IOM3CE0 = 12
, GPIO_PINCFG40_NCESRC40_IOM3CE1 = 13
, GPIO_PINCFG40_NCESRC40_IOM3CE2 = 14
, GPIO_PINCFG40_NCESRC40_IOM3CE3 = 15
,
GPIO_PINCFG40_NCESRC40_IOM4CE0 = 16
, GPIO_PINCFG40_NCESRC40_IOM4CE1 = 17
, GPIO_PINCFG40_NCESRC40_IOM4CE2 = 18
, GPIO_PINCFG40_NCESRC40_IOM4CE3 = 19
,
GPIO_PINCFG40_NCESRC40_IOM5CE0 = 20
, GPIO_PINCFG40_NCESRC40_IOM5CE1 = 21
, GPIO_PINCFG40_NCESRC40_IOM5CE2 = 22
, GPIO_PINCFG40_NCESRC40_IOM5CE3 = 23
,
GPIO_PINCFG40_NCESRC40_IOM6CE0 = 24
, GPIO_PINCFG40_NCESRC40_IOM6CE1 = 25
, GPIO_PINCFG40_NCESRC40_IOM6CE2 = 26
, GPIO_PINCFG40_NCESRC40_IOM6CE3 = 27
,
GPIO_PINCFG40_NCESRC40_IOM7CE0 = 28
, GPIO_PINCFG40_NCESRC40_IOM7CE1 = 29
, GPIO_PINCFG40_NCESRC40_IOM7CE2 = 30
, GPIO_PINCFG40_NCESRC40_IOM7CE3 = 31
,
GPIO_PINCFG40_NCESRC40_MSPI0CEN0 = 32
, GPIO_PINCFG40_NCESRC40_MSPI0CEN1 = 33
, GPIO_PINCFG40_NCESRC40_MSPI1CEN0 = 34
, GPIO_PINCFG40_NCESRC40_MSPI1CEN1 = 35
,
GPIO_PINCFG40_NCESRC40_MSPI2CEN0 = 36
, GPIO_PINCFG40_NCESRC40_MSPI2CEN1 = 37
, GPIO_PINCFG40_NCESRC40_DC_DPI_DE = 38
, GPIO_PINCFG40_NCESRC40_DISP_CONT_CSX = 39
,
GPIO_PINCFG40_NCESRC40_DC_SPI_CS_N = 40
, GPIO_PINCFG40_NCESRC40_DC_QSPI_CS_N = 41
, GPIO_PINCFG40_NCESRC40_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG40_PULLCFG40_Enum {
GPIO_PINCFG40_PULLCFG40_DIS = 0
, GPIO_PINCFG40_PULLCFG40_PD50K = 1
, GPIO_PINCFG40_PULLCFG40_PU15K = 2
, GPIO_PINCFG40_PULLCFG40_PU6K = 3
,
GPIO_PINCFG40_PULLCFG40_PU12K = 4
, GPIO_PINCFG40_PULLCFG40_PU24K = 5
, GPIO_PINCFG40_PULLCFG40_PU50K = 6
, GPIO_PINCFG40_PULLCFG40_PU100K = 7
} |
| |
| enum | GPIO_PINCFG40_DS40_Enum { GPIO_PINCFG40_DS40_0P1X = 0
, GPIO_PINCFG40_DS40_0P5X = 1
, GPIO_PINCFG40_DS40_0P75X = 2
, GPIO_PINCFG40_DS40_1P0X = 3
} |
| |
| enum | GPIO_PINCFG40_OUTCFG40_Enum { GPIO_PINCFG40_OUTCFG40_DIS = 0
, GPIO_PINCFG40_OUTCFG40_PUSHPULL = 1
, GPIO_PINCFG40_OUTCFG40_OD = 2
, GPIO_PINCFG40_OUTCFG40_TS = 3
} |
| |
| enum | GPIO_PINCFG40_IRPTEN40_Enum { GPIO_PINCFG40_IRPTEN40_DIS = 0
, GPIO_PINCFG40_IRPTEN40_INTFALL = 1
, GPIO_PINCFG40_IRPTEN40_INTRISE = 2
, GPIO_PINCFG40_IRPTEN40_INTANY = 3
} |
| |
| enum | GPIO_PINCFG40_FNCSEL40_Enum {
GPIO_PINCFG40_FNCSEL40_MSPI1_3 = 0
, GPIO_PINCFG40_FNCSEL40_TRIG1 = 1
, GPIO_PINCFG40_FNCSEL40_SWTRACE1 = 2
, GPIO_PINCFG40_FNCSEL40_GPIO = 3
,
GPIO_PINCFG40_FNCSEL40_UART0CTS = 4
, GPIO_PINCFG40_FNCSEL40_DISP_D18 = 5
, GPIO_PINCFG40_FNCSEL40_CT40 = 6
, GPIO_PINCFG40_FNCSEL40_NCE40 = 7
,
GPIO_PINCFG40_FNCSEL40_OBSBUS8 = 8
, GPIO_PINCFG40_FNCSEL40_RESERVED9 = 9
, GPIO_PINCFG40_FNCSEL40_RESERVED10 = 10
, GPIO_PINCFG40_FNCSEL40_FPIO = 11
,
GPIO_PINCFG40_FNCSEL40_RESERVED12 = 12
, GPIO_PINCFG40_FNCSEL40_RESERVED13 = 13
, GPIO_PINCFG40_FNCSEL40_RESERVED14 = 14
, GPIO_PINCFG40_FNCSEL40_RESERVED15 = 15
} |
| |
| enum | GPIO_PINCFG41_NCEPOL41_Enum { GPIO_PINCFG41_NCEPOL41_LOW = 0
, GPIO_PINCFG41_NCEPOL41_HIGH = 1
} |
| |
| enum | GPIO_PINCFG41_NCESRC41_Enum {
GPIO_PINCFG41_NCESRC41_IOM0CE0 = 0
, GPIO_PINCFG41_NCESRC41_IOM0CE1 = 1
, GPIO_PINCFG41_NCESRC41_IOM0CE2 = 2
, GPIO_PINCFG41_NCESRC41_IOM0CE3 = 3
,
GPIO_PINCFG41_NCESRC41_IOM1CE0 = 4
, GPIO_PINCFG41_NCESRC41_IOM1CE1 = 5
, GPIO_PINCFG41_NCESRC41_IOM1CE2 = 6
, GPIO_PINCFG41_NCESRC41_IOM1CE3 = 7
,
GPIO_PINCFG41_NCESRC41_IOM2CE0 = 8
, GPIO_PINCFG41_NCESRC41_IOM2CE1 = 9
, GPIO_PINCFG41_NCESRC41_IOM2CE2 = 10
, GPIO_PINCFG41_NCESRC41_IOM2CE3 = 11
,
GPIO_PINCFG41_NCESRC41_IOM3CE0 = 12
, GPIO_PINCFG41_NCESRC41_IOM3CE1 = 13
, GPIO_PINCFG41_NCESRC41_IOM3CE2 = 14
, GPIO_PINCFG41_NCESRC41_IOM3CE3 = 15
,
GPIO_PINCFG41_NCESRC41_IOM4CE0 = 16
, GPIO_PINCFG41_NCESRC41_IOM4CE1 = 17
, GPIO_PINCFG41_NCESRC41_IOM4CE2 = 18
, GPIO_PINCFG41_NCESRC41_IOM4CE3 = 19
,
GPIO_PINCFG41_NCESRC41_IOM5CE0 = 20
, GPIO_PINCFG41_NCESRC41_IOM5CE1 = 21
, GPIO_PINCFG41_NCESRC41_IOM5CE2 = 22
, GPIO_PINCFG41_NCESRC41_IOM5CE3 = 23
,
GPIO_PINCFG41_NCESRC41_IOM6CE0 = 24
, GPIO_PINCFG41_NCESRC41_IOM6CE1 = 25
, GPIO_PINCFG41_NCESRC41_IOM6CE2 = 26
, GPIO_PINCFG41_NCESRC41_IOM6CE3 = 27
,
GPIO_PINCFG41_NCESRC41_IOM7CE0 = 28
, GPIO_PINCFG41_NCESRC41_IOM7CE1 = 29
, GPIO_PINCFG41_NCESRC41_IOM7CE2 = 30
, GPIO_PINCFG41_NCESRC41_IOM7CE3 = 31
,
GPIO_PINCFG41_NCESRC41_MSPI0CEN0 = 32
, GPIO_PINCFG41_NCESRC41_MSPI0CEN1 = 33
, GPIO_PINCFG41_NCESRC41_MSPI1CEN0 = 34
, GPIO_PINCFG41_NCESRC41_MSPI1CEN1 = 35
,
GPIO_PINCFG41_NCESRC41_MSPI2CEN0 = 36
, GPIO_PINCFG41_NCESRC41_MSPI2CEN1 = 37
, GPIO_PINCFG41_NCESRC41_DC_DPI_DE = 38
, GPIO_PINCFG41_NCESRC41_DISP_CONT_CSX = 39
,
GPIO_PINCFG41_NCESRC41_DC_SPI_CS_N = 40
, GPIO_PINCFG41_NCESRC41_DC_QSPI_CS_N = 41
, GPIO_PINCFG41_NCESRC41_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG41_PULLCFG41_Enum {
GPIO_PINCFG41_PULLCFG41_DIS = 0
, GPIO_PINCFG41_PULLCFG41_PD50K = 1
, GPIO_PINCFG41_PULLCFG41_PU15K = 2
, GPIO_PINCFG41_PULLCFG41_PU6K = 3
,
GPIO_PINCFG41_PULLCFG41_PU12K = 4
, GPIO_PINCFG41_PULLCFG41_PU24K = 5
, GPIO_PINCFG41_PULLCFG41_PU50K = 6
, GPIO_PINCFG41_PULLCFG41_PU100K = 7
} |
| |
| enum | GPIO_PINCFG41_DS41_Enum { GPIO_PINCFG41_DS41_0P1X = 0
, GPIO_PINCFG41_DS41_0P5X = 1
, GPIO_PINCFG41_DS41_0P75X = 2
, GPIO_PINCFG41_DS41_1P0X = 3
} |
| |
| enum | GPIO_PINCFG41_OUTCFG41_Enum { GPIO_PINCFG41_OUTCFG41_DIS = 0
, GPIO_PINCFG41_OUTCFG41_PUSHPULL = 1
, GPIO_PINCFG41_OUTCFG41_OD = 2
, GPIO_PINCFG41_OUTCFG41_TS = 3
} |
| |
| enum | GPIO_PINCFG41_IRPTEN41_Enum { GPIO_PINCFG41_IRPTEN41_DIS = 0
, GPIO_PINCFG41_IRPTEN41_INTFALL = 1
, GPIO_PINCFG41_IRPTEN41_INTRISE = 2
, GPIO_PINCFG41_IRPTEN41_INTANY = 3
} |
| |
| enum | GPIO_PINCFG41_FNCSEL41_Enum {
GPIO_PINCFG41_FNCSEL41_MSPI1_4 = 0
, GPIO_PINCFG41_FNCSEL41_TRIG0 = 1
, GPIO_PINCFG41_FNCSEL41_SWTRACE2 = 2
, GPIO_PINCFG41_FNCSEL41_GPIO = 3
,
GPIO_PINCFG41_FNCSEL41_UART0TX = 4
, GPIO_PINCFG41_FNCSEL41_DISP_D19 = 5
, GPIO_PINCFG41_FNCSEL41_CT41 = 6
, GPIO_PINCFG41_FNCSEL41_NCE41 = 7
,
GPIO_PINCFG41_FNCSEL41_OBSBUS9 = 8
, GPIO_PINCFG41_FNCSEL41_SWO = 9
, GPIO_PINCFG41_FNCSEL41_RESERVED10 = 10
, GPIO_PINCFG41_FNCSEL41_FPIO = 11
,
GPIO_PINCFG41_FNCSEL41_RESERVED12 = 12
, GPIO_PINCFG41_FNCSEL41_RESERVED13 = 13
, GPIO_PINCFG41_FNCSEL41_RESERVED14 = 14
, GPIO_PINCFG41_FNCSEL41_RESERVED15 = 15
} |
| |
| enum | GPIO_PINCFG42_NCEPOL42_Enum { GPIO_PINCFG42_NCEPOL42_LOW = 0
, GPIO_PINCFG42_NCEPOL42_HIGH = 1
} |
| |
| enum | GPIO_PINCFG42_NCESRC42_Enum {
GPIO_PINCFG42_NCESRC42_IOM0CE0 = 0
, GPIO_PINCFG42_NCESRC42_IOM0CE1 = 1
, GPIO_PINCFG42_NCESRC42_IOM0CE2 = 2
, GPIO_PINCFG42_NCESRC42_IOM0CE3 = 3
,
GPIO_PINCFG42_NCESRC42_IOM1CE0 = 4
, GPIO_PINCFG42_NCESRC42_IOM1CE1 = 5
, GPIO_PINCFG42_NCESRC42_IOM1CE2 = 6
, GPIO_PINCFG42_NCESRC42_IOM1CE3 = 7
,
GPIO_PINCFG42_NCESRC42_IOM2CE0 = 8
, GPIO_PINCFG42_NCESRC42_IOM2CE1 = 9
, GPIO_PINCFG42_NCESRC42_IOM2CE2 = 10
, GPIO_PINCFG42_NCESRC42_IOM2CE3 = 11
,
GPIO_PINCFG42_NCESRC42_IOM3CE0 = 12
, GPIO_PINCFG42_NCESRC42_IOM3CE1 = 13
, GPIO_PINCFG42_NCESRC42_IOM3CE2 = 14
, GPIO_PINCFG42_NCESRC42_IOM3CE3 = 15
,
GPIO_PINCFG42_NCESRC42_IOM4CE0 = 16
, GPIO_PINCFG42_NCESRC42_IOM4CE1 = 17
, GPIO_PINCFG42_NCESRC42_IOM4CE2 = 18
, GPIO_PINCFG42_NCESRC42_IOM4CE3 = 19
,
GPIO_PINCFG42_NCESRC42_IOM5CE0 = 20
, GPIO_PINCFG42_NCESRC42_IOM5CE1 = 21
, GPIO_PINCFG42_NCESRC42_IOM5CE2 = 22
, GPIO_PINCFG42_NCESRC42_IOM5CE3 = 23
,
GPIO_PINCFG42_NCESRC42_IOM6CE0 = 24
, GPIO_PINCFG42_NCESRC42_IOM6CE1 = 25
, GPIO_PINCFG42_NCESRC42_IOM6CE2 = 26
, GPIO_PINCFG42_NCESRC42_IOM6CE3 = 27
,
GPIO_PINCFG42_NCESRC42_IOM7CE0 = 28
, GPIO_PINCFG42_NCESRC42_IOM7CE1 = 29
, GPIO_PINCFG42_NCESRC42_IOM7CE2 = 30
, GPIO_PINCFG42_NCESRC42_IOM7CE3 = 31
,
GPIO_PINCFG42_NCESRC42_MSPI0CEN0 = 32
, GPIO_PINCFG42_NCESRC42_MSPI0CEN1 = 33
, GPIO_PINCFG42_NCESRC42_MSPI1CEN0 = 34
, GPIO_PINCFG42_NCESRC42_MSPI1CEN1 = 35
,
GPIO_PINCFG42_NCESRC42_MSPI2CEN0 = 36
, GPIO_PINCFG42_NCESRC42_MSPI2CEN1 = 37
, GPIO_PINCFG42_NCESRC42_DC_DPI_DE = 38
, GPIO_PINCFG42_NCESRC42_DISP_CONT_CSX = 39
,
GPIO_PINCFG42_NCESRC42_DC_SPI_CS_N = 40
, GPIO_PINCFG42_NCESRC42_DC_QSPI_CS_N = 41
, GPIO_PINCFG42_NCESRC42_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG42_PULLCFG42_Enum {
GPIO_PINCFG42_PULLCFG42_DIS = 0
, GPIO_PINCFG42_PULLCFG42_PD50K = 1
, GPIO_PINCFG42_PULLCFG42_PU15K = 2
, GPIO_PINCFG42_PULLCFG42_PU6K = 3
,
GPIO_PINCFG42_PULLCFG42_PU12K = 4
, GPIO_PINCFG42_PULLCFG42_PU24K = 5
, GPIO_PINCFG42_PULLCFG42_PU50K = 6
, GPIO_PINCFG42_PULLCFG42_PU100K = 7
} |
| |
| enum | GPIO_PINCFG42_DS42_Enum { GPIO_PINCFG42_DS42_0P1X = 0
, GPIO_PINCFG42_DS42_0P5X = 1
, GPIO_PINCFG42_DS42_0P75X = 2
, GPIO_PINCFG42_DS42_1P0X = 3
} |
| |
| enum | GPIO_PINCFG42_OUTCFG42_Enum { GPIO_PINCFG42_OUTCFG42_DIS = 0
, GPIO_PINCFG42_OUTCFG42_PUSHPULL = 1
, GPIO_PINCFG42_OUTCFG42_OD = 2
, GPIO_PINCFG42_OUTCFG42_TS = 3
} |
| |
| enum | GPIO_PINCFG42_IRPTEN42_Enum { GPIO_PINCFG42_IRPTEN42_DIS = 0
, GPIO_PINCFG42_IRPTEN42_INTFALL = 1
, GPIO_PINCFG42_IRPTEN42_INTRISE = 2
, GPIO_PINCFG42_IRPTEN42_INTANY = 3
} |
| |
| enum | GPIO_PINCFG42_FNCSEL42_Enum {
GPIO_PINCFG42_FNCSEL42_MSPI1_5 = 0
, GPIO_PINCFG42_FNCSEL42_TRIG2 = 1
, GPIO_PINCFG42_FNCSEL42_SWTRACE3 = 2
, GPIO_PINCFG42_FNCSEL42_GPIO = 3
,
GPIO_PINCFG42_FNCSEL42_UART2TX = 4
, GPIO_PINCFG42_FNCSEL42_DISP_D20 = 5
, GPIO_PINCFG42_FNCSEL42_CT42 = 6
, GPIO_PINCFG42_FNCSEL42_NCE42 = 7
,
GPIO_PINCFG42_FNCSEL42_OBSBUS10 = 8
, GPIO_PINCFG42_FNCSEL42_RESERVED9 = 9
, GPIO_PINCFG42_FNCSEL42_RESERVED10 = 10
, GPIO_PINCFG42_FNCSEL42_FPIO = 11
,
GPIO_PINCFG42_FNCSEL42_RESERVED12 = 12
, GPIO_PINCFG42_FNCSEL42_RESERVED13 = 13
, GPIO_PINCFG42_FNCSEL42_RESERVED14 = 14
, GPIO_PINCFG42_FNCSEL42_RESERVED15 = 15
} |
| |
| enum | GPIO_PINCFG43_NCEPOL43_Enum { GPIO_PINCFG43_NCEPOL43_LOW = 0
, GPIO_PINCFG43_NCEPOL43_HIGH = 1
} |
| |
| enum | GPIO_PINCFG43_NCESRC43_Enum {
GPIO_PINCFG43_NCESRC43_IOM0CE0 = 0
, GPIO_PINCFG43_NCESRC43_IOM0CE1 = 1
, GPIO_PINCFG43_NCESRC43_IOM0CE2 = 2
, GPIO_PINCFG43_NCESRC43_IOM0CE3 = 3
,
GPIO_PINCFG43_NCESRC43_IOM1CE0 = 4
, GPIO_PINCFG43_NCESRC43_IOM1CE1 = 5
, GPIO_PINCFG43_NCESRC43_IOM1CE2 = 6
, GPIO_PINCFG43_NCESRC43_IOM1CE3 = 7
,
GPIO_PINCFG43_NCESRC43_IOM2CE0 = 8
, GPIO_PINCFG43_NCESRC43_IOM2CE1 = 9
, GPIO_PINCFG43_NCESRC43_IOM2CE2 = 10
, GPIO_PINCFG43_NCESRC43_IOM2CE3 = 11
,
GPIO_PINCFG43_NCESRC43_IOM3CE0 = 12
, GPIO_PINCFG43_NCESRC43_IOM3CE1 = 13
, GPIO_PINCFG43_NCESRC43_IOM3CE2 = 14
, GPIO_PINCFG43_NCESRC43_IOM3CE3 = 15
,
GPIO_PINCFG43_NCESRC43_IOM4CE0 = 16
, GPIO_PINCFG43_NCESRC43_IOM4CE1 = 17
, GPIO_PINCFG43_NCESRC43_IOM4CE2 = 18
, GPIO_PINCFG43_NCESRC43_IOM4CE3 = 19
,
GPIO_PINCFG43_NCESRC43_IOM5CE0 = 20
, GPIO_PINCFG43_NCESRC43_IOM5CE1 = 21
, GPIO_PINCFG43_NCESRC43_IOM5CE2 = 22
, GPIO_PINCFG43_NCESRC43_IOM5CE3 = 23
,
GPIO_PINCFG43_NCESRC43_IOM6CE0 = 24
, GPIO_PINCFG43_NCESRC43_IOM6CE1 = 25
, GPIO_PINCFG43_NCESRC43_IOM6CE2 = 26
, GPIO_PINCFG43_NCESRC43_IOM6CE3 = 27
,
GPIO_PINCFG43_NCESRC43_IOM7CE0 = 28
, GPIO_PINCFG43_NCESRC43_IOM7CE1 = 29
, GPIO_PINCFG43_NCESRC43_IOM7CE2 = 30
, GPIO_PINCFG43_NCESRC43_IOM7CE3 = 31
,
GPIO_PINCFG43_NCESRC43_MSPI0CEN0 = 32
, GPIO_PINCFG43_NCESRC43_MSPI0CEN1 = 33
, GPIO_PINCFG43_NCESRC43_MSPI1CEN0 = 34
, GPIO_PINCFG43_NCESRC43_MSPI1CEN1 = 35
,
GPIO_PINCFG43_NCESRC43_MSPI2CEN0 = 36
, GPIO_PINCFG43_NCESRC43_MSPI2CEN1 = 37
, GPIO_PINCFG43_NCESRC43_DC_DPI_DE = 38
, GPIO_PINCFG43_NCESRC43_DISP_CONT_CSX = 39
,
GPIO_PINCFG43_NCESRC43_DC_SPI_CS_N = 40
, GPIO_PINCFG43_NCESRC43_DC_QSPI_CS_N = 41
, GPIO_PINCFG43_NCESRC43_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG43_PULLCFG43_Enum {
GPIO_PINCFG43_PULLCFG43_DIS = 0
, GPIO_PINCFG43_PULLCFG43_PD50K = 1
, GPIO_PINCFG43_PULLCFG43_PU15K = 2
, GPIO_PINCFG43_PULLCFG43_PU6K = 3
,
GPIO_PINCFG43_PULLCFG43_PU12K = 4
, GPIO_PINCFG43_PULLCFG43_PU24K = 5
, GPIO_PINCFG43_PULLCFG43_PU50K = 6
, GPIO_PINCFG43_PULLCFG43_PU100K = 7
} |
| |
| enum | GPIO_PINCFG43_DS43_Enum { GPIO_PINCFG43_DS43_0P1X = 0
, GPIO_PINCFG43_DS43_0P5X = 1
, GPIO_PINCFG43_DS43_0P75X = 2
, GPIO_PINCFG43_DS43_1P0X = 3
} |
| |
| enum | GPIO_PINCFG43_OUTCFG43_Enum { GPIO_PINCFG43_OUTCFG43_DIS = 0
, GPIO_PINCFG43_OUTCFG43_PUSHPULL = 1
, GPIO_PINCFG43_OUTCFG43_OD = 2
, GPIO_PINCFG43_OUTCFG43_TS = 3
} |
| |
| enum | GPIO_PINCFG43_IRPTEN43_Enum { GPIO_PINCFG43_IRPTEN43_DIS = 0
, GPIO_PINCFG43_IRPTEN43_INTFALL = 1
, GPIO_PINCFG43_IRPTEN43_INTRISE = 2
, GPIO_PINCFG43_IRPTEN43_INTANY = 3
} |
| |
| enum | GPIO_PINCFG43_FNCSEL43_Enum {
GPIO_PINCFG43_FNCSEL43_MSPI1_6 = 0
, GPIO_PINCFG43_FNCSEL43_TRIG3 = 1
, GPIO_PINCFG43_FNCSEL43_SWTRACECTL = 2
, GPIO_PINCFG43_FNCSEL43_GPIO = 3
,
GPIO_PINCFG43_FNCSEL43_UART0RX = 4
, GPIO_PINCFG43_FNCSEL43_DISP_D21 = 5
, GPIO_PINCFG43_FNCSEL43_CT43 = 6
, GPIO_PINCFG43_FNCSEL43_NCE43 = 7
,
GPIO_PINCFG43_FNCSEL43_OBSBUS11 = 8
, GPIO_PINCFG43_FNCSEL43_RESERVED9 = 9
, GPIO_PINCFG43_FNCSEL43_RESERVED10 = 10
, GPIO_PINCFG43_FNCSEL43_FPIO = 11
,
GPIO_PINCFG43_FNCSEL43_RESERVED12 = 12
, GPIO_PINCFG43_FNCSEL43_RESERVED13 = 13
, GPIO_PINCFG43_FNCSEL43_RESERVED14 = 14
, GPIO_PINCFG43_FNCSEL43_RESERVED15 = 15
} |
| |
| enum | GPIO_PINCFG44_NCEPOL44_Enum { GPIO_PINCFG44_NCEPOL44_LOW = 0
, GPIO_PINCFG44_NCEPOL44_HIGH = 1
} |
| |
| enum | GPIO_PINCFG44_NCESRC44_Enum {
GPIO_PINCFG44_NCESRC44_IOM0CE0 = 0
, GPIO_PINCFG44_NCESRC44_IOM0CE1 = 1
, GPIO_PINCFG44_NCESRC44_IOM0CE2 = 2
, GPIO_PINCFG44_NCESRC44_IOM0CE3 = 3
,
GPIO_PINCFG44_NCESRC44_IOM1CE0 = 4
, GPIO_PINCFG44_NCESRC44_IOM1CE1 = 5
, GPIO_PINCFG44_NCESRC44_IOM1CE2 = 6
, GPIO_PINCFG44_NCESRC44_IOM1CE3 = 7
,
GPIO_PINCFG44_NCESRC44_IOM2CE0 = 8
, GPIO_PINCFG44_NCESRC44_IOM2CE1 = 9
, GPIO_PINCFG44_NCESRC44_IOM2CE2 = 10
, GPIO_PINCFG44_NCESRC44_IOM2CE3 = 11
,
GPIO_PINCFG44_NCESRC44_IOM3CE0 = 12
, GPIO_PINCFG44_NCESRC44_IOM3CE1 = 13
, GPIO_PINCFG44_NCESRC44_IOM3CE2 = 14
, GPIO_PINCFG44_NCESRC44_IOM3CE3 = 15
,
GPIO_PINCFG44_NCESRC44_IOM4CE0 = 16
, GPIO_PINCFG44_NCESRC44_IOM4CE1 = 17
, GPIO_PINCFG44_NCESRC44_IOM4CE2 = 18
, GPIO_PINCFG44_NCESRC44_IOM4CE3 = 19
,
GPIO_PINCFG44_NCESRC44_IOM5CE0 = 20
, GPIO_PINCFG44_NCESRC44_IOM5CE1 = 21
, GPIO_PINCFG44_NCESRC44_IOM5CE2 = 22
, GPIO_PINCFG44_NCESRC44_IOM5CE3 = 23
,
GPIO_PINCFG44_NCESRC44_IOM6CE0 = 24
, GPIO_PINCFG44_NCESRC44_IOM6CE1 = 25
, GPIO_PINCFG44_NCESRC44_IOM6CE2 = 26
, GPIO_PINCFG44_NCESRC44_IOM6CE3 = 27
,
GPIO_PINCFG44_NCESRC44_IOM7CE0 = 28
, GPIO_PINCFG44_NCESRC44_IOM7CE1 = 29
, GPIO_PINCFG44_NCESRC44_IOM7CE2 = 30
, GPIO_PINCFG44_NCESRC44_IOM7CE3 = 31
,
GPIO_PINCFG44_NCESRC44_MSPI0CEN0 = 32
, GPIO_PINCFG44_NCESRC44_MSPI0CEN1 = 33
, GPIO_PINCFG44_NCESRC44_MSPI1CEN0 = 34
, GPIO_PINCFG44_NCESRC44_MSPI1CEN1 = 35
,
GPIO_PINCFG44_NCESRC44_MSPI2CEN0 = 36
, GPIO_PINCFG44_NCESRC44_MSPI2CEN1 = 37
, GPIO_PINCFG44_NCESRC44_DC_DPI_DE = 38
, GPIO_PINCFG44_NCESRC44_DISP_CONT_CSX = 39
,
GPIO_PINCFG44_NCESRC44_DC_SPI_CS_N = 40
, GPIO_PINCFG44_NCESRC44_DC_QSPI_CS_N = 41
, GPIO_PINCFG44_NCESRC44_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG44_PULLCFG44_Enum {
GPIO_PINCFG44_PULLCFG44_DIS = 0
, GPIO_PINCFG44_PULLCFG44_PD50K = 1
, GPIO_PINCFG44_PULLCFG44_PU15K = 2
, GPIO_PINCFG44_PULLCFG44_PU6K = 3
,
GPIO_PINCFG44_PULLCFG44_PU12K = 4
, GPIO_PINCFG44_PULLCFG44_PU24K = 5
, GPIO_PINCFG44_PULLCFG44_PU50K = 6
, GPIO_PINCFG44_PULLCFG44_PU100K = 7
} |
| |
| enum | GPIO_PINCFG44_DS44_Enum { GPIO_PINCFG44_DS44_0P1X = 0
, GPIO_PINCFG44_DS44_0P5X = 1
, GPIO_PINCFG44_DS44_0P75X = 2
, GPIO_PINCFG44_DS44_1P0X = 3
} |
| |
| enum | GPIO_PINCFG44_OUTCFG44_Enum { GPIO_PINCFG44_OUTCFG44_DIS = 0
, GPIO_PINCFG44_OUTCFG44_PUSHPULL = 1
, GPIO_PINCFG44_OUTCFG44_OD = 2
, GPIO_PINCFG44_OUTCFG44_TS = 3
} |
| |
| enum | GPIO_PINCFG44_IRPTEN44_Enum { GPIO_PINCFG44_IRPTEN44_DIS = 0
, GPIO_PINCFG44_IRPTEN44_INTFALL = 1
, GPIO_PINCFG44_IRPTEN44_INTRISE = 2
, GPIO_PINCFG44_IRPTEN44_INTANY = 3
} |
| |
| enum | GPIO_PINCFG44_FNCSEL44_Enum {
GPIO_PINCFG44_FNCSEL44_MSPI1_7 = 0
, GPIO_PINCFG44_FNCSEL44_TRIG1 = 1
, GPIO_PINCFG44_FNCSEL44_SWO = 2
, GPIO_PINCFG44_FNCSEL44_GPIO = 3
,
GPIO_PINCFG44_FNCSEL44_UART2RX = 4
, GPIO_PINCFG44_FNCSEL44_DISP_D22 = 5
, GPIO_PINCFG44_FNCSEL44_CT44 = 6
, GPIO_PINCFG44_FNCSEL44_NCE44 = 7
,
GPIO_PINCFG44_FNCSEL44_OBSBUS12 = 8
, GPIO_PINCFG44_FNCSEL44_VCMPO = 9
, GPIO_PINCFG44_FNCSEL44_RESERVED10 = 10
, GPIO_PINCFG44_FNCSEL44_FPIO = 11
,
GPIO_PINCFG44_FNCSEL44_RESERVED12 = 12
, GPIO_PINCFG44_FNCSEL44_RESERVED13 = 13
, GPIO_PINCFG44_FNCSEL44_RESERVED14 = 14
, GPIO_PINCFG44_FNCSEL44_RESERVED15 = 15
} |
| |
| enum | GPIO_PINCFG45_NCEPOL45_Enum { GPIO_PINCFG45_NCEPOL45_LOW = 0
, GPIO_PINCFG45_NCEPOL45_HIGH = 1
} |
| |
| enum | GPIO_PINCFG45_NCESRC45_Enum {
GPIO_PINCFG45_NCESRC45_IOM0CE0 = 0
, GPIO_PINCFG45_NCESRC45_IOM0CE1 = 1
, GPIO_PINCFG45_NCESRC45_IOM0CE2 = 2
, GPIO_PINCFG45_NCESRC45_IOM0CE3 = 3
,
GPIO_PINCFG45_NCESRC45_IOM1CE0 = 4
, GPIO_PINCFG45_NCESRC45_IOM1CE1 = 5
, GPIO_PINCFG45_NCESRC45_IOM1CE2 = 6
, GPIO_PINCFG45_NCESRC45_IOM1CE3 = 7
,
GPIO_PINCFG45_NCESRC45_IOM2CE0 = 8
, GPIO_PINCFG45_NCESRC45_IOM2CE1 = 9
, GPIO_PINCFG45_NCESRC45_IOM2CE2 = 10
, GPIO_PINCFG45_NCESRC45_IOM2CE3 = 11
,
GPIO_PINCFG45_NCESRC45_IOM3CE0 = 12
, GPIO_PINCFG45_NCESRC45_IOM3CE1 = 13
, GPIO_PINCFG45_NCESRC45_IOM3CE2 = 14
, GPIO_PINCFG45_NCESRC45_IOM3CE3 = 15
,
GPIO_PINCFG45_NCESRC45_IOM4CE0 = 16
, GPIO_PINCFG45_NCESRC45_IOM4CE1 = 17
, GPIO_PINCFG45_NCESRC45_IOM4CE2 = 18
, GPIO_PINCFG45_NCESRC45_IOM4CE3 = 19
,
GPIO_PINCFG45_NCESRC45_IOM5CE0 = 20
, GPIO_PINCFG45_NCESRC45_IOM5CE1 = 21
, GPIO_PINCFG45_NCESRC45_IOM5CE2 = 22
, GPIO_PINCFG45_NCESRC45_IOM5CE3 = 23
,
GPIO_PINCFG45_NCESRC45_IOM6CE0 = 24
, GPIO_PINCFG45_NCESRC45_IOM6CE1 = 25
, GPIO_PINCFG45_NCESRC45_IOM6CE2 = 26
, GPIO_PINCFG45_NCESRC45_IOM6CE3 = 27
,
GPIO_PINCFG45_NCESRC45_IOM7CE0 = 28
, GPIO_PINCFG45_NCESRC45_IOM7CE1 = 29
, GPIO_PINCFG45_NCESRC45_IOM7CE2 = 30
, GPIO_PINCFG45_NCESRC45_IOM7CE3 = 31
,
GPIO_PINCFG45_NCESRC45_MSPI0CEN0 = 32
, GPIO_PINCFG45_NCESRC45_MSPI0CEN1 = 33
, GPIO_PINCFG45_NCESRC45_MSPI1CEN0 = 34
, GPIO_PINCFG45_NCESRC45_MSPI1CEN1 = 35
,
GPIO_PINCFG45_NCESRC45_MSPI2CEN0 = 36
, GPIO_PINCFG45_NCESRC45_MSPI2CEN1 = 37
, GPIO_PINCFG45_NCESRC45_DC_DPI_DE = 38
, GPIO_PINCFG45_NCESRC45_DISP_CONT_CSX = 39
,
GPIO_PINCFG45_NCESRC45_DC_SPI_CS_N = 40
, GPIO_PINCFG45_NCESRC45_DC_QSPI_CS_N = 41
, GPIO_PINCFG45_NCESRC45_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG45_PULLCFG45_Enum {
GPIO_PINCFG45_PULLCFG45_DIS = 0
, GPIO_PINCFG45_PULLCFG45_PD50K = 1
, GPIO_PINCFG45_PULLCFG45_PU15K = 2
, GPIO_PINCFG45_PULLCFG45_PU6K = 3
,
GPIO_PINCFG45_PULLCFG45_PU12K = 4
, GPIO_PINCFG45_PULLCFG45_PU24K = 5
, GPIO_PINCFG45_PULLCFG45_PU50K = 6
, GPIO_PINCFG45_PULLCFG45_PU100K = 7
} |
| |
| enum | GPIO_PINCFG45_DS45_Enum { GPIO_PINCFG45_DS45_0P1X = 0
, GPIO_PINCFG45_DS45_0P5X = 1
, GPIO_PINCFG45_DS45_0P75X = 2
, GPIO_PINCFG45_DS45_1P0X = 3
} |
| |
| enum | GPIO_PINCFG45_OUTCFG45_Enum { GPIO_PINCFG45_OUTCFG45_DIS = 0
, GPIO_PINCFG45_OUTCFG45_PUSHPULL = 1
, GPIO_PINCFG45_OUTCFG45_OD = 2
, GPIO_PINCFG45_OUTCFG45_TS = 3
} |
| |
| enum | GPIO_PINCFG45_IRPTEN45_Enum { GPIO_PINCFG45_IRPTEN45_DIS = 0
, GPIO_PINCFG45_IRPTEN45_INTFALL = 1
, GPIO_PINCFG45_IRPTEN45_INTRISE = 2
, GPIO_PINCFG45_IRPTEN45_INTANY = 3
} |
| |
| enum | GPIO_PINCFG45_FNCSEL45_Enum {
GPIO_PINCFG45_FNCSEL45_MSPI1_8 = 0
, GPIO_PINCFG45_FNCSEL45_TRIG2 = 1
, GPIO_PINCFG45_FNCSEL45_32KHzXT = 2
, GPIO_PINCFG45_FNCSEL45_GPIO = 3
,
GPIO_PINCFG45_FNCSEL45_UART0TX = 4
, GPIO_PINCFG45_FNCSEL45_DISP_D23 = 5
, GPIO_PINCFG45_FNCSEL45_CT45 = 6
, GPIO_PINCFG45_FNCSEL45_NCE45 = 7
,
GPIO_PINCFG45_FNCSEL45_OBSBUS13 = 8
, GPIO_PINCFG45_FNCSEL45_RESERVED9 = 9
, GPIO_PINCFG45_FNCSEL45_RESERVED10 = 10
, GPIO_PINCFG45_FNCSEL45_FPIO = 11
,
GPIO_PINCFG45_FNCSEL45_RESERVED12 = 12
, GPIO_PINCFG45_FNCSEL45_RESERVED13 = 13
, GPIO_PINCFG45_FNCSEL45_RESERVED14 = 14
, GPIO_PINCFG45_FNCSEL45_RESERVED15 = 15
} |
| |
| enum | GPIO_PINCFG46_NCEPOL46_Enum { GPIO_PINCFG46_NCEPOL46_LOW = 0
, GPIO_PINCFG46_NCEPOL46_HIGH = 1
} |
| |
| enum | GPIO_PINCFG46_NCESRC46_Enum {
GPIO_PINCFG46_NCESRC46_IOM0CE0 = 0
, GPIO_PINCFG46_NCESRC46_IOM0CE1 = 1
, GPIO_PINCFG46_NCESRC46_IOM0CE2 = 2
, GPIO_PINCFG46_NCESRC46_IOM0CE3 = 3
,
GPIO_PINCFG46_NCESRC46_IOM1CE0 = 4
, GPIO_PINCFG46_NCESRC46_IOM1CE1 = 5
, GPIO_PINCFG46_NCESRC46_IOM1CE2 = 6
, GPIO_PINCFG46_NCESRC46_IOM1CE3 = 7
,
GPIO_PINCFG46_NCESRC46_IOM2CE0 = 8
, GPIO_PINCFG46_NCESRC46_IOM2CE1 = 9
, GPIO_PINCFG46_NCESRC46_IOM2CE2 = 10
, GPIO_PINCFG46_NCESRC46_IOM2CE3 = 11
,
GPIO_PINCFG46_NCESRC46_IOM3CE0 = 12
, GPIO_PINCFG46_NCESRC46_IOM3CE1 = 13
, GPIO_PINCFG46_NCESRC46_IOM3CE2 = 14
, GPIO_PINCFG46_NCESRC46_IOM3CE3 = 15
,
GPIO_PINCFG46_NCESRC46_IOM4CE0 = 16
, GPIO_PINCFG46_NCESRC46_IOM4CE1 = 17
, GPIO_PINCFG46_NCESRC46_IOM4CE2 = 18
, GPIO_PINCFG46_NCESRC46_IOM4CE3 = 19
,
GPIO_PINCFG46_NCESRC46_IOM5CE0 = 20
, GPIO_PINCFG46_NCESRC46_IOM5CE1 = 21
, GPIO_PINCFG46_NCESRC46_IOM5CE2 = 22
, GPIO_PINCFG46_NCESRC46_IOM5CE3 = 23
,
GPIO_PINCFG46_NCESRC46_IOM6CE0 = 24
, GPIO_PINCFG46_NCESRC46_IOM6CE1 = 25
, GPIO_PINCFG46_NCESRC46_IOM6CE2 = 26
, GPIO_PINCFG46_NCESRC46_IOM6CE3 = 27
,
GPIO_PINCFG46_NCESRC46_IOM7CE0 = 28
, GPIO_PINCFG46_NCESRC46_IOM7CE1 = 29
, GPIO_PINCFG46_NCESRC46_IOM7CE2 = 30
, GPIO_PINCFG46_NCESRC46_IOM7CE3 = 31
,
GPIO_PINCFG46_NCESRC46_MSPI0CEN0 = 32
, GPIO_PINCFG46_NCESRC46_MSPI0CEN1 = 33
, GPIO_PINCFG46_NCESRC46_MSPI1CEN0 = 34
, GPIO_PINCFG46_NCESRC46_MSPI1CEN1 = 35
,
GPIO_PINCFG46_NCESRC46_MSPI2CEN0 = 36
, GPIO_PINCFG46_NCESRC46_MSPI2CEN1 = 37
, GPIO_PINCFG46_NCESRC46_DC_DPI_DE = 38
, GPIO_PINCFG46_NCESRC46_DISP_CONT_CSX = 39
,
GPIO_PINCFG46_NCESRC46_DC_SPI_CS_N = 40
, GPIO_PINCFG46_NCESRC46_DC_QSPI_CS_N = 41
, GPIO_PINCFG46_NCESRC46_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG46_PULLCFG46_Enum {
GPIO_PINCFG46_PULLCFG46_DIS = 0
, GPIO_PINCFG46_PULLCFG46_PD50K = 1
, GPIO_PINCFG46_PULLCFG46_PU15K = 2
, GPIO_PINCFG46_PULLCFG46_PU6K = 3
,
GPIO_PINCFG46_PULLCFG46_PU12K = 4
, GPIO_PINCFG46_PULLCFG46_PU24K = 5
, GPIO_PINCFG46_PULLCFG46_PU50K = 6
, GPIO_PINCFG46_PULLCFG46_PU100K = 7
} |
| |
| enum | GPIO_PINCFG46_DS46_Enum { GPIO_PINCFG46_DS46_0P1X = 0
, GPIO_PINCFG46_DS46_0P5X = 1
, GPIO_PINCFG46_DS46_0P75X = 2
, GPIO_PINCFG46_DS46_1P0X = 3
} |
| |
| enum | GPIO_PINCFG46_OUTCFG46_Enum { GPIO_PINCFG46_OUTCFG46_DIS = 0
, GPIO_PINCFG46_OUTCFG46_PUSHPULL = 1
, GPIO_PINCFG46_OUTCFG46_OD = 2
, GPIO_PINCFG46_OUTCFG46_TS = 3
} |
| |
| enum | GPIO_PINCFG46_IRPTEN46_Enum { GPIO_PINCFG46_IRPTEN46_DIS = 0
, GPIO_PINCFG46_IRPTEN46_INTFALL = 1
, GPIO_PINCFG46_IRPTEN46_INTRISE = 2
, GPIO_PINCFG46_IRPTEN46_INTANY = 3
} |
| |
| enum | GPIO_PINCFG46_FNCSEL46_Enum {
GPIO_PINCFG46_FNCSEL46_MSPI1_9 = 0
, GPIO_PINCFG46_FNCSEL46_TRIG3 = 1
, GPIO_PINCFG46_FNCSEL46_CLKOUT_32M = 2
, GPIO_PINCFG46_FNCSEL46_GPIO = 3
,
GPIO_PINCFG46_FNCSEL46_UART2TX = 4
, GPIO_PINCFG46_FNCSEL46_UART3TX = 5
, GPIO_PINCFG46_FNCSEL46_CT46 = 6
, GPIO_PINCFG46_FNCSEL46_NCE46 = 7
,
GPIO_PINCFG46_FNCSEL46_OBSBUS14 = 8
, GPIO_PINCFG46_FNCSEL46_I2S1_SDIN = 9
, GPIO_PINCFG46_FNCSEL46_I2S0_SDIN = 10
, GPIO_PINCFG46_FNCSEL46_FPIO = 11
,
GPIO_PINCFG46_FNCSEL46_RESERVED12 = 12
, GPIO_PINCFG46_FNCSEL46_RESERVED13 = 13
, GPIO_PINCFG46_FNCSEL46_RESERVED14 = 14
, GPIO_PINCFG46_FNCSEL46_RESERVED15 = 15
} |
| |
| enum | GPIO_PINCFG47_NCEPOL47_Enum { GPIO_PINCFG47_NCEPOL47_LOW = 0
, GPIO_PINCFG47_NCEPOL47_HIGH = 1
} |
| |
| enum | GPIO_PINCFG47_NCESRC47_Enum {
GPIO_PINCFG47_NCESRC47_IOM0CE0 = 0
, GPIO_PINCFG47_NCESRC47_IOM0CE1 = 1
, GPIO_PINCFG47_NCESRC47_IOM0CE2 = 2
, GPIO_PINCFG47_NCESRC47_IOM0CE3 = 3
,
GPIO_PINCFG47_NCESRC47_IOM1CE0 = 4
, GPIO_PINCFG47_NCESRC47_IOM1CE1 = 5
, GPIO_PINCFG47_NCESRC47_IOM1CE2 = 6
, GPIO_PINCFG47_NCESRC47_IOM1CE3 = 7
,
GPIO_PINCFG47_NCESRC47_IOM2CE0 = 8
, GPIO_PINCFG47_NCESRC47_IOM2CE1 = 9
, GPIO_PINCFG47_NCESRC47_IOM2CE2 = 10
, GPIO_PINCFG47_NCESRC47_IOM2CE3 = 11
,
GPIO_PINCFG47_NCESRC47_IOM3CE0 = 12
, GPIO_PINCFG47_NCESRC47_IOM3CE1 = 13
, GPIO_PINCFG47_NCESRC47_IOM3CE2 = 14
, GPIO_PINCFG47_NCESRC47_IOM3CE3 = 15
,
GPIO_PINCFG47_NCESRC47_IOM4CE0 = 16
, GPIO_PINCFG47_NCESRC47_IOM4CE1 = 17
, GPIO_PINCFG47_NCESRC47_IOM4CE2 = 18
, GPIO_PINCFG47_NCESRC47_IOM4CE3 = 19
,
GPIO_PINCFG47_NCESRC47_IOM5CE0 = 20
, GPIO_PINCFG47_NCESRC47_IOM5CE1 = 21
, GPIO_PINCFG47_NCESRC47_IOM5CE2 = 22
, GPIO_PINCFG47_NCESRC47_IOM5CE3 = 23
,
GPIO_PINCFG47_NCESRC47_IOM6CE0 = 24
, GPIO_PINCFG47_NCESRC47_IOM6CE1 = 25
, GPIO_PINCFG47_NCESRC47_IOM6CE2 = 26
, GPIO_PINCFG47_NCESRC47_IOM6CE3 = 27
,
GPIO_PINCFG47_NCESRC47_IOM7CE0 = 28
, GPIO_PINCFG47_NCESRC47_IOM7CE1 = 29
, GPIO_PINCFG47_NCESRC47_IOM7CE2 = 30
, GPIO_PINCFG47_NCESRC47_IOM7CE3 = 31
,
GPIO_PINCFG47_NCESRC47_MSPI0CEN0 = 32
, GPIO_PINCFG47_NCESRC47_MSPI0CEN1 = 33
, GPIO_PINCFG47_NCESRC47_MSPI1CEN0 = 34
, GPIO_PINCFG47_NCESRC47_MSPI1CEN1 = 35
,
GPIO_PINCFG47_NCESRC47_MSPI2CEN0 = 36
, GPIO_PINCFG47_NCESRC47_MSPI2CEN1 = 37
, GPIO_PINCFG47_NCESRC47_DC_DPI_DE = 38
, GPIO_PINCFG47_NCESRC47_DISP_CONT_CSX = 39
,
GPIO_PINCFG47_NCESRC47_DC_SPI_CS_N = 40
, GPIO_PINCFG47_NCESRC47_DC_QSPI_CS_N = 41
, GPIO_PINCFG47_NCESRC47_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG47_PULLCFG47_Enum {
GPIO_PINCFG47_PULLCFG47_DIS = 0
, GPIO_PINCFG47_PULLCFG47_PD50K = 1
, GPIO_PINCFG47_PULLCFG47_PU15K = 2
, GPIO_PINCFG47_PULLCFG47_PU6K = 3
,
GPIO_PINCFG47_PULLCFG47_PU12K = 4
, GPIO_PINCFG47_PULLCFG47_PU24K = 5
, GPIO_PINCFG47_PULLCFG47_PU50K = 6
, GPIO_PINCFG47_PULLCFG47_PU100K = 7
} |
| |
| enum | GPIO_PINCFG47_DS47_Enum { GPIO_PINCFG47_DS47_0P1X = 0
, GPIO_PINCFG47_DS47_0P5X = 1
, GPIO_PINCFG47_DS47_0P75X = 2
, GPIO_PINCFG47_DS47_1P0X = 3
} |
| |
| enum | GPIO_PINCFG47_OUTCFG47_Enum { GPIO_PINCFG47_OUTCFG47_DIS = 0
, GPIO_PINCFG47_OUTCFG47_PUSHPULL = 1
, GPIO_PINCFG47_OUTCFG47_OD = 2
, GPIO_PINCFG47_OUTCFG47_TS = 3
} |
| |
| enum | GPIO_PINCFG47_IRPTEN47_Enum { GPIO_PINCFG47_IRPTEN47_DIS = 0
, GPIO_PINCFG47_IRPTEN47_INTFALL = 1
, GPIO_PINCFG47_IRPTEN47_INTRISE = 2
, GPIO_PINCFG47_IRPTEN47_INTANY = 3
} |
| |
| enum | GPIO_PINCFG47_FNCSEL47_Enum {
GPIO_PINCFG47_FNCSEL47_M5SCL = 0
, GPIO_PINCFG47_FNCSEL47_M5SCK = 1
, GPIO_PINCFG47_FNCSEL47_I2S1_CLK = 2
, GPIO_PINCFG47_FNCSEL47_GPIO = 3
,
GPIO_PINCFG47_FNCSEL47_UART0RX = 4
, GPIO_PINCFG47_FNCSEL47_UART1RX = 5
, GPIO_PINCFG47_FNCSEL47_CT47 = 6
, GPIO_PINCFG47_FNCSEL47_NCE47 = 7
,
GPIO_PINCFG47_FNCSEL47_OBSBUS15 = 8
, GPIO_PINCFG47_FNCSEL47_RESERVED9 = 9
, GPIO_PINCFG47_FNCSEL47_I2S0_CLK = 10
, GPIO_PINCFG47_FNCSEL47_FPIO = 11
,
GPIO_PINCFG47_FNCSEL47_RESERVED12 = 12
, GPIO_PINCFG47_FNCSEL47_RESERVED13 = 13
, GPIO_PINCFG47_FNCSEL47_RESERVED14 = 14
, GPIO_PINCFG47_FNCSEL47_RESERVED15 = 15
} |
| |
| enum | GPIO_PINCFG48_NCEPOL48_Enum { GPIO_PINCFG48_NCEPOL48_LOW = 0
, GPIO_PINCFG48_NCEPOL48_HIGH = 1
} |
| |
| enum | GPIO_PINCFG48_NCESRC48_Enum {
GPIO_PINCFG48_NCESRC48_IOM0CE0 = 0
, GPIO_PINCFG48_NCESRC48_IOM0CE1 = 1
, GPIO_PINCFG48_NCESRC48_IOM0CE2 = 2
, GPIO_PINCFG48_NCESRC48_IOM0CE3 = 3
,
GPIO_PINCFG48_NCESRC48_IOM1CE0 = 4
, GPIO_PINCFG48_NCESRC48_IOM1CE1 = 5
, GPIO_PINCFG48_NCESRC48_IOM1CE2 = 6
, GPIO_PINCFG48_NCESRC48_IOM1CE3 = 7
,
GPIO_PINCFG48_NCESRC48_IOM2CE0 = 8
, GPIO_PINCFG48_NCESRC48_IOM2CE1 = 9
, GPIO_PINCFG48_NCESRC48_IOM2CE2 = 10
, GPIO_PINCFG48_NCESRC48_IOM2CE3 = 11
,
GPIO_PINCFG48_NCESRC48_IOM3CE0 = 12
, GPIO_PINCFG48_NCESRC48_IOM3CE1 = 13
, GPIO_PINCFG48_NCESRC48_IOM3CE2 = 14
, GPIO_PINCFG48_NCESRC48_IOM3CE3 = 15
,
GPIO_PINCFG48_NCESRC48_IOM4CE0 = 16
, GPIO_PINCFG48_NCESRC48_IOM4CE1 = 17
, GPIO_PINCFG48_NCESRC48_IOM4CE2 = 18
, GPIO_PINCFG48_NCESRC48_IOM4CE3 = 19
,
GPIO_PINCFG48_NCESRC48_IOM5CE0 = 20
, GPIO_PINCFG48_NCESRC48_IOM5CE1 = 21
, GPIO_PINCFG48_NCESRC48_IOM5CE2 = 22
, GPIO_PINCFG48_NCESRC48_IOM5CE3 = 23
,
GPIO_PINCFG48_NCESRC48_IOM6CE0 = 24
, GPIO_PINCFG48_NCESRC48_IOM6CE1 = 25
, GPIO_PINCFG48_NCESRC48_IOM6CE2 = 26
, GPIO_PINCFG48_NCESRC48_IOM6CE3 = 27
,
GPIO_PINCFG48_NCESRC48_IOM7CE0 = 28
, GPIO_PINCFG48_NCESRC48_IOM7CE1 = 29
, GPIO_PINCFG48_NCESRC48_IOM7CE2 = 30
, GPIO_PINCFG48_NCESRC48_IOM7CE3 = 31
,
GPIO_PINCFG48_NCESRC48_MSPI0CEN0 = 32
, GPIO_PINCFG48_NCESRC48_MSPI0CEN1 = 33
, GPIO_PINCFG48_NCESRC48_MSPI1CEN0 = 34
, GPIO_PINCFG48_NCESRC48_MSPI1CEN1 = 35
,
GPIO_PINCFG48_NCESRC48_MSPI2CEN0 = 36
, GPIO_PINCFG48_NCESRC48_MSPI2CEN1 = 37
, GPIO_PINCFG48_NCESRC48_DC_DPI_DE = 38
, GPIO_PINCFG48_NCESRC48_DISP_CONT_CSX = 39
,
GPIO_PINCFG48_NCESRC48_DC_SPI_CS_N = 40
, GPIO_PINCFG48_NCESRC48_DC_QSPI_CS_N = 41
, GPIO_PINCFG48_NCESRC48_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG48_PULLCFG48_Enum {
GPIO_PINCFG48_PULLCFG48_DIS = 0
, GPIO_PINCFG48_PULLCFG48_PD50K = 1
, GPIO_PINCFG48_PULLCFG48_PU15K = 2
, GPIO_PINCFG48_PULLCFG48_PU6K = 3
,
GPIO_PINCFG48_PULLCFG48_PU12K = 4
, GPIO_PINCFG48_PULLCFG48_PU24K = 5
, GPIO_PINCFG48_PULLCFG48_PU50K = 6
, GPIO_PINCFG48_PULLCFG48_PU100K = 7
} |
| |
| enum | GPIO_PINCFG48_DS48_Enum { GPIO_PINCFG48_DS48_0P1X = 0
, GPIO_PINCFG48_DS48_0P5X = 1
, GPIO_PINCFG48_DS48_0P75X = 2
, GPIO_PINCFG48_DS48_1P0X = 3
} |
| |
| enum | GPIO_PINCFG48_OUTCFG48_Enum { GPIO_PINCFG48_OUTCFG48_DIS = 0
, GPIO_PINCFG48_OUTCFG48_PUSHPULL = 1
, GPIO_PINCFG48_OUTCFG48_OD = 2
, GPIO_PINCFG48_OUTCFG48_TS = 3
} |
| |
| enum | GPIO_PINCFG48_IRPTEN48_Enum { GPIO_PINCFG48_IRPTEN48_DIS = 0
, GPIO_PINCFG48_IRPTEN48_INTFALL = 1
, GPIO_PINCFG48_IRPTEN48_INTRISE = 2
, GPIO_PINCFG48_IRPTEN48_INTANY = 3
} |
| |
| enum | GPIO_PINCFG48_FNCSEL48_Enum {
GPIO_PINCFG48_FNCSEL48_M5SDAWIR3 = 0
, GPIO_PINCFG48_FNCSEL48_M5MOSI = 1
, GPIO_PINCFG48_FNCSEL48_I2S1_DATA = 2
, GPIO_PINCFG48_FNCSEL48_GPIO = 3
,
GPIO_PINCFG48_FNCSEL48_UART2RX = 4
, GPIO_PINCFG48_FNCSEL48_UART3RX = 5
, GPIO_PINCFG48_FNCSEL48_CT48 = 6
, GPIO_PINCFG48_FNCSEL48_NCE48 = 7
,
GPIO_PINCFG48_FNCSEL48_OBSBUS0 = 8
, GPIO_PINCFG48_FNCSEL48_I2S1_SDOUT = 9
, GPIO_PINCFG48_FNCSEL48_I2S0_SDOUT = 10
, GPIO_PINCFG48_FNCSEL48_FPIO = 11
,
GPIO_PINCFG48_FNCSEL48_RESERVED12 = 12
, GPIO_PINCFG48_FNCSEL48_RESERVED13 = 13
, GPIO_PINCFG48_FNCSEL48_RESERVED14 = 14
, GPIO_PINCFG48_FNCSEL48_RESERVED15 = 15
} |
| |
| enum | GPIO_PINCFG49_NCEPOL49_Enum { GPIO_PINCFG49_NCEPOL49_LOW = 0
, GPIO_PINCFG49_NCEPOL49_HIGH = 1
} |
| |
| enum | GPIO_PINCFG49_NCESRC49_Enum {
GPIO_PINCFG49_NCESRC49_IOM0CE0 = 0
, GPIO_PINCFG49_NCESRC49_IOM0CE1 = 1
, GPIO_PINCFG49_NCESRC49_IOM0CE2 = 2
, GPIO_PINCFG49_NCESRC49_IOM0CE3 = 3
,
GPIO_PINCFG49_NCESRC49_IOM1CE0 = 4
, GPIO_PINCFG49_NCESRC49_IOM1CE1 = 5
, GPIO_PINCFG49_NCESRC49_IOM1CE2 = 6
, GPIO_PINCFG49_NCESRC49_IOM1CE3 = 7
,
GPIO_PINCFG49_NCESRC49_IOM2CE0 = 8
, GPIO_PINCFG49_NCESRC49_IOM2CE1 = 9
, GPIO_PINCFG49_NCESRC49_IOM2CE2 = 10
, GPIO_PINCFG49_NCESRC49_IOM2CE3 = 11
,
GPIO_PINCFG49_NCESRC49_IOM3CE0 = 12
, GPIO_PINCFG49_NCESRC49_IOM3CE1 = 13
, GPIO_PINCFG49_NCESRC49_IOM3CE2 = 14
, GPIO_PINCFG49_NCESRC49_IOM3CE3 = 15
,
GPIO_PINCFG49_NCESRC49_IOM4CE0 = 16
, GPIO_PINCFG49_NCESRC49_IOM4CE1 = 17
, GPIO_PINCFG49_NCESRC49_IOM4CE2 = 18
, GPIO_PINCFG49_NCESRC49_IOM4CE3 = 19
,
GPIO_PINCFG49_NCESRC49_IOM5CE0 = 20
, GPIO_PINCFG49_NCESRC49_IOM5CE1 = 21
, GPIO_PINCFG49_NCESRC49_IOM5CE2 = 22
, GPIO_PINCFG49_NCESRC49_IOM5CE3 = 23
,
GPIO_PINCFG49_NCESRC49_IOM6CE0 = 24
, GPIO_PINCFG49_NCESRC49_IOM6CE1 = 25
, GPIO_PINCFG49_NCESRC49_IOM6CE2 = 26
, GPIO_PINCFG49_NCESRC49_IOM6CE3 = 27
,
GPIO_PINCFG49_NCESRC49_IOM7CE0 = 28
, GPIO_PINCFG49_NCESRC49_IOM7CE1 = 29
, GPIO_PINCFG49_NCESRC49_IOM7CE2 = 30
, GPIO_PINCFG49_NCESRC49_IOM7CE3 = 31
,
GPIO_PINCFG49_NCESRC49_MSPI0CEN0 = 32
, GPIO_PINCFG49_NCESRC49_MSPI0CEN1 = 33
, GPIO_PINCFG49_NCESRC49_MSPI1CEN0 = 34
, GPIO_PINCFG49_NCESRC49_MSPI1CEN1 = 35
,
GPIO_PINCFG49_NCESRC49_MSPI2CEN0 = 36
, GPIO_PINCFG49_NCESRC49_MSPI2CEN1 = 37
, GPIO_PINCFG49_NCESRC49_DC_DPI_DE = 38
, GPIO_PINCFG49_NCESRC49_DISP_CONT_CSX = 39
,
GPIO_PINCFG49_NCESRC49_DC_SPI_CS_N = 40
, GPIO_PINCFG49_NCESRC49_DC_QSPI_CS_N = 41
, GPIO_PINCFG49_NCESRC49_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG49_PULLCFG49_Enum {
GPIO_PINCFG49_PULLCFG49_DIS = 0
, GPIO_PINCFG49_PULLCFG49_PD50K = 1
, GPIO_PINCFG49_PULLCFG49_PU15K = 2
, GPIO_PINCFG49_PULLCFG49_PU6K = 3
,
GPIO_PINCFG49_PULLCFG49_PU12K = 4
, GPIO_PINCFG49_PULLCFG49_PU24K = 5
, GPIO_PINCFG49_PULLCFG49_PU50K = 6
, GPIO_PINCFG49_PULLCFG49_PU100K = 7
} |
| |
| enum | GPIO_PINCFG49_DS49_Enum { GPIO_PINCFG49_DS49_0P1X = 0
, GPIO_PINCFG49_DS49_0P5X = 1
, GPIO_PINCFG49_DS49_0P75X = 2
, GPIO_PINCFG49_DS49_1P0X = 3
} |
| |
| enum | GPIO_PINCFG49_OUTCFG49_Enum { GPIO_PINCFG49_OUTCFG49_DIS = 0
, GPIO_PINCFG49_OUTCFG49_PUSHPULL = 1
, GPIO_PINCFG49_OUTCFG49_OD = 2
, GPIO_PINCFG49_OUTCFG49_TS = 3
} |
| |
| enum | GPIO_PINCFG49_IRPTEN49_Enum { GPIO_PINCFG49_IRPTEN49_DIS = 0
, GPIO_PINCFG49_IRPTEN49_INTFALL = 1
, GPIO_PINCFG49_IRPTEN49_INTRISE = 2
, GPIO_PINCFG49_IRPTEN49_INTANY = 3
} |
| |
| enum | GPIO_PINCFG49_FNCSEL49_Enum {
GPIO_PINCFG49_FNCSEL49_M5MISO = 0
, GPIO_PINCFG49_FNCSEL49_TRIG0 = 1
, GPIO_PINCFG49_FNCSEL49_I2S1_WS = 2
, GPIO_PINCFG49_FNCSEL49_GPIO = 3
,
GPIO_PINCFG49_FNCSEL49_UART0RTS = 4
, GPIO_PINCFG49_FNCSEL49_UART1RTS = 5
, GPIO_PINCFG49_FNCSEL49_CT49 = 6
, GPIO_PINCFG49_FNCSEL49_NCE49 = 7
,
GPIO_PINCFG49_FNCSEL49_OBSBUS1 = 8
, GPIO_PINCFG49_FNCSEL49_RESERVED9 = 9
, GPIO_PINCFG49_FNCSEL49_I2S0_WS = 10
, GPIO_PINCFG49_FNCSEL49_FPIO = 11
,
GPIO_PINCFG49_FNCSEL49_RESERVED12 = 12
, GPIO_PINCFG49_FNCSEL49_RESERVED13 = 13
, GPIO_PINCFG49_FNCSEL49_RESERVED14 = 14
, GPIO_PINCFG49_FNCSEL49_RESERVED15 = 15
} |
| |
| enum | GPIO_PINCFG50_NCEPOL50_Enum { GPIO_PINCFG50_NCEPOL50_LOW = 0
, GPIO_PINCFG50_NCEPOL50_HIGH = 1
} |
| |
| enum | GPIO_PINCFG50_NCESRC50_Enum {
GPIO_PINCFG50_NCESRC50_IOM0CE0 = 0
, GPIO_PINCFG50_NCESRC50_IOM0CE1 = 1
, GPIO_PINCFG50_NCESRC50_IOM0CE2 = 2
, GPIO_PINCFG50_NCESRC50_IOM0CE3 = 3
,
GPIO_PINCFG50_NCESRC50_IOM1CE0 = 4
, GPIO_PINCFG50_NCESRC50_IOM1CE1 = 5
, GPIO_PINCFG50_NCESRC50_IOM1CE2 = 6
, GPIO_PINCFG50_NCESRC50_IOM1CE3 = 7
,
GPIO_PINCFG50_NCESRC50_IOM2CE0 = 8
, GPIO_PINCFG50_NCESRC50_IOM2CE1 = 9
, GPIO_PINCFG50_NCESRC50_IOM2CE2 = 10
, GPIO_PINCFG50_NCESRC50_IOM2CE3 = 11
,
GPIO_PINCFG50_NCESRC50_IOM3CE0 = 12
, GPIO_PINCFG50_NCESRC50_IOM3CE1 = 13
, GPIO_PINCFG50_NCESRC50_IOM3CE2 = 14
, GPIO_PINCFG50_NCESRC50_IOM3CE3 = 15
,
GPIO_PINCFG50_NCESRC50_IOM4CE0 = 16
, GPIO_PINCFG50_NCESRC50_IOM4CE1 = 17
, GPIO_PINCFG50_NCESRC50_IOM4CE2 = 18
, GPIO_PINCFG50_NCESRC50_IOM4CE3 = 19
,
GPIO_PINCFG50_NCESRC50_IOM5CE0 = 20
, GPIO_PINCFG50_NCESRC50_IOM5CE1 = 21
, GPIO_PINCFG50_NCESRC50_IOM5CE2 = 22
, GPIO_PINCFG50_NCESRC50_IOM5CE3 = 23
,
GPIO_PINCFG50_NCESRC50_IOM6CE0 = 24
, GPIO_PINCFG50_NCESRC50_IOM6CE1 = 25
, GPIO_PINCFG50_NCESRC50_IOM6CE2 = 26
, GPIO_PINCFG50_NCESRC50_IOM6CE3 = 27
,
GPIO_PINCFG50_NCESRC50_IOM7CE0 = 28
, GPIO_PINCFG50_NCESRC50_IOM7CE1 = 29
, GPIO_PINCFG50_NCESRC50_IOM7CE2 = 30
, GPIO_PINCFG50_NCESRC50_IOM7CE3 = 31
,
GPIO_PINCFG50_NCESRC50_MSPI0CEN0 = 32
, GPIO_PINCFG50_NCESRC50_MSPI0CEN1 = 33
, GPIO_PINCFG50_NCESRC50_MSPI1CEN0 = 34
, GPIO_PINCFG50_NCESRC50_MSPI1CEN1 = 35
,
GPIO_PINCFG50_NCESRC50_MSPI2CEN0 = 36
, GPIO_PINCFG50_NCESRC50_MSPI2CEN1 = 37
, GPIO_PINCFG50_NCESRC50_DC_DPI_DE = 38
, GPIO_PINCFG50_NCESRC50_DISP_CONT_CSX = 39
,
GPIO_PINCFG50_NCESRC50_DC_SPI_CS_N = 40
, GPIO_PINCFG50_NCESRC50_DC_QSPI_CS_N = 41
, GPIO_PINCFG50_NCESRC50_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG50_PULLCFG50_Enum {
GPIO_PINCFG50_PULLCFG50_DIS = 0
, GPIO_PINCFG50_PULLCFG50_PD50K = 1
, GPIO_PINCFG50_PULLCFG50_PU15K = 2
, GPIO_PINCFG50_PULLCFG50_PU6K = 3
,
GPIO_PINCFG50_PULLCFG50_PU12K = 4
, GPIO_PINCFG50_PULLCFG50_PU24K = 5
, GPIO_PINCFG50_PULLCFG50_PU50K = 6
, GPIO_PINCFG50_PULLCFG50_PU100K = 7
} |
| |
| enum | GPIO_PINCFG50_DS50_Enum { GPIO_PINCFG50_DS50_0P1X = 0
, GPIO_PINCFG50_DS50_0P5X = 1
} |
| |
| enum | GPIO_PINCFG50_OUTCFG50_Enum { GPIO_PINCFG50_OUTCFG50_DIS = 0
, GPIO_PINCFG50_OUTCFG50_PUSHPULL = 1
, GPIO_PINCFG50_OUTCFG50_OD = 2
, GPIO_PINCFG50_OUTCFG50_TS = 3
} |
| |
| enum | GPIO_PINCFG50_IRPTEN50_Enum { GPIO_PINCFG50_IRPTEN50_DIS = 0
, GPIO_PINCFG50_IRPTEN50_INTFALL = 1
, GPIO_PINCFG50_IRPTEN50_INTRISE = 2
, GPIO_PINCFG50_IRPTEN50_INTANY = 3
} |
| |
| enum | GPIO_PINCFG50_FNCSEL50_Enum {
GPIO_PINCFG50_FNCSEL50_PDM0_CLK = 0
, GPIO_PINCFG50_FNCSEL50_TRIG0 = 1
, GPIO_PINCFG50_FNCSEL50_SWTRACECLK = 2
, GPIO_PINCFG50_FNCSEL50_GPIO = 3
,
GPIO_PINCFG50_FNCSEL50_UART2RTS = 4
, GPIO_PINCFG50_FNCSEL50_UART3RTS = 5
, GPIO_PINCFG50_FNCSEL50_CT50 = 6
, GPIO_PINCFG50_FNCSEL50_NCE50 = 7
,
GPIO_PINCFG50_FNCSEL50_OBSBUS2 = 8
, GPIO_PINCFG50_FNCSEL50_DISP_TE = 9
, GPIO_PINCFG50_FNCSEL50_RESERVED10 = 10
, GPIO_PINCFG50_FNCSEL50_FPIO = 11
,
GPIO_PINCFG50_FNCSEL50_RESERVED12 = 12
, GPIO_PINCFG50_FNCSEL50_RESERVED13 = 13
, GPIO_PINCFG50_FNCSEL50_RESERVED14 = 14
, GPIO_PINCFG50_FNCSEL50_RESERVED15 = 15
} |
| |
| enum | GPIO_PINCFG51_NCEPOL51_Enum { GPIO_PINCFG51_NCEPOL51_LOW = 0
, GPIO_PINCFG51_NCEPOL51_HIGH = 1
} |
| |
| enum | GPIO_PINCFG51_NCESRC51_Enum {
GPIO_PINCFG51_NCESRC51_IOM0CE0 = 0
, GPIO_PINCFG51_NCESRC51_IOM0CE1 = 1
, GPIO_PINCFG51_NCESRC51_IOM0CE2 = 2
, GPIO_PINCFG51_NCESRC51_IOM0CE3 = 3
,
GPIO_PINCFG51_NCESRC51_IOM1CE0 = 4
, GPIO_PINCFG51_NCESRC51_IOM1CE1 = 5
, GPIO_PINCFG51_NCESRC51_IOM1CE2 = 6
, GPIO_PINCFG51_NCESRC51_IOM1CE3 = 7
,
GPIO_PINCFG51_NCESRC51_IOM2CE0 = 8
, GPIO_PINCFG51_NCESRC51_IOM2CE1 = 9
, GPIO_PINCFG51_NCESRC51_IOM2CE2 = 10
, GPIO_PINCFG51_NCESRC51_IOM2CE3 = 11
,
GPIO_PINCFG51_NCESRC51_IOM3CE0 = 12
, GPIO_PINCFG51_NCESRC51_IOM3CE1 = 13
, GPIO_PINCFG51_NCESRC51_IOM3CE2 = 14
, GPIO_PINCFG51_NCESRC51_IOM3CE3 = 15
,
GPIO_PINCFG51_NCESRC51_IOM4CE0 = 16
, GPIO_PINCFG51_NCESRC51_IOM4CE1 = 17
, GPIO_PINCFG51_NCESRC51_IOM4CE2 = 18
, GPIO_PINCFG51_NCESRC51_IOM4CE3 = 19
,
GPIO_PINCFG51_NCESRC51_IOM5CE0 = 20
, GPIO_PINCFG51_NCESRC51_IOM5CE1 = 21
, GPIO_PINCFG51_NCESRC51_IOM5CE2 = 22
, GPIO_PINCFG51_NCESRC51_IOM5CE3 = 23
,
GPIO_PINCFG51_NCESRC51_IOM6CE0 = 24
, GPIO_PINCFG51_NCESRC51_IOM6CE1 = 25
, GPIO_PINCFG51_NCESRC51_IOM6CE2 = 26
, GPIO_PINCFG51_NCESRC51_IOM6CE3 = 27
,
GPIO_PINCFG51_NCESRC51_IOM7CE0 = 28
, GPIO_PINCFG51_NCESRC51_IOM7CE1 = 29
, GPIO_PINCFG51_NCESRC51_IOM7CE2 = 30
, GPIO_PINCFG51_NCESRC51_IOM7CE3 = 31
,
GPIO_PINCFG51_NCESRC51_MSPI0CEN0 = 32
, GPIO_PINCFG51_NCESRC51_MSPI0CEN1 = 33
, GPIO_PINCFG51_NCESRC51_MSPI1CEN0 = 34
, GPIO_PINCFG51_NCESRC51_MSPI1CEN1 = 35
,
GPIO_PINCFG51_NCESRC51_MSPI2CEN0 = 36
, GPIO_PINCFG51_NCESRC51_MSPI2CEN1 = 37
, GPIO_PINCFG51_NCESRC51_DC_DPI_DE = 38
, GPIO_PINCFG51_NCESRC51_DISP_CONT_CSX = 39
,
GPIO_PINCFG51_NCESRC51_DC_SPI_CS_N = 40
, GPIO_PINCFG51_NCESRC51_DC_QSPI_CS_N = 41
, GPIO_PINCFG51_NCESRC51_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG51_PULLCFG51_Enum {
GPIO_PINCFG51_PULLCFG51_DIS = 0
, GPIO_PINCFG51_PULLCFG51_PD50K = 1
, GPIO_PINCFG51_PULLCFG51_PU15K = 2
, GPIO_PINCFG51_PULLCFG51_PU6K = 3
,
GPIO_PINCFG51_PULLCFG51_PU12K = 4
, GPIO_PINCFG51_PULLCFG51_PU24K = 5
, GPIO_PINCFG51_PULLCFG51_PU50K = 6
, GPIO_PINCFG51_PULLCFG51_PU100K = 7
} |
| |
| enum | GPIO_PINCFG51_DS51_Enum { GPIO_PINCFG51_DS51_0P1X = 0
, GPIO_PINCFG51_DS51_0P5X = 1
, GPIO_PINCFG51_DS51_0P75X = 2
, GPIO_PINCFG51_DS51_1P0X = 3
} |
| |
| enum | GPIO_PINCFG51_OUTCFG51_Enum { GPIO_PINCFG51_OUTCFG51_DIS = 0
, GPIO_PINCFG51_OUTCFG51_PUSHPULL = 1
, GPIO_PINCFG51_OUTCFG51_OD = 2
, GPIO_PINCFG51_OUTCFG51_TS = 3
} |
| |
| enum | GPIO_PINCFG51_IRPTEN51_Enum { GPIO_PINCFG51_IRPTEN51_DIS = 0
, GPIO_PINCFG51_IRPTEN51_INTFALL = 1
, GPIO_PINCFG51_IRPTEN51_INTRISE = 2
, GPIO_PINCFG51_IRPTEN51_INTANY = 3
} |
| |
| enum | GPIO_PINCFG51_FNCSEL51_Enum {
GPIO_PINCFG51_FNCSEL51_PDM0_DATA = 0
, GPIO_PINCFG51_FNCSEL51_TRIG1 = 1
, GPIO_PINCFG51_FNCSEL51_SWTRACE0 = 2
, GPIO_PINCFG51_FNCSEL51_GPIO = 3
,
GPIO_PINCFG51_FNCSEL51_UART0CTS = 4
, GPIO_PINCFG51_FNCSEL51_UART1CTS = 5
, GPIO_PINCFG51_FNCSEL51_CT51 = 6
, GPIO_PINCFG51_FNCSEL51_NCE51 = 7
,
GPIO_PINCFG51_FNCSEL51_OBSBUS3 = 8
, GPIO_PINCFG51_FNCSEL51_RESERVED9 = 9
, GPIO_PINCFG51_FNCSEL51_RESERVED10 = 10
, GPIO_PINCFG51_FNCSEL51_FPIO = 11
,
GPIO_PINCFG51_FNCSEL51_RESERVED12 = 12
, GPIO_PINCFG51_FNCSEL51_RESERVED13 = 13
, GPIO_PINCFG51_FNCSEL51_RESERVED14 = 14
, GPIO_PINCFG51_FNCSEL51_RESERVED15 = 15
} |
| |
| enum | GPIO_PINCFG52_NCEPOL52_Enum { GPIO_PINCFG52_NCEPOL52_LOW = 0
, GPIO_PINCFG52_NCEPOL52_HIGH = 1
} |
| |
| enum | GPIO_PINCFG52_NCESRC52_Enum {
GPIO_PINCFG52_NCESRC52_IOM0CE0 = 0
, GPIO_PINCFG52_NCESRC52_IOM0CE1 = 1
, GPIO_PINCFG52_NCESRC52_IOM0CE2 = 2
, GPIO_PINCFG52_NCESRC52_IOM0CE3 = 3
,
GPIO_PINCFG52_NCESRC52_IOM1CE0 = 4
, GPIO_PINCFG52_NCESRC52_IOM1CE1 = 5
, GPIO_PINCFG52_NCESRC52_IOM1CE2 = 6
, GPIO_PINCFG52_NCESRC52_IOM1CE3 = 7
,
GPIO_PINCFG52_NCESRC52_IOM2CE0 = 8
, GPIO_PINCFG52_NCESRC52_IOM2CE1 = 9
, GPIO_PINCFG52_NCESRC52_IOM2CE2 = 10
, GPIO_PINCFG52_NCESRC52_IOM2CE3 = 11
,
GPIO_PINCFG52_NCESRC52_IOM3CE0 = 12
, GPIO_PINCFG52_NCESRC52_IOM3CE1 = 13
, GPIO_PINCFG52_NCESRC52_IOM3CE2 = 14
, GPIO_PINCFG52_NCESRC52_IOM3CE3 = 15
,
GPIO_PINCFG52_NCESRC52_IOM4CE0 = 16
, GPIO_PINCFG52_NCESRC52_IOM4CE1 = 17
, GPIO_PINCFG52_NCESRC52_IOM4CE2 = 18
, GPIO_PINCFG52_NCESRC52_IOM4CE3 = 19
,
GPIO_PINCFG52_NCESRC52_IOM5CE0 = 20
, GPIO_PINCFG52_NCESRC52_IOM5CE1 = 21
, GPIO_PINCFG52_NCESRC52_IOM5CE2 = 22
, GPIO_PINCFG52_NCESRC52_IOM5CE3 = 23
,
GPIO_PINCFG52_NCESRC52_IOM6CE0 = 24
, GPIO_PINCFG52_NCESRC52_IOM6CE1 = 25
, GPIO_PINCFG52_NCESRC52_IOM6CE2 = 26
, GPIO_PINCFG52_NCESRC52_IOM6CE3 = 27
,
GPIO_PINCFG52_NCESRC52_IOM7CE0 = 28
, GPIO_PINCFG52_NCESRC52_IOM7CE1 = 29
, GPIO_PINCFG52_NCESRC52_IOM7CE2 = 30
, GPIO_PINCFG52_NCESRC52_IOM7CE3 = 31
,
GPIO_PINCFG52_NCESRC52_MSPI0CEN0 = 32
, GPIO_PINCFG52_NCESRC52_MSPI0CEN1 = 33
, GPIO_PINCFG52_NCESRC52_MSPI1CEN0 = 34
, GPIO_PINCFG52_NCESRC52_MSPI1CEN1 = 35
,
GPIO_PINCFG52_NCESRC52_MSPI2CEN0 = 36
, GPIO_PINCFG52_NCESRC52_MSPI2CEN1 = 37
, GPIO_PINCFG52_NCESRC52_DC_DPI_DE = 38
, GPIO_PINCFG52_NCESRC52_DISP_CONT_CSX = 39
,
GPIO_PINCFG52_NCESRC52_DC_SPI_CS_N = 40
, GPIO_PINCFG52_NCESRC52_DC_QSPI_CS_N = 41
, GPIO_PINCFG52_NCESRC52_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG52_PULLCFG52_Enum {
GPIO_PINCFG52_PULLCFG52_DIS = 0
, GPIO_PINCFG52_PULLCFG52_PD50K = 1
, GPIO_PINCFG52_PULLCFG52_PU15K = 2
, GPIO_PINCFG52_PULLCFG52_PU6K = 3
,
GPIO_PINCFG52_PULLCFG52_PU12K = 4
, GPIO_PINCFG52_PULLCFG52_PU24K = 5
, GPIO_PINCFG52_PULLCFG52_PU50K = 6
, GPIO_PINCFG52_PULLCFG52_PU100K = 7
} |
| |
| enum | GPIO_PINCFG52_DS52_Enum { GPIO_PINCFG52_DS52_0P1X = 0
, GPIO_PINCFG52_DS52_0P5X = 1
, GPIO_PINCFG52_DS52_0P75X = 2
, GPIO_PINCFG52_DS52_1P0X = 3
} |
| |
| enum | GPIO_PINCFG52_OUTCFG52_Enum { GPIO_PINCFG52_OUTCFG52_DIS = 0
, GPIO_PINCFG52_OUTCFG52_PUSHPULL = 1
, GPIO_PINCFG52_OUTCFG52_OD = 2
, GPIO_PINCFG52_OUTCFG52_TS = 3
} |
| |
| enum | GPIO_PINCFG52_IRPTEN52_Enum { GPIO_PINCFG52_IRPTEN52_DIS = 0
, GPIO_PINCFG52_IRPTEN52_INTFALL = 1
, GPIO_PINCFG52_IRPTEN52_INTRISE = 2
, GPIO_PINCFG52_IRPTEN52_INTANY = 3
} |
| |
| enum | GPIO_PINCFG52_FNCSEL52_Enum {
GPIO_PINCFG52_FNCSEL52_PDM1_CLK = 0
, GPIO_PINCFG52_FNCSEL52_TRIG2 = 1
, GPIO_PINCFG52_FNCSEL52_SWTRACE1 = 2
, GPIO_PINCFG52_FNCSEL52_GPIO = 3
,
GPIO_PINCFG52_FNCSEL52_UART2CTS = 4
, GPIO_PINCFG52_FNCSEL52_UART3CTS = 5
, GPIO_PINCFG52_FNCSEL52_CT52 = 6
, GPIO_PINCFG52_FNCSEL52_NCE52 = 7
,
GPIO_PINCFG52_FNCSEL52_OBSBUS4 = 8
, GPIO_PINCFG52_FNCSEL52_VCMPO = 9
, GPIO_PINCFG52_FNCSEL52_RESERVED10 = 10
, GPIO_PINCFG52_FNCSEL52_FPIO = 11
,
GPIO_PINCFG52_FNCSEL52_RESERVED12 = 12
, GPIO_PINCFG52_FNCSEL52_RESERVED13 = 13
, GPIO_PINCFG52_FNCSEL52_RESERVED14 = 14
, GPIO_PINCFG52_FNCSEL52_RESERVED15 = 15
} |
| |
| enum | GPIO_PINCFG53_NCEPOL53_Enum { GPIO_PINCFG53_NCEPOL53_LOW = 0
, GPIO_PINCFG53_NCEPOL53_HIGH = 1
} |
| |
| enum | GPIO_PINCFG53_NCESRC53_Enum {
GPIO_PINCFG53_NCESRC53_IOM0CE0 = 0
, GPIO_PINCFG53_NCESRC53_IOM0CE1 = 1
, GPIO_PINCFG53_NCESRC53_IOM0CE2 = 2
, GPIO_PINCFG53_NCESRC53_IOM0CE3 = 3
,
GPIO_PINCFG53_NCESRC53_IOM1CE0 = 4
, GPIO_PINCFG53_NCESRC53_IOM1CE1 = 5
, GPIO_PINCFG53_NCESRC53_IOM1CE2 = 6
, GPIO_PINCFG53_NCESRC53_IOM1CE3 = 7
,
GPIO_PINCFG53_NCESRC53_IOM2CE0 = 8
, GPIO_PINCFG53_NCESRC53_IOM2CE1 = 9
, GPIO_PINCFG53_NCESRC53_IOM2CE2 = 10
, GPIO_PINCFG53_NCESRC53_IOM2CE3 = 11
,
GPIO_PINCFG53_NCESRC53_IOM3CE0 = 12
, GPIO_PINCFG53_NCESRC53_IOM3CE1 = 13
, GPIO_PINCFG53_NCESRC53_IOM3CE2 = 14
, GPIO_PINCFG53_NCESRC53_IOM3CE3 = 15
,
GPIO_PINCFG53_NCESRC53_IOM4CE0 = 16
, GPIO_PINCFG53_NCESRC53_IOM4CE1 = 17
, GPIO_PINCFG53_NCESRC53_IOM4CE2 = 18
, GPIO_PINCFG53_NCESRC53_IOM4CE3 = 19
,
GPIO_PINCFG53_NCESRC53_IOM5CE0 = 20
, GPIO_PINCFG53_NCESRC53_IOM5CE1 = 21
, GPIO_PINCFG53_NCESRC53_IOM5CE2 = 22
, GPIO_PINCFG53_NCESRC53_IOM5CE3 = 23
,
GPIO_PINCFG53_NCESRC53_IOM6CE0 = 24
, GPIO_PINCFG53_NCESRC53_IOM6CE1 = 25
, GPIO_PINCFG53_NCESRC53_IOM6CE2 = 26
, GPIO_PINCFG53_NCESRC53_IOM6CE3 = 27
,
GPIO_PINCFG53_NCESRC53_IOM7CE0 = 28
, GPIO_PINCFG53_NCESRC53_IOM7CE1 = 29
, GPIO_PINCFG53_NCESRC53_IOM7CE2 = 30
, GPIO_PINCFG53_NCESRC53_IOM7CE3 = 31
,
GPIO_PINCFG53_NCESRC53_MSPI0CEN0 = 32
, GPIO_PINCFG53_NCESRC53_MSPI0CEN1 = 33
, GPIO_PINCFG53_NCESRC53_MSPI1CEN0 = 34
, GPIO_PINCFG53_NCESRC53_MSPI1CEN1 = 35
,
GPIO_PINCFG53_NCESRC53_MSPI2CEN0 = 36
, GPIO_PINCFG53_NCESRC53_MSPI2CEN1 = 37
, GPIO_PINCFG53_NCESRC53_DC_DPI_DE = 38
, GPIO_PINCFG53_NCESRC53_DISP_CONT_CSX = 39
,
GPIO_PINCFG53_NCESRC53_DC_SPI_CS_N = 40
, GPIO_PINCFG53_NCESRC53_DC_QSPI_CS_N = 41
, GPIO_PINCFG53_NCESRC53_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG53_PULLCFG53_Enum {
GPIO_PINCFG53_PULLCFG53_DIS = 0
, GPIO_PINCFG53_PULLCFG53_PD50K = 1
, GPIO_PINCFG53_PULLCFG53_PU15K = 2
, GPIO_PINCFG53_PULLCFG53_PU6K = 3
,
GPIO_PINCFG53_PULLCFG53_PU12K = 4
, GPIO_PINCFG53_PULLCFG53_PU24K = 5
, GPIO_PINCFG53_PULLCFG53_PU50K = 6
, GPIO_PINCFG53_PULLCFG53_PU100K = 7
} |
| |
| enum | GPIO_PINCFG53_DS53_Enum { GPIO_PINCFG53_DS53_0P1X = 0
, GPIO_PINCFG53_DS53_0P5X = 1
, GPIO_PINCFG53_DS53_0P75X = 2
, GPIO_PINCFG53_DS53_1P0X = 3
} |
| |
| enum | GPIO_PINCFG53_OUTCFG53_Enum { GPIO_PINCFG53_OUTCFG53_DIS = 0
, GPIO_PINCFG53_OUTCFG53_PUSHPULL = 1
, GPIO_PINCFG53_OUTCFG53_OD = 2
, GPIO_PINCFG53_OUTCFG53_TS = 3
} |
| |
| enum | GPIO_PINCFG53_IRPTEN53_Enum { GPIO_PINCFG53_IRPTEN53_DIS = 0
, GPIO_PINCFG53_IRPTEN53_INTFALL = 1
, GPIO_PINCFG53_IRPTEN53_INTRISE = 2
, GPIO_PINCFG53_IRPTEN53_INTANY = 3
} |
| |
| enum | GPIO_PINCFG53_FNCSEL53_Enum {
GPIO_PINCFG53_FNCSEL53_PDM1_DATA = 0
, GPIO_PINCFG53_FNCSEL53_TRIG3 = 1
, GPIO_PINCFG53_FNCSEL53_SWTRACE2 = 2
, GPIO_PINCFG53_FNCSEL53_GPIO = 3
,
GPIO_PINCFG53_FNCSEL53_UART0TX = 4
, GPIO_PINCFG53_FNCSEL53_UART1TX = 5
, GPIO_PINCFG53_FNCSEL53_CT53 = 6
, GPIO_PINCFG53_FNCSEL53_NCE53 = 7
,
GPIO_PINCFG53_FNCSEL53_OBSBUS5 = 8
, GPIO_PINCFG53_FNCSEL53_RESERVED9 = 9
, GPIO_PINCFG53_FNCSEL53_RESERVED10 = 10
, GPIO_PINCFG53_FNCSEL53_FPIO = 11
,
GPIO_PINCFG53_FNCSEL53_RESERVED12 = 12
, GPIO_PINCFG53_FNCSEL53_RESERVED13 = 13
, GPIO_PINCFG53_FNCSEL53_RESERVED14 = 14
, GPIO_PINCFG53_FNCSEL53_RESERVED15 = 15
} |
| |
| enum | GPIO_PINCFG54_NCEPOL54_Enum { GPIO_PINCFG54_NCEPOL54_LOW = 0
, GPIO_PINCFG54_NCEPOL54_HIGH = 1
} |
| |
| enum | GPIO_PINCFG54_NCESRC54_Enum {
GPIO_PINCFG54_NCESRC54_IOM0CE0 = 0
, GPIO_PINCFG54_NCESRC54_IOM0CE1 = 1
, GPIO_PINCFG54_NCESRC54_IOM0CE2 = 2
, GPIO_PINCFG54_NCESRC54_IOM0CE3 = 3
,
GPIO_PINCFG54_NCESRC54_IOM1CE0 = 4
, GPIO_PINCFG54_NCESRC54_IOM1CE1 = 5
, GPIO_PINCFG54_NCESRC54_IOM1CE2 = 6
, GPIO_PINCFG54_NCESRC54_IOM1CE3 = 7
,
GPIO_PINCFG54_NCESRC54_IOM2CE0 = 8
, GPIO_PINCFG54_NCESRC54_IOM2CE1 = 9
, GPIO_PINCFG54_NCESRC54_IOM2CE2 = 10
, GPIO_PINCFG54_NCESRC54_IOM2CE3 = 11
,
GPIO_PINCFG54_NCESRC54_IOM3CE0 = 12
, GPIO_PINCFG54_NCESRC54_IOM3CE1 = 13
, GPIO_PINCFG54_NCESRC54_IOM3CE2 = 14
, GPIO_PINCFG54_NCESRC54_IOM3CE3 = 15
,
GPIO_PINCFG54_NCESRC54_IOM4CE0 = 16
, GPIO_PINCFG54_NCESRC54_IOM4CE1 = 17
, GPIO_PINCFG54_NCESRC54_IOM4CE2 = 18
, GPIO_PINCFG54_NCESRC54_IOM4CE3 = 19
,
GPIO_PINCFG54_NCESRC54_IOM5CE0 = 20
, GPIO_PINCFG54_NCESRC54_IOM5CE1 = 21
, GPIO_PINCFG54_NCESRC54_IOM5CE2 = 22
, GPIO_PINCFG54_NCESRC54_IOM5CE3 = 23
,
GPIO_PINCFG54_NCESRC54_IOM6CE0 = 24
, GPIO_PINCFG54_NCESRC54_IOM6CE1 = 25
, GPIO_PINCFG54_NCESRC54_IOM6CE2 = 26
, GPIO_PINCFG54_NCESRC54_IOM6CE3 = 27
,
GPIO_PINCFG54_NCESRC54_IOM7CE0 = 28
, GPIO_PINCFG54_NCESRC54_IOM7CE1 = 29
, GPIO_PINCFG54_NCESRC54_IOM7CE2 = 30
, GPIO_PINCFG54_NCESRC54_IOM7CE3 = 31
,
GPIO_PINCFG54_NCESRC54_MSPI0CEN0 = 32
, GPIO_PINCFG54_NCESRC54_MSPI0CEN1 = 33
, GPIO_PINCFG54_NCESRC54_MSPI1CEN0 = 34
, GPIO_PINCFG54_NCESRC54_MSPI1CEN1 = 35
,
GPIO_PINCFG54_NCESRC54_MSPI2CEN0 = 36
, GPIO_PINCFG54_NCESRC54_MSPI2CEN1 = 37
, GPIO_PINCFG54_NCESRC54_DC_DPI_DE = 38
, GPIO_PINCFG54_NCESRC54_DISP_CONT_CSX = 39
,
GPIO_PINCFG54_NCESRC54_DC_SPI_CS_N = 40
, GPIO_PINCFG54_NCESRC54_DC_QSPI_CS_N = 41
, GPIO_PINCFG54_NCESRC54_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG54_PULLCFG54_Enum {
GPIO_PINCFG54_PULLCFG54_DIS = 0
, GPIO_PINCFG54_PULLCFG54_PD50K = 1
, GPIO_PINCFG54_PULLCFG54_PU15K = 2
, GPIO_PINCFG54_PULLCFG54_PU6K = 3
,
GPIO_PINCFG54_PULLCFG54_PU12K = 4
, GPIO_PINCFG54_PULLCFG54_PU24K = 5
, GPIO_PINCFG54_PULLCFG54_PU50K = 6
, GPIO_PINCFG54_PULLCFG54_PU100K = 7
} |
| |
| enum | GPIO_PINCFG54_DS54_Enum { GPIO_PINCFG54_DS54_0P1X = 0
, GPIO_PINCFG54_DS54_0P5X = 1
, GPIO_PINCFG54_DS54_0P75X = 2
, GPIO_PINCFG54_DS54_1P0X = 3
} |
| |
| enum | GPIO_PINCFG54_OUTCFG54_Enum { GPIO_PINCFG54_OUTCFG54_DIS = 0
, GPIO_PINCFG54_OUTCFG54_PUSHPULL = 1
, GPIO_PINCFG54_OUTCFG54_OD = 2
, GPIO_PINCFG54_OUTCFG54_TS = 3
} |
| |
| enum | GPIO_PINCFG54_IRPTEN54_Enum { GPIO_PINCFG54_IRPTEN54_DIS = 0
, GPIO_PINCFG54_IRPTEN54_INTFALL = 1
, GPIO_PINCFG54_IRPTEN54_INTRISE = 2
, GPIO_PINCFG54_IRPTEN54_INTANY = 3
} |
| |
| enum | GPIO_PINCFG54_FNCSEL54_Enum {
GPIO_PINCFG54_FNCSEL54_PDM2_CLK = 0
, GPIO_PINCFG54_FNCSEL54_TRIG0 = 1
, GPIO_PINCFG54_FNCSEL54_SWTRACE3 = 2
, GPIO_PINCFG54_FNCSEL54_GPIO = 3
,
GPIO_PINCFG54_FNCSEL54_UART2TX = 4
, GPIO_PINCFG54_FNCSEL54_UART3TX = 5
, GPIO_PINCFG54_FNCSEL54_CT54 = 6
, GPIO_PINCFG54_FNCSEL54_NCE54 = 7
,
GPIO_PINCFG54_FNCSEL54_OBSBUS6 = 8
, GPIO_PINCFG54_FNCSEL54_RESERVED9 = 9
, GPIO_PINCFG54_FNCSEL54_RESERVED10 = 10
, GPIO_PINCFG54_FNCSEL54_FPIO = 11
,
GPIO_PINCFG54_FNCSEL54_RESERVED12 = 12
, GPIO_PINCFG54_FNCSEL54_RESERVED13 = 13
, GPIO_PINCFG54_FNCSEL54_RESERVED14 = 14
, GPIO_PINCFG54_FNCSEL54_RESERVED15 = 15
} |
| |
| enum | GPIO_PINCFG55_NCEPOL55_Enum { GPIO_PINCFG55_NCEPOL55_LOW = 0
, GPIO_PINCFG55_NCEPOL55_HIGH = 1
} |
| |
| enum | GPIO_PINCFG55_NCESRC55_Enum {
GPIO_PINCFG55_NCESRC55_IOM0CE0 = 0
, GPIO_PINCFG55_NCESRC55_IOM0CE1 = 1
, GPIO_PINCFG55_NCESRC55_IOM0CE2 = 2
, GPIO_PINCFG55_NCESRC55_IOM0CE3 = 3
,
GPIO_PINCFG55_NCESRC55_IOM1CE0 = 4
, GPIO_PINCFG55_NCESRC55_IOM1CE1 = 5
, GPIO_PINCFG55_NCESRC55_IOM1CE2 = 6
, GPIO_PINCFG55_NCESRC55_IOM1CE3 = 7
,
GPIO_PINCFG55_NCESRC55_IOM2CE0 = 8
, GPIO_PINCFG55_NCESRC55_IOM2CE1 = 9
, GPIO_PINCFG55_NCESRC55_IOM2CE2 = 10
, GPIO_PINCFG55_NCESRC55_IOM2CE3 = 11
,
GPIO_PINCFG55_NCESRC55_IOM3CE0 = 12
, GPIO_PINCFG55_NCESRC55_IOM3CE1 = 13
, GPIO_PINCFG55_NCESRC55_IOM3CE2 = 14
, GPIO_PINCFG55_NCESRC55_IOM3CE3 = 15
,
GPIO_PINCFG55_NCESRC55_IOM4CE0 = 16
, GPIO_PINCFG55_NCESRC55_IOM4CE1 = 17
, GPIO_PINCFG55_NCESRC55_IOM4CE2 = 18
, GPIO_PINCFG55_NCESRC55_IOM4CE3 = 19
,
GPIO_PINCFG55_NCESRC55_IOM5CE0 = 20
, GPIO_PINCFG55_NCESRC55_IOM5CE1 = 21
, GPIO_PINCFG55_NCESRC55_IOM5CE2 = 22
, GPIO_PINCFG55_NCESRC55_IOM5CE3 = 23
,
GPIO_PINCFG55_NCESRC55_IOM6CE0 = 24
, GPIO_PINCFG55_NCESRC55_IOM6CE1 = 25
, GPIO_PINCFG55_NCESRC55_IOM6CE2 = 26
, GPIO_PINCFG55_NCESRC55_IOM6CE3 = 27
,
GPIO_PINCFG55_NCESRC55_IOM7CE0 = 28
, GPIO_PINCFG55_NCESRC55_IOM7CE1 = 29
, GPIO_PINCFG55_NCESRC55_IOM7CE2 = 30
, GPIO_PINCFG55_NCESRC55_IOM7CE3 = 31
,
GPIO_PINCFG55_NCESRC55_MSPI0CEN0 = 32
, GPIO_PINCFG55_NCESRC55_MSPI0CEN1 = 33
, GPIO_PINCFG55_NCESRC55_MSPI1CEN0 = 34
, GPIO_PINCFG55_NCESRC55_MSPI1CEN1 = 35
,
GPIO_PINCFG55_NCESRC55_MSPI2CEN0 = 36
, GPIO_PINCFG55_NCESRC55_MSPI2CEN1 = 37
, GPIO_PINCFG55_NCESRC55_DC_DPI_DE = 38
, GPIO_PINCFG55_NCESRC55_DISP_CONT_CSX = 39
,
GPIO_PINCFG55_NCESRC55_DC_SPI_CS_N = 40
, GPIO_PINCFG55_NCESRC55_DC_QSPI_CS_N = 41
, GPIO_PINCFG55_NCESRC55_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG55_PULLCFG55_Enum {
GPIO_PINCFG55_PULLCFG55_DIS = 0
, GPIO_PINCFG55_PULLCFG55_PD50K = 1
, GPIO_PINCFG55_PULLCFG55_PU15K = 2
, GPIO_PINCFG55_PULLCFG55_PU6K = 3
,
GPIO_PINCFG55_PULLCFG55_PU12K = 4
, GPIO_PINCFG55_PULLCFG55_PU24K = 5
, GPIO_PINCFG55_PULLCFG55_PU50K = 6
, GPIO_PINCFG55_PULLCFG55_PU100K = 7
} |
| |
| enum | GPIO_PINCFG55_DS55_Enum { GPIO_PINCFG55_DS55_0P1X = 0
, GPIO_PINCFG55_DS55_0P5X = 1
, GPIO_PINCFG55_DS55_0P75X = 2
, GPIO_PINCFG55_DS55_1P0X = 3
} |
| |
| enum | GPIO_PINCFG55_OUTCFG55_Enum { GPIO_PINCFG55_OUTCFG55_DIS = 0
, GPIO_PINCFG55_OUTCFG55_PUSHPULL = 1
, GPIO_PINCFG55_OUTCFG55_OD = 2
, GPIO_PINCFG55_OUTCFG55_TS = 3
} |
| |
| enum | GPIO_PINCFG55_IRPTEN55_Enum { GPIO_PINCFG55_IRPTEN55_DIS = 0
, GPIO_PINCFG55_IRPTEN55_INTFALL = 1
, GPIO_PINCFG55_IRPTEN55_INTRISE = 2
, GPIO_PINCFG55_IRPTEN55_INTANY = 3
} |
| |
| enum | GPIO_PINCFG55_FNCSEL55_Enum {
GPIO_PINCFG55_FNCSEL55_PDM2_DATA = 0
, GPIO_PINCFG55_FNCSEL55_TRIG1 = 1
, GPIO_PINCFG55_FNCSEL55_SWTRACECTL = 2
, GPIO_PINCFG55_FNCSEL55_GPIO = 3
,
GPIO_PINCFG55_FNCSEL55_UART0RX = 4
, GPIO_PINCFG55_FNCSEL55_UART1RX = 5
, GPIO_PINCFG55_FNCSEL55_CT55 = 6
, GPIO_PINCFG55_FNCSEL55_NCE55 = 7
,
GPIO_PINCFG55_FNCSEL55_OBSBUS7 = 8
, GPIO_PINCFG55_FNCSEL55_RESERVED9 = 9
, GPIO_PINCFG55_FNCSEL55_RESERVED10 = 10
, GPIO_PINCFG55_FNCSEL55_FPIO = 11
,
GPIO_PINCFG55_FNCSEL55_RESERVED12 = 12
, GPIO_PINCFG55_FNCSEL55_RESERVED13 = 13
, GPIO_PINCFG55_FNCSEL55_RESERVED14 = 14
, GPIO_PINCFG55_FNCSEL55_RESERVED15 = 15
} |
| |
| enum | GPIO_PINCFG56_NCEPOL56_Enum { GPIO_PINCFG56_NCEPOL56_LOW = 0
, GPIO_PINCFG56_NCEPOL56_HIGH = 1
} |
| |
| enum | GPIO_PINCFG56_NCESRC56_Enum {
GPIO_PINCFG56_NCESRC56_IOM0CE0 = 0
, GPIO_PINCFG56_NCESRC56_IOM0CE1 = 1
, GPIO_PINCFG56_NCESRC56_IOM0CE2 = 2
, GPIO_PINCFG56_NCESRC56_IOM0CE3 = 3
,
GPIO_PINCFG56_NCESRC56_IOM1CE0 = 4
, GPIO_PINCFG56_NCESRC56_IOM1CE1 = 5
, GPIO_PINCFG56_NCESRC56_IOM1CE2 = 6
, GPIO_PINCFG56_NCESRC56_IOM1CE3 = 7
,
GPIO_PINCFG56_NCESRC56_IOM2CE0 = 8
, GPIO_PINCFG56_NCESRC56_IOM2CE1 = 9
, GPIO_PINCFG56_NCESRC56_IOM2CE2 = 10
, GPIO_PINCFG56_NCESRC56_IOM2CE3 = 11
,
GPIO_PINCFG56_NCESRC56_IOM3CE0 = 12
, GPIO_PINCFG56_NCESRC56_IOM3CE1 = 13
, GPIO_PINCFG56_NCESRC56_IOM3CE2 = 14
, GPIO_PINCFG56_NCESRC56_IOM3CE3 = 15
,
GPIO_PINCFG56_NCESRC56_IOM4CE0 = 16
, GPIO_PINCFG56_NCESRC56_IOM4CE1 = 17
, GPIO_PINCFG56_NCESRC56_IOM4CE2 = 18
, GPIO_PINCFG56_NCESRC56_IOM4CE3 = 19
,
GPIO_PINCFG56_NCESRC56_IOM5CE0 = 20
, GPIO_PINCFG56_NCESRC56_IOM5CE1 = 21
, GPIO_PINCFG56_NCESRC56_IOM5CE2 = 22
, GPIO_PINCFG56_NCESRC56_IOM5CE3 = 23
,
GPIO_PINCFG56_NCESRC56_IOM6CE0 = 24
, GPIO_PINCFG56_NCESRC56_IOM6CE1 = 25
, GPIO_PINCFG56_NCESRC56_IOM6CE2 = 26
, GPIO_PINCFG56_NCESRC56_IOM6CE3 = 27
,
GPIO_PINCFG56_NCESRC56_IOM7CE0 = 28
, GPIO_PINCFG56_NCESRC56_IOM7CE1 = 29
, GPIO_PINCFG56_NCESRC56_IOM7CE2 = 30
, GPIO_PINCFG56_NCESRC56_IOM7CE3 = 31
,
GPIO_PINCFG56_NCESRC56_MSPI0CEN0 = 32
, GPIO_PINCFG56_NCESRC56_MSPI0CEN1 = 33
, GPIO_PINCFG56_NCESRC56_MSPI1CEN0 = 34
, GPIO_PINCFG56_NCESRC56_MSPI1CEN1 = 35
,
GPIO_PINCFG56_NCESRC56_MSPI2CEN0 = 36
, GPIO_PINCFG56_NCESRC56_MSPI2CEN1 = 37
, GPIO_PINCFG56_NCESRC56_DC_DPI_DE = 38
, GPIO_PINCFG56_NCESRC56_DISP_CONT_CSX = 39
,
GPIO_PINCFG56_NCESRC56_DC_SPI_CS_N = 40
, GPIO_PINCFG56_NCESRC56_DC_QSPI_CS_N = 41
, GPIO_PINCFG56_NCESRC56_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG56_PULLCFG56_Enum {
GPIO_PINCFG56_PULLCFG56_DIS = 0
, GPIO_PINCFG56_PULLCFG56_PD50K = 1
, GPIO_PINCFG56_PULLCFG56_PU15K = 2
, GPIO_PINCFG56_PULLCFG56_PU6K = 3
,
GPIO_PINCFG56_PULLCFG56_PU12K = 4
, GPIO_PINCFG56_PULLCFG56_PU24K = 5
, GPIO_PINCFG56_PULLCFG56_PU50K = 6
, GPIO_PINCFG56_PULLCFG56_PU100K = 7
} |
| |
| enum | GPIO_PINCFG56_DS56_Enum { GPIO_PINCFG56_DS56_0P1X = 0
, GPIO_PINCFG56_DS56_0P5X = 1
, GPIO_PINCFG56_DS56_0P75X = 2
, GPIO_PINCFG56_DS56_1P0X = 3
} |
| |
| enum | GPIO_PINCFG56_OUTCFG56_Enum { GPIO_PINCFG56_OUTCFG56_DIS = 0
, GPIO_PINCFG56_OUTCFG56_PUSHPULL = 1
, GPIO_PINCFG56_OUTCFG56_OD = 2
, GPIO_PINCFG56_OUTCFG56_TS = 3
} |
| |
| enum | GPIO_PINCFG56_IRPTEN56_Enum { GPIO_PINCFG56_IRPTEN56_DIS = 0
, GPIO_PINCFG56_IRPTEN56_INTFALL = 1
, GPIO_PINCFG56_IRPTEN56_INTRISE = 2
, GPIO_PINCFG56_IRPTEN56_INTANY = 3
} |
| |
| enum | GPIO_PINCFG56_FNCSEL56_Enum {
GPIO_PINCFG56_FNCSEL56_PDM3_CLK = 0
, GPIO_PINCFG56_FNCSEL56_TRIG2 = 1
, GPIO_PINCFG56_FNCSEL56_SWO = 2
, GPIO_PINCFG56_FNCSEL56_GPIO = 3
,
GPIO_PINCFG56_FNCSEL56_UART2RX = 4
, GPIO_PINCFG56_FNCSEL56_UART3RX = 5
, GPIO_PINCFG56_FNCSEL56_CT56 = 6
, GPIO_PINCFG56_FNCSEL56_NCE56 = 7
,
GPIO_PINCFG56_FNCSEL56_OBSBUS8 = 8
, GPIO_PINCFG56_FNCSEL56_RESERVED9 = 9
, GPIO_PINCFG56_FNCSEL56_RESERVED10 = 10
, GPIO_PINCFG56_FNCSEL56_FPIO = 11
,
GPIO_PINCFG56_FNCSEL56_RESERVED12 = 12
, GPIO_PINCFG56_FNCSEL56_RESERVED13 = 13
, GPIO_PINCFG56_FNCSEL56_RESERVED14 = 14
, GPIO_PINCFG56_FNCSEL56_RESERVED15 = 15
} |
| |
| enum | GPIO_PINCFG57_NCEPOL57_Enum { GPIO_PINCFG57_NCEPOL57_LOW = 0
, GPIO_PINCFG57_NCEPOL57_HIGH = 1
} |
| |
| enum | GPIO_PINCFG57_NCESRC57_Enum {
GPIO_PINCFG57_NCESRC57_IOM0CE0 = 0
, GPIO_PINCFG57_NCESRC57_IOM0CE1 = 1
, GPIO_PINCFG57_NCESRC57_IOM0CE2 = 2
, GPIO_PINCFG57_NCESRC57_IOM0CE3 = 3
,
GPIO_PINCFG57_NCESRC57_IOM1CE0 = 4
, GPIO_PINCFG57_NCESRC57_IOM1CE1 = 5
, GPIO_PINCFG57_NCESRC57_IOM1CE2 = 6
, GPIO_PINCFG57_NCESRC57_IOM1CE3 = 7
,
GPIO_PINCFG57_NCESRC57_IOM2CE0 = 8
, GPIO_PINCFG57_NCESRC57_IOM2CE1 = 9
, GPIO_PINCFG57_NCESRC57_IOM2CE2 = 10
, GPIO_PINCFG57_NCESRC57_IOM2CE3 = 11
,
GPIO_PINCFG57_NCESRC57_IOM3CE0 = 12
, GPIO_PINCFG57_NCESRC57_IOM3CE1 = 13
, GPIO_PINCFG57_NCESRC57_IOM3CE2 = 14
, GPIO_PINCFG57_NCESRC57_IOM3CE3 = 15
,
GPIO_PINCFG57_NCESRC57_IOM4CE0 = 16
, GPIO_PINCFG57_NCESRC57_IOM4CE1 = 17
, GPIO_PINCFG57_NCESRC57_IOM4CE2 = 18
, GPIO_PINCFG57_NCESRC57_IOM4CE3 = 19
,
GPIO_PINCFG57_NCESRC57_IOM5CE0 = 20
, GPIO_PINCFG57_NCESRC57_IOM5CE1 = 21
, GPIO_PINCFG57_NCESRC57_IOM5CE2 = 22
, GPIO_PINCFG57_NCESRC57_IOM5CE3 = 23
,
GPIO_PINCFG57_NCESRC57_IOM6CE0 = 24
, GPIO_PINCFG57_NCESRC57_IOM6CE1 = 25
, GPIO_PINCFG57_NCESRC57_IOM6CE2 = 26
, GPIO_PINCFG57_NCESRC57_IOM6CE3 = 27
,
GPIO_PINCFG57_NCESRC57_IOM7CE0 = 28
, GPIO_PINCFG57_NCESRC57_IOM7CE1 = 29
, GPIO_PINCFG57_NCESRC57_IOM7CE2 = 30
, GPIO_PINCFG57_NCESRC57_IOM7CE3 = 31
,
GPIO_PINCFG57_NCESRC57_MSPI0CEN0 = 32
, GPIO_PINCFG57_NCESRC57_MSPI0CEN1 = 33
, GPIO_PINCFG57_NCESRC57_MSPI1CEN0 = 34
, GPIO_PINCFG57_NCESRC57_MSPI1CEN1 = 35
,
GPIO_PINCFG57_NCESRC57_MSPI2CEN0 = 36
, GPIO_PINCFG57_NCESRC57_MSPI2CEN1 = 37
, GPIO_PINCFG57_NCESRC57_DC_DPI_DE = 38
, GPIO_PINCFG57_NCESRC57_DISP_CONT_CSX = 39
,
GPIO_PINCFG57_NCESRC57_DC_SPI_CS_N = 40
, GPIO_PINCFG57_NCESRC57_DC_QSPI_CS_N = 41
, GPIO_PINCFG57_NCESRC57_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG57_PULLCFG57_Enum {
GPIO_PINCFG57_PULLCFG57_DIS = 0
, GPIO_PINCFG57_PULLCFG57_PD50K = 1
, GPIO_PINCFG57_PULLCFG57_PU15K = 2
, GPIO_PINCFG57_PULLCFG57_PU6K = 3
,
GPIO_PINCFG57_PULLCFG57_PU12K = 4
, GPIO_PINCFG57_PULLCFG57_PU24K = 5
, GPIO_PINCFG57_PULLCFG57_PU50K = 6
, GPIO_PINCFG57_PULLCFG57_PU100K = 7
} |
| |
| enum | GPIO_PINCFG57_DS57_Enum { GPIO_PINCFG57_DS57_0P1X = 0
, GPIO_PINCFG57_DS57_0P5X = 1
, GPIO_PINCFG57_DS57_0P75X = 2
, GPIO_PINCFG57_DS57_1P0X = 3
} |
| |
| enum | GPIO_PINCFG57_OUTCFG57_Enum { GPIO_PINCFG57_OUTCFG57_DIS = 0
, GPIO_PINCFG57_OUTCFG57_PUSHPULL = 1
, GPIO_PINCFG57_OUTCFG57_OD = 2
, GPIO_PINCFG57_OUTCFG57_TS = 3
} |
| |
| enum | GPIO_PINCFG57_IRPTEN57_Enum { GPIO_PINCFG57_IRPTEN57_DIS = 0
, GPIO_PINCFG57_IRPTEN57_INTFALL = 1
, GPIO_PINCFG57_IRPTEN57_INTRISE = 2
, GPIO_PINCFG57_IRPTEN57_INTANY = 3
} |
| |
| enum | GPIO_PINCFG57_FNCSEL57_Enum {
GPIO_PINCFG57_FNCSEL57_PDM3_DATA = 0
, GPIO_PINCFG57_FNCSEL57_TRIG3 = 1
, GPIO_PINCFG57_FNCSEL57_SWO = 2
, GPIO_PINCFG57_FNCSEL57_GPIO = 3
,
GPIO_PINCFG57_FNCSEL57_UART0RTS = 4
, GPIO_PINCFG57_FNCSEL57_UART1RTS = 5
, GPIO_PINCFG57_FNCSEL57_CT57 = 6
, GPIO_PINCFG57_FNCSEL57_NCE57 = 7
,
GPIO_PINCFG57_FNCSEL57_OBSBUS9 = 8
, GPIO_PINCFG57_FNCSEL57_VCMPO = 9
, GPIO_PINCFG57_FNCSEL57_RESERVED10 = 10
, GPIO_PINCFG57_FNCSEL57_FPIO = 11
,
GPIO_PINCFG57_FNCSEL57_RESERVED12 = 12
, GPIO_PINCFG57_FNCSEL57_RESERVED13 = 13
, GPIO_PINCFG57_FNCSEL57_RESERVED14 = 14
, GPIO_PINCFG57_FNCSEL57_RESERVED15 = 15
} |
| |
| enum | GPIO_PINCFG58_NCEPOL58_Enum { GPIO_PINCFG58_NCEPOL58_LOW = 0
, GPIO_PINCFG58_NCEPOL58_HIGH = 1
} |
| |
| enum | GPIO_PINCFG58_NCESRC58_Enum {
GPIO_PINCFG58_NCESRC58_IOM0CE0 = 0
, GPIO_PINCFG58_NCESRC58_IOM0CE1 = 1
, GPIO_PINCFG58_NCESRC58_IOM0CE2 = 2
, GPIO_PINCFG58_NCESRC58_IOM0CE3 = 3
,
GPIO_PINCFG58_NCESRC58_IOM1CE0 = 4
, GPIO_PINCFG58_NCESRC58_IOM1CE1 = 5
, GPIO_PINCFG58_NCESRC58_IOM1CE2 = 6
, GPIO_PINCFG58_NCESRC58_IOM1CE3 = 7
,
GPIO_PINCFG58_NCESRC58_IOM2CE0 = 8
, GPIO_PINCFG58_NCESRC58_IOM2CE1 = 9
, GPIO_PINCFG58_NCESRC58_IOM2CE2 = 10
, GPIO_PINCFG58_NCESRC58_IOM2CE3 = 11
,
GPIO_PINCFG58_NCESRC58_IOM3CE0 = 12
, GPIO_PINCFG58_NCESRC58_IOM3CE1 = 13
, GPIO_PINCFG58_NCESRC58_IOM3CE2 = 14
, GPIO_PINCFG58_NCESRC58_IOM3CE3 = 15
,
GPIO_PINCFG58_NCESRC58_IOM4CE0 = 16
, GPIO_PINCFG58_NCESRC58_IOM4CE1 = 17
, GPIO_PINCFG58_NCESRC58_IOM4CE2 = 18
, GPIO_PINCFG58_NCESRC58_IOM4CE3 = 19
,
GPIO_PINCFG58_NCESRC58_IOM5CE0 = 20
, GPIO_PINCFG58_NCESRC58_IOM5CE1 = 21
, GPIO_PINCFG58_NCESRC58_IOM5CE2 = 22
, GPIO_PINCFG58_NCESRC58_IOM5CE3 = 23
,
GPIO_PINCFG58_NCESRC58_IOM6CE0 = 24
, GPIO_PINCFG58_NCESRC58_IOM6CE1 = 25
, GPIO_PINCFG58_NCESRC58_IOM6CE2 = 26
, GPIO_PINCFG58_NCESRC58_IOM6CE3 = 27
,
GPIO_PINCFG58_NCESRC58_IOM7CE0 = 28
, GPIO_PINCFG58_NCESRC58_IOM7CE1 = 29
, GPIO_PINCFG58_NCESRC58_IOM7CE2 = 30
, GPIO_PINCFG58_NCESRC58_IOM7CE3 = 31
,
GPIO_PINCFG58_NCESRC58_MSPI0CEN0 = 32
, GPIO_PINCFG58_NCESRC58_MSPI0CEN1 = 33
, GPIO_PINCFG58_NCESRC58_MSPI1CEN0 = 34
, GPIO_PINCFG58_NCESRC58_MSPI1CEN1 = 35
,
GPIO_PINCFG58_NCESRC58_MSPI2CEN0 = 36
, GPIO_PINCFG58_NCESRC58_MSPI2CEN1 = 37
, GPIO_PINCFG58_NCESRC58_DC_DPI_DE = 38
, GPIO_PINCFG58_NCESRC58_DISP_CONT_CSX = 39
,
GPIO_PINCFG58_NCESRC58_DC_SPI_CS_N = 40
, GPIO_PINCFG58_NCESRC58_DC_QSPI_CS_N = 41
, GPIO_PINCFG58_NCESRC58_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG58_PULLCFG58_Enum {
GPIO_PINCFG58_PULLCFG58_DIS = 0
, GPIO_PINCFG58_PULLCFG58_PD50K = 1
, GPIO_PINCFG58_PULLCFG58_PU15K = 2
, GPIO_PINCFG58_PULLCFG58_PU6K = 3
,
GPIO_PINCFG58_PULLCFG58_PU12K = 4
, GPIO_PINCFG58_PULLCFG58_PU24K = 5
, GPIO_PINCFG58_PULLCFG58_PU50K = 6
, GPIO_PINCFG58_PULLCFG58_PU100K = 7
} |
| |
| enum | GPIO_PINCFG58_DS58_Enum { GPIO_PINCFG58_DS58_0P1X = 0
, GPIO_PINCFG58_DS58_0P5X = 1
} |
| |
| enum | GPIO_PINCFG58_OUTCFG58_Enum { GPIO_PINCFG58_OUTCFG58_DIS = 0
, GPIO_PINCFG58_OUTCFG58_PUSHPULL = 1
, GPIO_PINCFG58_OUTCFG58_OD = 2
, GPIO_PINCFG58_OUTCFG58_TS = 3
} |
| |
| enum | GPIO_PINCFG58_IRPTEN58_Enum { GPIO_PINCFG58_IRPTEN58_DIS = 0
, GPIO_PINCFG58_IRPTEN58_INTFALL = 1
, GPIO_PINCFG58_IRPTEN58_INTRISE = 2
, GPIO_PINCFG58_IRPTEN58_INTANY = 3
} |
| |
| enum | GPIO_PINCFG58_FNCSEL58_Enum {
GPIO_PINCFG58_FNCSEL58_RESERVED0 = 0
, GPIO_PINCFG58_FNCSEL58_RESERVED1 = 1
, GPIO_PINCFG58_FNCSEL58_RESERVED2 = 2
, GPIO_PINCFG58_FNCSEL58_GPIO = 3
,
GPIO_PINCFG58_FNCSEL58_UART0RTS = 4
, GPIO_PINCFG58_FNCSEL58_UART3RTS = 5
, GPIO_PINCFG58_FNCSEL58_CT58 = 6
, GPIO_PINCFG58_FNCSEL58_NCE58 = 7
,
GPIO_PINCFG58_FNCSEL58_OBSBUS10 = 8
, GPIO_PINCFG58_FNCSEL58_RESERVED9 = 9
, GPIO_PINCFG58_FNCSEL58_RESERVED10 = 10
, GPIO_PINCFG58_FNCSEL58_FPIO = 11
,
GPIO_PINCFG58_FNCSEL58_RESERVED12 = 12
, GPIO_PINCFG58_FNCSEL58_RESERVED13 = 13
, GPIO_PINCFG58_FNCSEL58_RESERVED14 = 14
, GPIO_PINCFG58_FNCSEL58_RESERVED15 = 15
} |
| |
| enum | GPIO_PINCFG59_NCEPOL59_Enum { GPIO_PINCFG59_NCEPOL59_LOW = 0
, GPIO_PINCFG59_NCEPOL59_HIGH = 1
} |
| |
| enum | GPIO_PINCFG59_NCESRC59_Enum {
GPIO_PINCFG59_NCESRC59_IOM0CE0 = 0
, GPIO_PINCFG59_NCESRC59_IOM0CE1 = 1
, GPIO_PINCFG59_NCESRC59_IOM0CE2 = 2
, GPIO_PINCFG59_NCESRC59_IOM0CE3 = 3
,
GPIO_PINCFG59_NCESRC59_IOM1CE0 = 4
, GPIO_PINCFG59_NCESRC59_IOM1CE1 = 5
, GPIO_PINCFG59_NCESRC59_IOM1CE2 = 6
, GPIO_PINCFG59_NCESRC59_IOM1CE3 = 7
,
GPIO_PINCFG59_NCESRC59_IOM2CE0 = 8
, GPIO_PINCFG59_NCESRC59_IOM2CE1 = 9
, GPIO_PINCFG59_NCESRC59_IOM2CE2 = 10
, GPIO_PINCFG59_NCESRC59_IOM2CE3 = 11
,
GPIO_PINCFG59_NCESRC59_IOM3CE0 = 12
, GPIO_PINCFG59_NCESRC59_IOM3CE1 = 13
, GPIO_PINCFG59_NCESRC59_IOM3CE2 = 14
, GPIO_PINCFG59_NCESRC59_IOM3CE3 = 15
,
GPIO_PINCFG59_NCESRC59_IOM4CE0 = 16
, GPIO_PINCFG59_NCESRC59_IOM4CE1 = 17
, GPIO_PINCFG59_NCESRC59_IOM4CE2 = 18
, GPIO_PINCFG59_NCESRC59_IOM4CE3 = 19
,
GPIO_PINCFG59_NCESRC59_IOM5CE0 = 20
, GPIO_PINCFG59_NCESRC59_IOM5CE1 = 21
, GPIO_PINCFG59_NCESRC59_IOM5CE2 = 22
, GPIO_PINCFG59_NCESRC59_IOM5CE3 = 23
,
GPIO_PINCFG59_NCESRC59_IOM6CE0 = 24
, GPIO_PINCFG59_NCESRC59_IOM6CE1 = 25
, GPIO_PINCFG59_NCESRC59_IOM6CE2 = 26
, GPIO_PINCFG59_NCESRC59_IOM6CE3 = 27
,
GPIO_PINCFG59_NCESRC59_IOM7CE0 = 28
, GPIO_PINCFG59_NCESRC59_IOM7CE1 = 29
, GPIO_PINCFG59_NCESRC59_IOM7CE2 = 30
, GPIO_PINCFG59_NCESRC59_IOM7CE3 = 31
,
GPIO_PINCFG59_NCESRC59_MSPI0CEN0 = 32
, GPIO_PINCFG59_NCESRC59_MSPI0CEN1 = 33
, GPIO_PINCFG59_NCESRC59_MSPI1CEN0 = 34
, GPIO_PINCFG59_NCESRC59_MSPI1CEN1 = 35
,
GPIO_PINCFG59_NCESRC59_MSPI2CEN0 = 36
, GPIO_PINCFG59_NCESRC59_MSPI2CEN1 = 37
, GPIO_PINCFG59_NCESRC59_DC_DPI_DE = 38
, GPIO_PINCFG59_NCESRC59_DISP_CONT_CSX = 39
,
GPIO_PINCFG59_NCESRC59_DC_SPI_CS_N = 40
, GPIO_PINCFG59_NCESRC59_DC_QSPI_CS_N = 41
, GPIO_PINCFG59_NCESRC59_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG59_PULLCFG59_Enum {
GPIO_PINCFG59_PULLCFG59_DIS = 0
, GPIO_PINCFG59_PULLCFG59_PD50K = 1
, GPIO_PINCFG59_PULLCFG59_PU15K = 2
, GPIO_PINCFG59_PULLCFG59_PU6K = 3
,
GPIO_PINCFG59_PULLCFG59_PU12K = 4
, GPIO_PINCFG59_PULLCFG59_PU24K = 5
, GPIO_PINCFG59_PULLCFG59_PU50K = 6
, GPIO_PINCFG59_PULLCFG59_PU100K = 7
} |
| |
| enum | GPIO_PINCFG59_DS59_Enum { GPIO_PINCFG59_DS59_0P1X = 0
, GPIO_PINCFG59_DS59_0P5X = 1
} |
| |
| enum | GPIO_PINCFG59_OUTCFG59_Enum { GPIO_PINCFG59_OUTCFG59_DIS = 0
, GPIO_PINCFG59_OUTCFG59_PUSHPULL = 1
, GPIO_PINCFG59_OUTCFG59_OD = 2
, GPIO_PINCFG59_OUTCFG59_TS = 3
} |
| |
| enum | GPIO_PINCFG59_IRPTEN59_Enum { GPIO_PINCFG59_IRPTEN59_DIS = 0
, GPIO_PINCFG59_IRPTEN59_INTFALL = 1
, GPIO_PINCFG59_IRPTEN59_INTRISE = 2
, GPIO_PINCFG59_IRPTEN59_INTANY = 3
} |
| |
| enum | GPIO_PINCFG59_FNCSEL59_Enum {
GPIO_PINCFG59_FNCSEL59_RESERVED0 = 0
, GPIO_PINCFG59_FNCSEL59_TRIG0 = 1
, GPIO_PINCFG59_FNCSEL59_RESERVED2 = 2
, GPIO_PINCFG59_FNCSEL59_GPIO = 3
,
GPIO_PINCFG59_FNCSEL59_UART0CTS = 4
, GPIO_PINCFG59_FNCSEL59_UART1CTS = 5
, GPIO_PINCFG59_FNCSEL59_CT59 = 6
, GPIO_PINCFG59_FNCSEL59_NCE59 = 7
,
GPIO_PINCFG59_FNCSEL59_OBSBUS11 = 8
, GPIO_PINCFG59_FNCSEL59_RESERVED9 = 9
, GPIO_PINCFG59_FNCSEL59_RESERVED10 = 10
, GPIO_PINCFG59_FNCSEL59_FPIO = 11
,
GPIO_PINCFG59_FNCSEL59_RESERVED12 = 12
, GPIO_PINCFG59_FNCSEL59_RESERVED13 = 13
, GPIO_PINCFG59_FNCSEL59_RESERVED14 = 14
, GPIO_PINCFG59_FNCSEL59_RESERVED15 = 15
} |
| |
| enum | GPIO_PINCFG60_NCEPOL60_Enum { GPIO_PINCFG60_NCEPOL60_LOW = 0
, GPIO_PINCFG60_NCEPOL60_HIGH = 1
} |
| |
| enum | GPIO_PINCFG60_NCESRC60_Enum {
GPIO_PINCFG60_NCESRC60_IOM0CE0 = 0
, GPIO_PINCFG60_NCESRC60_IOM0CE1 = 1
, GPIO_PINCFG60_NCESRC60_IOM0CE2 = 2
, GPIO_PINCFG60_NCESRC60_IOM0CE3 = 3
,
GPIO_PINCFG60_NCESRC60_IOM1CE0 = 4
, GPIO_PINCFG60_NCESRC60_IOM1CE1 = 5
, GPIO_PINCFG60_NCESRC60_IOM1CE2 = 6
, GPIO_PINCFG60_NCESRC60_IOM1CE3 = 7
,
GPIO_PINCFG60_NCESRC60_IOM2CE0 = 8
, GPIO_PINCFG60_NCESRC60_IOM2CE1 = 9
, GPIO_PINCFG60_NCESRC60_IOM2CE2 = 10
, GPIO_PINCFG60_NCESRC60_IOM2CE3 = 11
,
GPIO_PINCFG60_NCESRC60_IOM3CE0 = 12
, GPIO_PINCFG60_NCESRC60_IOM3CE1 = 13
, GPIO_PINCFG60_NCESRC60_IOM3CE2 = 14
, GPIO_PINCFG60_NCESRC60_IOM3CE3 = 15
,
GPIO_PINCFG60_NCESRC60_IOM4CE0 = 16
, GPIO_PINCFG60_NCESRC60_IOM4CE1 = 17
, GPIO_PINCFG60_NCESRC60_IOM4CE2 = 18
, GPIO_PINCFG60_NCESRC60_IOM4CE3 = 19
,
GPIO_PINCFG60_NCESRC60_IOM5CE0 = 20
, GPIO_PINCFG60_NCESRC60_IOM5CE1 = 21
, GPIO_PINCFG60_NCESRC60_IOM5CE2 = 22
, GPIO_PINCFG60_NCESRC60_IOM5CE3 = 23
,
GPIO_PINCFG60_NCESRC60_IOM6CE0 = 24
, GPIO_PINCFG60_NCESRC60_IOM6CE1 = 25
, GPIO_PINCFG60_NCESRC60_IOM6CE2 = 26
, GPIO_PINCFG60_NCESRC60_IOM6CE3 = 27
,
GPIO_PINCFG60_NCESRC60_IOM7CE0 = 28
, GPIO_PINCFG60_NCESRC60_IOM7CE1 = 29
, GPIO_PINCFG60_NCESRC60_IOM7CE2 = 30
, GPIO_PINCFG60_NCESRC60_IOM7CE3 = 31
,
GPIO_PINCFG60_NCESRC60_MSPI0CEN0 = 32
, GPIO_PINCFG60_NCESRC60_MSPI0CEN1 = 33
, GPIO_PINCFG60_NCESRC60_MSPI1CEN0 = 34
, GPIO_PINCFG60_NCESRC60_MSPI1CEN1 = 35
,
GPIO_PINCFG60_NCESRC60_MSPI2CEN0 = 36
, GPIO_PINCFG60_NCESRC60_MSPI2CEN1 = 37
, GPIO_PINCFG60_NCESRC60_DC_DPI_DE = 38
, GPIO_PINCFG60_NCESRC60_DISP_CONT_CSX = 39
,
GPIO_PINCFG60_NCESRC60_DC_SPI_CS_N = 40
, GPIO_PINCFG60_NCESRC60_DC_QSPI_CS_N = 41
, GPIO_PINCFG60_NCESRC60_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG60_PULLCFG60_Enum {
GPIO_PINCFG60_PULLCFG60_DIS = 0
, GPIO_PINCFG60_PULLCFG60_PD50K = 1
, GPIO_PINCFG60_PULLCFG60_PU15K = 2
, GPIO_PINCFG60_PULLCFG60_PU6K = 3
,
GPIO_PINCFG60_PULLCFG60_PU12K = 4
, GPIO_PINCFG60_PULLCFG60_PU24K = 5
, GPIO_PINCFG60_PULLCFG60_PU50K = 6
, GPIO_PINCFG60_PULLCFG60_PU100K = 7
} |
| |
| enum | GPIO_PINCFG60_DS60_Enum { GPIO_PINCFG60_DS60_0P1X = 0
, GPIO_PINCFG60_DS60_0P5X = 1
} |
| |
| enum | GPIO_PINCFG60_OUTCFG60_Enum { GPIO_PINCFG60_OUTCFG60_DIS = 0
, GPIO_PINCFG60_OUTCFG60_PUSHPULL = 1
, GPIO_PINCFG60_OUTCFG60_OD = 2
, GPIO_PINCFG60_OUTCFG60_TS = 3
} |
| |
| enum | GPIO_PINCFG60_IRPTEN60_Enum { GPIO_PINCFG60_IRPTEN60_DIS = 0
, GPIO_PINCFG60_IRPTEN60_INTFALL = 1
, GPIO_PINCFG60_IRPTEN60_INTRISE = 2
, GPIO_PINCFG60_IRPTEN60_INTANY = 3
} |
| |
| enum | GPIO_PINCFG60_FNCSEL60_Enum {
GPIO_PINCFG60_FNCSEL60_RESERVED0 = 0
, GPIO_PINCFG60_FNCSEL60_TRIG1 = 1
, GPIO_PINCFG60_FNCSEL60_RESERVED2 = 2
, GPIO_PINCFG60_FNCSEL60_GPIO = 3
,
GPIO_PINCFG60_FNCSEL60_UART0TX = 4
, GPIO_PINCFG60_FNCSEL60_UART3CTS = 5
, GPIO_PINCFG60_FNCSEL60_CT60 = 6
, GPIO_PINCFG60_FNCSEL60_NCE60 = 7
,
GPIO_PINCFG60_FNCSEL60_OBSBUS12 = 8
, GPIO_PINCFG60_FNCSEL60_RESERVED9 = 9
, GPIO_PINCFG60_FNCSEL60_RESERVED10 = 10
, GPIO_PINCFG60_FNCSEL60_FPIO = 11
,
GPIO_PINCFG60_FNCSEL60_RESERVED12 = 12
, GPIO_PINCFG60_FNCSEL60_RESERVED13 = 13
, GPIO_PINCFG60_FNCSEL60_RESERVED14 = 14
, GPIO_PINCFG60_FNCSEL60_RESERVED15 = 15
} |
| |
| enum | GPIO_PINCFG61_NCEPOL61_Enum { GPIO_PINCFG61_NCEPOL61_LOW = 0
, GPIO_PINCFG61_NCEPOL61_HIGH = 1
} |
| |
| enum | GPIO_PINCFG61_NCESRC61_Enum {
GPIO_PINCFG61_NCESRC61_IOM0CE0 = 0
, GPIO_PINCFG61_NCESRC61_IOM0CE1 = 1
, GPIO_PINCFG61_NCESRC61_IOM0CE2 = 2
, GPIO_PINCFG61_NCESRC61_IOM0CE3 = 3
,
GPIO_PINCFG61_NCESRC61_IOM1CE0 = 4
, GPIO_PINCFG61_NCESRC61_IOM1CE1 = 5
, GPIO_PINCFG61_NCESRC61_IOM1CE2 = 6
, GPIO_PINCFG61_NCESRC61_IOM1CE3 = 7
,
GPIO_PINCFG61_NCESRC61_IOM2CE0 = 8
, GPIO_PINCFG61_NCESRC61_IOM2CE1 = 9
, GPIO_PINCFG61_NCESRC61_IOM2CE2 = 10
, GPIO_PINCFG61_NCESRC61_IOM2CE3 = 11
,
GPIO_PINCFG61_NCESRC61_IOM3CE0 = 12
, GPIO_PINCFG61_NCESRC61_IOM3CE1 = 13
, GPIO_PINCFG61_NCESRC61_IOM3CE2 = 14
, GPIO_PINCFG61_NCESRC61_IOM3CE3 = 15
,
GPIO_PINCFG61_NCESRC61_IOM4CE0 = 16
, GPIO_PINCFG61_NCESRC61_IOM4CE1 = 17
, GPIO_PINCFG61_NCESRC61_IOM4CE2 = 18
, GPIO_PINCFG61_NCESRC61_IOM4CE3 = 19
,
GPIO_PINCFG61_NCESRC61_IOM5CE0 = 20
, GPIO_PINCFG61_NCESRC61_IOM5CE1 = 21
, GPIO_PINCFG61_NCESRC61_IOM5CE2 = 22
, GPIO_PINCFG61_NCESRC61_IOM5CE3 = 23
,
GPIO_PINCFG61_NCESRC61_IOM6CE0 = 24
, GPIO_PINCFG61_NCESRC61_IOM6CE1 = 25
, GPIO_PINCFG61_NCESRC61_IOM6CE2 = 26
, GPIO_PINCFG61_NCESRC61_IOM6CE3 = 27
,
GPIO_PINCFG61_NCESRC61_IOM7CE0 = 28
, GPIO_PINCFG61_NCESRC61_IOM7CE1 = 29
, GPIO_PINCFG61_NCESRC61_IOM7CE2 = 30
, GPIO_PINCFG61_NCESRC61_IOM7CE3 = 31
,
GPIO_PINCFG61_NCESRC61_MSPI0CEN0 = 32
, GPIO_PINCFG61_NCESRC61_MSPI0CEN1 = 33
, GPIO_PINCFG61_NCESRC61_MSPI1CEN0 = 34
, GPIO_PINCFG61_NCESRC61_MSPI1CEN1 = 35
,
GPIO_PINCFG61_NCESRC61_MSPI2CEN0 = 36
, GPIO_PINCFG61_NCESRC61_MSPI2CEN1 = 37
, GPIO_PINCFG61_NCESRC61_DC_DPI_DE = 38
, GPIO_PINCFG61_NCESRC61_DISP_CONT_CSX = 39
,
GPIO_PINCFG61_NCESRC61_DC_SPI_CS_N = 40
, GPIO_PINCFG61_NCESRC61_DC_QSPI_CS_N = 41
, GPIO_PINCFG61_NCESRC61_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG61_PULLCFG61_Enum {
GPIO_PINCFG61_PULLCFG61_DIS = 0
, GPIO_PINCFG61_PULLCFG61_PD50K = 1
, GPIO_PINCFG61_PULLCFG61_PU15K = 2
, GPIO_PINCFG61_PULLCFG61_PU6K = 3
,
GPIO_PINCFG61_PULLCFG61_PU12K = 4
, GPIO_PINCFG61_PULLCFG61_PU24K = 5
, GPIO_PINCFG61_PULLCFG61_PU50K = 6
, GPIO_PINCFG61_PULLCFG61_PU100K = 7
} |
| |
| enum | GPIO_PINCFG61_DS61_Enum { GPIO_PINCFG61_DS61_0P1X = 0
, GPIO_PINCFG61_DS61_0P5X = 1
, GPIO_PINCFG61_DS61_0P75X = 2
, GPIO_PINCFG61_DS61_1P0X = 3
} |
| |
| enum | GPIO_PINCFG61_OUTCFG61_Enum { GPIO_PINCFG61_OUTCFG61_DIS = 0
, GPIO_PINCFG61_OUTCFG61_PUSHPULL = 1
, GPIO_PINCFG61_OUTCFG61_OD = 2
, GPIO_PINCFG61_OUTCFG61_TS = 3
} |
| |
| enum | GPIO_PINCFG61_IRPTEN61_Enum { GPIO_PINCFG61_IRPTEN61_DIS = 0
, GPIO_PINCFG61_IRPTEN61_INTFALL = 1
, GPIO_PINCFG61_IRPTEN61_INTRISE = 2
, GPIO_PINCFG61_IRPTEN61_INTANY = 3
} |
| |
| enum | GPIO_PINCFG61_FNCSEL61_Enum {
GPIO_PINCFG61_FNCSEL61_M6SCL = 0
, GPIO_PINCFG61_FNCSEL61_M6SCK = 1
, GPIO_PINCFG61_FNCSEL61_I2S1_CLK = 2
, GPIO_PINCFG61_FNCSEL61_GPIO = 3
,
GPIO_PINCFG61_FNCSEL61_UART2TX = 4
, GPIO_PINCFG61_FNCSEL61_UART3TX = 5
, GPIO_PINCFG61_FNCSEL61_CT61 = 6
, GPIO_PINCFG61_FNCSEL61_NCE61 = 7
,
GPIO_PINCFG61_FNCSEL61_OBSBUS13 = 8
, GPIO_PINCFG61_FNCSEL61_RESERVED9 = 9
, GPIO_PINCFG61_FNCSEL61_I3CM0_SCL = 10
, GPIO_PINCFG61_FNCSEL61_FPIO = 11
,
GPIO_PINCFG61_FNCSEL61_RESERVED12 = 12
, GPIO_PINCFG61_FNCSEL61_RESERVED13 = 13
, GPIO_PINCFG61_FNCSEL61_RESERVED14 = 14
, GPIO_PINCFG61_FNCSEL61_RESERVED15 = 15
} |
| |
| enum | GPIO_PINCFG62_NCEPOL62_Enum { GPIO_PINCFG62_NCEPOL62_LOW = 0
, GPIO_PINCFG62_NCEPOL62_HIGH = 1
} |
| |
| enum | GPIO_PINCFG62_NCESRC62_Enum {
GPIO_PINCFG62_NCESRC62_IOM0CE0 = 0
, GPIO_PINCFG62_NCESRC62_IOM0CE1 = 1
, GPIO_PINCFG62_NCESRC62_IOM0CE2 = 2
, GPIO_PINCFG62_NCESRC62_IOM0CE3 = 3
,
GPIO_PINCFG62_NCESRC62_IOM1CE0 = 4
, GPIO_PINCFG62_NCESRC62_IOM1CE1 = 5
, GPIO_PINCFG62_NCESRC62_IOM1CE2 = 6
, GPIO_PINCFG62_NCESRC62_IOM1CE3 = 7
,
GPIO_PINCFG62_NCESRC62_IOM2CE0 = 8
, GPIO_PINCFG62_NCESRC62_IOM2CE1 = 9
, GPIO_PINCFG62_NCESRC62_IOM2CE2 = 10
, GPIO_PINCFG62_NCESRC62_IOM2CE3 = 11
,
GPIO_PINCFG62_NCESRC62_IOM3CE0 = 12
, GPIO_PINCFG62_NCESRC62_IOM3CE1 = 13
, GPIO_PINCFG62_NCESRC62_IOM3CE2 = 14
, GPIO_PINCFG62_NCESRC62_IOM3CE3 = 15
,
GPIO_PINCFG62_NCESRC62_IOM4CE0 = 16
, GPIO_PINCFG62_NCESRC62_IOM4CE1 = 17
, GPIO_PINCFG62_NCESRC62_IOM4CE2 = 18
, GPIO_PINCFG62_NCESRC62_IOM4CE3 = 19
,
GPIO_PINCFG62_NCESRC62_IOM5CE0 = 20
, GPIO_PINCFG62_NCESRC62_IOM5CE1 = 21
, GPIO_PINCFG62_NCESRC62_IOM5CE2 = 22
, GPIO_PINCFG62_NCESRC62_IOM5CE3 = 23
,
GPIO_PINCFG62_NCESRC62_IOM6CE0 = 24
, GPIO_PINCFG62_NCESRC62_IOM6CE1 = 25
, GPIO_PINCFG62_NCESRC62_IOM6CE2 = 26
, GPIO_PINCFG62_NCESRC62_IOM6CE3 = 27
,
GPIO_PINCFG62_NCESRC62_IOM7CE0 = 28
, GPIO_PINCFG62_NCESRC62_IOM7CE1 = 29
, GPIO_PINCFG62_NCESRC62_IOM7CE2 = 30
, GPIO_PINCFG62_NCESRC62_IOM7CE3 = 31
,
GPIO_PINCFG62_NCESRC62_MSPI0CEN0 = 32
, GPIO_PINCFG62_NCESRC62_MSPI0CEN1 = 33
, GPIO_PINCFG62_NCESRC62_MSPI1CEN0 = 34
, GPIO_PINCFG62_NCESRC62_MSPI1CEN1 = 35
,
GPIO_PINCFG62_NCESRC62_MSPI2CEN0 = 36
, GPIO_PINCFG62_NCESRC62_MSPI2CEN1 = 37
, GPIO_PINCFG62_NCESRC62_DC_DPI_DE = 38
, GPIO_PINCFG62_NCESRC62_DISP_CONT_CSX = 39
,
GPIO_PINCFG62_NCESRC62_DC_SPI_CS_N = 40
, GPIO_PINCFG62_NCESRC62_DC_QSPI_CS_N = 41
, GPIO_PINCFG62_NCESRC62_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG62_PULLCFG62_Enum {
GPIO_PINCFG62_PULLCFG62_DIS = 0
, GPIO_PINCFG62_PULLCFG62_PD50K = 1
, GPIO_PINCFG62_PULLCFG62_PU15K = 2
, GPIO_PINCFG62_PULLCFG62_PU6K = 3
,
GPIO_PINCFG62_PULLCFG62_PU12K = 4
, GPIO_PINCFG62_PULLCFG62_PU24K = 5
, GPIO_PINCFG62_PULLCFG62_PU50K = 6
, GPIO_PINCFG62_PULLCFG62_PU100K = 7
} |
| |
| enum | GPIO_PINCFG62_DS62_Enum { GPIO_PINCFG62_DS62_0P1X = 0
, GPIO_PINCFG62_DS62_0P5X = 1
, GPIO_PINCFG62_DS62_0P75X = 2
, GPIO_PINCFG62_DS62_1P0X = 3
} |
| |
| enum | GPIO_PINCFG62_OUTCFG62_Enum { GPIO_PINCFG62_OUTCFG62_DIS = 0
, GPIO_PINCFG62_OUTCFG62_PUSHPULL = 1
, GPIO_PINCFG62_OUTCFG62_OD = 2
, GPIO_PINCFG62_OUTCFG62_TS = 3
} |
| |
| enum | GPIO_PINCFG62_IRPTEN62_Enum { GPIO_PINCFG62_IRPTEN62_DIS = 0
, GPIO_PINCFG62_IRPTEN62_INTFALL = 1
, GPIO_PINCFG62_IRPTEN62_INTRISE = 2
, GPIO_PINCFG62_IRPTEN62_INTANY = 3
} |
| |
| enum | GPIO_PINCFG62_FNCSEL62_Enum {
GPIO_PINCFG62_FNCSEL62_M6SDAWIR3 = 0
, GPIO_PINCFG62_FNCSEL62_M6MOSI = 1
, GPIO_PINCFG62_FNCSEL62_I2S1_DATA = 2
, GPIO_PINCFG62_FNCSEL62_GPIO = 3
,
GPIO_PINCFG62_FNCSEL62_UART0RX = 4
, GPIO_PINCFG62_FNCSEL62_UART1RX = 5
, GPIO_PINCFG62_FNCSEL62_CT62 = 6
, GPIO_PINCFG62_FNCSEL62_NCE62 = 7
,
GPIO_PINCFG62_FNCSEL62_OBSBUS14 = 8
, GPIO_PINCFG62_FNCSEL62_I2S1_SDOUT = 9
, GPIO_PINCFG62_FNCSEL62_I3CM0_SDA = 10
, GPIO_PINCFG62_FNCSEL62_FPIO = 11
,
GPIO_PINCFG62_FNCSEL62_RESERVED12 = 12
, GPIO_PINCFG62_FNCSEL62_RESERVED13 = 13
, GPIO_PINCFG62_FNCSEL62_RESERVED14 = 14
, GPIO_PINCFG62_FNCSEL62_RESERVED15 = 15
} |
| |
| enum | GPIO_PINCFG63_NCEPOL63_Enum { GPIO_PINCFG63_NCEPOL63_LOW = 0
, GPIO_PINCFG63_NCEPOL63_HIGH = 1
} |
| |
| enum | GPIO_PINCFG63_NCESRC63_Enum {
GPIO_PINCFG63_NCESRC63_IOM0CE0 = 0
, GPIO_PINCFG63_NCESRC63_IOM0CE1 = 1
, GPIO_PINCFG63_NCESRC63_IOM0CE2 = 2
, GPIO_PINCFG63_NCESRC63_IOM0CE3 = 3
,
GPIO_PINCFG63_NCESRC63_IOM1CE0 = 4
, GPIO_PINCFG63_NCESRC63_IOM1CE1 = 5
, GPIO_PINCFG63_NCESRC63_IOM1CE2 = 6
, GPIO_PINCFG63_NCESRC63_IOM1CE3 = 7
,
GPIO_PINCFG63_NCESRC63_IOM2CE0 = 8
, GPIO_PINCFG63_NCESRC63_IOM2CE1 = 9
, GPIO_PINCFG63_NCESRC63_IOM2CE2 = 10
, GPIO_PINCFG63_NCESRC63_IOM2CE3 = 11
,
GPIO_PINCFG63_NCESRC63_IOM3CE0 = 12
, GPIO_PINCFG63_NCESRC63_IOM3CE1 = 13
, GPIO_PINCFG63_NCESRC63_IOM3CE2 = 14
, GPIO_PINCFG63_NCESRC63_IOM3CE3 = 15
,
GPIO_PINCFG63_NCESRC63_IOM4CE0 = 16
, GPIO_PINCFG63_NCESRC63_IOM4CE1 = 17
, GPIO_PINCFG63_NCESRC63_IOM4CE2 = 18
, GPIO_PINCFG63_NCESRC63_IOM4CE3 = 19
,
GPIO_PINCFG63_NCESRC63_IOM5CE0 = 20
, GPIO_PINCFG63_NCESRC63_IOM5CE1 = 21
, GPIO_PINCFG63_NCESRC63_IOM5CE2 = 22
, GPIO_PINCFG63_NCESRC63_IOM5CE3 = 23
,
GPIO_PINCFG63_NCESRC63_IOM6CE0 = 24
, GPIO_PINCFG63_NCESRC63_IOM6CE1 = 25
, GPIO_PINCFG63_NCESRC63_IOM6CE2 = 26
, GPIO_PINCFG63_NCESRC63_IOM6CE3 = 27
,
GPIO_PINCFG63_NCESRC63_IOM7CE0 = 28
, GPIO_PINCFG63_NCESRC63_IOM7CE1 = 29
, GPIO_PINCFG63_NCESRC63_IOM7CE2 = 30
, GPIO_PINCFG63_NCESRC63_IOM7CE3 = 31
,
GPIO_PINCFG63_NCESRC63_MSPI0CEN0 = 32
, GPIO_PINCFG63_NCESRC63_MSPI0CEN1 = 33
, GPIO_PINCFG63_NCESRC63_MSPI1CEN0 = 34
, GPIO_PINCFG63_NCESRC63_MSPI1CEN1 = 35
,
GPIO_PINCFG63_NCESRC63_MSPI2CEN0 = 36
, GPIO_PINCFG63_NCESRC63_MSPI2CEN1 = 37
, GPIO_PINCFG63_NCESRC63_DC_DPI_DE = 38
, GPIO_PINCFG63_NCESRC63_DISP_CONT_CSX = 39
,
GPIO_PINCFG63_NCESRC63_DC_SPI_CS_N = 40
, GPIO_PINCFG63_NCESRC63_DC_QSPI_CS_N = 41
, GPIO_PINCFG63_NCESRC63_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG63_PULLCFG63_Enum {
GPIO_PINCFG63_PULLCFG63_DIS = 0
, GPIO_PINCFG63_PULLCFG63_PD50K = 1
, GPIO_PINCFG63_PULLCFG63_PU15K = 2
, GPIO_PINCFG63_PULLCFG63_PU6K = 3
,
GPIO_PINCFG63_PULLCFG63_PU12K = 4
, GPIO_PINCFG63_PULLCFG63_PU24K = 5
, GPIO_PINCFG63_PULLCFG63_PU50K = 6
, GPIO_PINCFG63_PULLCFG63_PU100K = 7
} |
| |
| enum | GPIO_PINCFG63_DS63_Enum { GPIO_PINCFG63_DS63_0P1X = 0
, GPIO_PINCFG63_DS63_0P5X = 1
, GPIO_PINCFG63_DS63_0P75X = 2
, GPIO_PINCFG63_DS63_1P0X = 3
} |
| |
| enum | GPIO_PINCFG63_OUTCFG63_Enum { GPIO_PINCFG63_OUTCFG63_DIS = 0
, GPIO_PINCFG63_OUTCFG63_PUSHPULL = 1
, GPIO_PINCFG63_OUTCFG63_OD = 2
, GPIO_PINCFG63_OUTCFG63_TS = 3
} |
| |
| enum | GPIO_PINCFG63_IRPTEN63_Enum { GPIO_PINCFG63_IRPTEN63_DIS = 0
, GPIO_PINCFG63_IRPTEN63_INTFALL = 1
, GPIO_PINCFG63_IRPTEN63_INTRISE = 2
, GPIO_PINCFG63_IRPTEN63_INTANY = 3
} |
| |
| enum | GPIO_PINCFG63_FNCSEL63_Enum {
GPIO_PINCFG63_FNCSEL63_M6MISO = 0
, GPIO_PINCFG63_FNCSEL63_CLKOUT = 1
, GPIO_PINCFG63_FNCSEL63_I2S1_WS = 2
, GPIO_PINCFG63_FNCSEL63_GPIO = 3
,
GPIO_PINCFG63_FNCSEL63_UART2RX = 4
, GPIO_PINCFG63_FNCSEL63_UART3RX = 5
, GPIO_PINCFG63_FNCSEL63_CT63 = 6
, GPIO_PINCFG63_FNCSEL63_NCE63 = 7
,
GPIO_PINCFG63_FNCSEL63_OBSBUS15 = 8
, GPIO_PINCFG63_FNCSEL63_DISP_TE = 9
, GPIO_PINCFG63_FNCSEL63_RESERVED10 = 10
, GPIO_PINCFG63_FNCSEL63_FPIO = 11
,
GPIO_PINCFG63_FNCSEL63_RESERVED12 = 12
, GPIO_PINCFG63_FNCSEL63_RESERVED13 = 13
, GPIO_PINCFG63_FNCSEL63_RESERVED14 = 14
, GPIO_PINCFG63_FNCSEL63_RESERVED15 = 15
} |
| |
| enum | GPIO_PINCFG64_NCEPOL64_Enum { GPIO_PINCFG64_NCEPOL64_LOW = 0
, GPIO_PINCFG64_NCEPOL64_HIGH = 1
} |
| |
| enum | GPIO_PINCFG64_NCESRC64_Enum {
GPIO_PINCFG64_NCESRC64_IOM0CE0 = 0
, GPIO_PINCFG64_NCESRC64_IOM0CE1 = 1
, GPIO_PINCFG64_NCESRC64_IOM0CE2 = 2
, GPIO_PINCFG64_NCESRC64_IOM0CE3 = 3
,
GPIO_PINCFG64_NCESRC64_IOM1CE0 = 4
, GPIO_PINCFG64_NCESRC64_IOM1CE1 = 5
, GPIO_PINCFG64_NCESRC64_IOM1CE2 = 6
, GPIO_PINCFG64_NCESRC64_IOM1CE3 = 7
,
GPIO_PINCFG64_NCESRC64_IOM2CE0 = 8
, GPIO_PINCFG64_NCESRC64_IOM2CE1 = 9
, GPIO_PINCFG64_NCESRC64_IOM2CE2 = 10
, GPIO_PINCFG64_NCESRC64_IOM2CE3 = 11
,
GPIO_PINCFG64_NCESRC64_IOM3CE0 = 12
, GPIO_PINCFG64_NCESRC64_IOM3CE1 = 13
, GPIO_PINCFG64_NCESRC64_IOM3CE2 = 14
, GPIO_PINCFG64_NCESRC64_IOM3CE3 = 15
,
GPIO_PINCFG64_NCESRC64_IOM4CE0 = 16
, GPIO_PINCFG64_NCESRC64_IOM4CE1 = 17
, GPIO_PINCFG64_NCESRC64_IOM4CE2 = 18
, GPIO_PINCFG64_NCESRC64_IOM4CE3 = 19
,
GPIO_PINCFG64_NCESRC64_IOM5CE0 = 20
, GPIO_PINCFG64_NCESRC64_IOM5CE1 = 21
, GPIO_PINCFG64_NCESRC64_IOM5CE2 = 22
, GPIO_PINCFG64_NCESRC64_IOM5CE3 = 23
,
GPIO_PINCFG64_NCESRC64_IOM6CE0 = 24
, GPIO_PINCFG64_NCESRC64_IOM6CE1 = 25
, GPIO_PINCFG64_NCESRC64_IOM6CE2 = 26
, GPIO_PINCFG64_NCESRC64_IOM6CE3 = 27
,
GPIO_PINCFG64_NCESRC64_IOM7CE0 = 28
, GPIO_PINCFG64_NCESRC64_IOM7CE1 = 29
, GPIO_PINCFG64_NCESRC64_IOM7CE2 = 30
, GPIO_PINCFG64_NCESRC64_IOM7CE3 = 31
,
GPIO_PINCFG64_NCESRC64_MSPI0CEN0 = 32
, GPIO_PINCFG64_NCESRC64_MSPI0CEN1 = 33
, GPIO_PINCFG64_NCESRC64_MSPI1CEN0 = 34
, GPIO_PINCFG64_NCESRC64_MSPI1CEN1 = 35
,
GPIO_PINCFG64_NCESRC64_MSPI2CEN0 = 36
, GPIO_PINCFG64_NCESRC64_MSPI2CEN1 = 37
, GPIO_PINCFG64_NCESRC64_DC_DPI_DE = 38
, GPIO_PINCFG64_NCESRC64_DISP_CONT_CSX = 39
,
GPIO_PINCFG64_NCESRC64_DC_SPI_CS_N = 40
, GPIO_PINCFG64_NCESRC64_DC_QSPI_CS_N = 41
, GPIO_PINCFG64_NCESRC64_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG64_PULLCFG64_Enum {
GPIO_PINCFG64_PULLCFG64_DIS = 0
, GPIO_PINCFG64_PULLCFG64_PD50K = 1
, GPIO_PINCFG64_PULLCFG64_PU15K = 2
, GPIO_PINCFG64_PULLCFG64_PU6K = 3
,
GPIO_PINCFG64_PULLCFG64_PU12K = 4
, GPIO_PINCFG64_PULLCFG64_PU24K = 5
, GPIO_PINCFG64_PULLCFG64_PU50K = 6
, GPIO_PINCFG64_PULLCFG64_PU100K = 7
} |
| |
| enum | GPIO_PINCFG64_DS64_Enum { GPIO_PINCFG64_DS64_0P1X = 0
, GPIO_PINCFG64_DS64_0P5X = 1
, GPIO_PINCFG64_DS64_0P75X = 2
, GPIO_PINCFG64_DS64_1P0X = 3
} |
| |
| enum | GPIO_PINCFG64_OUTCFG64_Enum { GPIO_PINCFG64_OUTCFG64_DIS = 0
, GPIO_PINCFG64_OUTCFG64_PUSHPULL = 1
, GPIO_PINCFG64_OUTCFG64_OD = 2
, GPIO_PINCFG64_OUTCFG64_TS = 3
} |
| |
| enum | GPIO_PINCFG64_IRPTEN64_Enum { GPIO_PINCFG64_IRPTEN64_DIS = 0
, GPIO_PINCFG64_IRPTEN64_INTFALL = 1
, GPIO_PINCFG64_IRPTEN64_INTRISE = 2
, GPIO_PINCFG64_IRPTEN64_INTANY = 3
} |
| |
| enum | GPIO_PINCFG64_FNCSEL64_Enum {
GPIO_PINCFG64_FNCSEL64_MSPI0_0 = 0
, GPIO_PINCFG64_FNCSEL64_32KHzXT = 1
, GPIO_PINCFG64_FNCSEL64_SWO = 2
, GPIO_PINCFG64_FNCSEL64_GPIO = 3
,
GPIO_PINCFG64_FNCSEL64_UART0RTS = 4
, GPIO_PINCFG64_FNCSEL64_DISP_D0 = 5
, GPIO_PINCFG64_FNCSEL64_CT64 = 6
, GPIO_PINCFG64_FNCSEL64_NCE64 = 7
,
GPIO_PINCFG64_FNCSEL64_OBSBUS0 = 8
, GPIO_PINCFG64_FNCSEL64_I2S1_SDIN = 9
, GPIO_PINCFG64_FNCSEL64_RESERVED10 = 10
, GPIO_PINCFG64_FNCSEL64_FPIO = 11
,
GPIO_PINCFG64_FNCSEL64_RESERVED12 = 12
, GPIO_PINCFG64_FNCSEL64_RESERVED13 = 13
, GPIO_PINCFG64_FNCSEL64_RESERVED14 = 14
, GPIO_PINCFG64_FNCSEL64_RESERVED15 = 15
} |
| |
| enum | GPIO_PINCFG65_NCEPOL65_Enum { GPIO_PINCFG65_NCEPOL65_LOW = 0
, GPIO_PINCFG65_NCEPOL65_HIGH = 1
} |
| |
| enum | GPIO_PINCFG65_NCESRC65_Enum {
GPIO_PINCFG65_NCESRC65_IOM0CE0 = 0
, GPIO_PINCFG65_NCESRC65_IOM0CE1 = 1
, GPIO_PINCFG65_NCESRC65_IOM0CE2 = 2
, GPIO_PINCFG65_NCESRC65_IOM0CE3 = 3
,
GPIO_PINCFG65_NCESRC65_IOM1CE0 = 4
, GPIO_PINCFG65_NCESRC65_IOM1CE1 = 5
, GPIO_PINCFG65_NCESRC65_IOM1CE2 = 6
, GPIO_PINCFG65_NCESRC65_IOM1CE3 = 7
,
GPIO_PINCFG65_NCESRC65_IOM2CE0 = 8
, GPIO_PINCFG65_NCESRC65_IOM2CE1 = 9
, GPIO_PINCFG65_NCESRC65_IOM2CE2 = 10
, GPIO_PINCFG65_NCESRC65_IOM2CE3 = 11
,
GPIO_PINCFG65_NCESRC65_IOM3CE0 = 12
, GPIO_PINCFG65_NCESRC65_IOM3CE1 = 13
, GPIO_PINCFG65_NCESRC65_IOM3CE2 = 14
, GPIO_PINCFG65_NCESRC65_IOM3CE3 = 15
,
GPIO_PINCFG65_NCESRC65_IOM4CE0 = 16
, GPIO_PINCFG65_NCESRC65_IOM4CE1 = 17
, GPIO_PINCFG65_NCESRC65_IOM4CE2 = 18
, GPIO_PINCFG65_NCESRC65_IOM4CE3 = 19
,
GPIO_PINCFG65_NCESRC65_IOM5CE0 = 20
, GPIO_PINCFG65_NCESRC65_IOM5CE1 = 21
, GPIO_PINCFG65_NCESRC65_IOM5CE2 = 22
, GPIO_PINCFG65_NCESRC65_IOM5CE3 = 23
,
GPIO_PINCFG65_NCESRC65_IOM6CE0 = 24
, GPIO_PINCFG65_NCESRC65_IOM6CE1 = 25
, GPIO_PINCFG65_NCESRC65_IOM6CE2 = 26
, GPIO_PINCFG65_NCESRC65_IOM6CE3 = 27
,
GPIO_PINCFG65_NCESRC65_IOM7CE0 = 28
, GPIO_PINCFG65_NCESRC65_IOM7CE1 = 29
, GPIO_PINCFG65_NCESRC65_IOM7CE2 = 30
, GPIO_PINCFG65_NCESRC65_IOM7CE3 = 31
,
GPIO_PINCFG65_NCESRC65_MSPI0CEN0 = 32
, GPIO_PINCFG65_NCESRC65_MSPI0CEN1 = 33
, GPIO_PINCFG65_NCESRC65_MSPI1CEN0 = 34
, GPIO_PINCFG65_NCESRC65_MSPI1CEN1 = 35
,
GPIO_PINCFG65_NCESRC65_MSPI2CEN0 = 36
, GPIO_PINCFG65_NCESRC65_MSPI2CEN1 = 37
, GPIO_PINCFG65_NCESRC65_DC_DPI_DE = 38
, GPIO_PINCFG65_NCESRC65_DISP_CONT_CSX = 39
,
GPIO_PINCFG65_NCESRC65_DC_SPI_CS_N = 40
, GPIO_PINCFG65_NCESRC65_DC_QSPI_CS_N = 41
, GPIO_PINCFG65_NCESRC65_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG65_PULLCFG65_Enum {
GPIO_PINCFG65_PULLCFG65_DIS = 0
, GPIO_PINCFG65_PULLCFG65_PD50K = 1
, GPIO_PINCFG65_PULLCFG65_PU15K = 2
, GPIO_PINCFG65_PULLCFG65_PU6K = 3
,
GPIO_PINCFG65_PULLCFG65_PU12K = 4
, GPIO_PINCFG65_PULLCFG65_PU24K = 5
, GPIO_PINCFG65_PULLCFG65_PU50K = 6
, GPIO_PINCFG65_PULLCFG65_PU100K = 7
} |
| |
| enum | GPIO_PINCFG65_DS65_Enum { GPIO_PINCFG65_DS65_0P1X = 0
, GPIO_PINCFG65_DS65_0P5X = 1
, GPIO_PINCFG65_DS65_0P75X = 2
, GPIO_PINCFG65_DS65_1P0X = 3
} |
| |
| enum | GPIO_PINCFG65_OUTCFG65_Enum { GPIO_PINCFG65_OUTCFG65_DIS = 0
, GPIO_PINCFG65_OUTCFG65_PUSHPULL = 1
, GPIO_PINCFG65_OUTCFG65_OD = 2
, GPIO_PINCFG65_OUTCFG65_TS = 3
} |
| |
| enum | GPIO_PINCFG65_IRPTEN65_Enum { GPIO_PINCFG65_IRPTEN65_DIS = 0
, GPIO_PINCFG65_IRPTEN65_INTFALL = 1
, GPIO_PINCFG65_IRPTEN65_INTRISE = 2
, GPIO_PINCFG65_IRPTEN65_INTANY = 3
} |
| |
| enum | GPIO_PINCFG65_FNCSEL65_Enum {
GPIO_PINCFG65_FNCSEL65_MSPI0_1 = 0
, GPIO_PINCFG65_FNCSEL65_32KHzXT = 1
, GPIO_PINCFG65_FNCSEL65_SWO = 2
, GPIO_PINCFG65_FNCSEL65_GPIO = 3
,
GPIO_PINCFG65_FNCSEL65_UART0CTS = 4
, GPIO_PINCFG65_FNCSEL65_DISP_D1 = 5
, GPIO_PINCFG65_FNCSEL65_CT65 = 6
, GPIO_PINCFG65_FNCSEL65_NCE65 = 7
,
GPIO_PINCFG65_FNCSEL65_OBSBUS1 = 8
, GPIO_PINCFG65_FNCSEL65_RESERVED9 = 9
, GPIO_PINCFG65_FNCSEL65_RESERVED10 = 10
, GPIO_PINCFG65_FNCSEL65_FPIO = 11
,
GPIO_PINCFG65_FNCSEL65_RESERVED12 = 12
, GPIO_PINCFG65_FNCSEL65_RESERVED13 = 13
, GPIO_PINCFG65_FNCSEL65_RESERVED14 = 14
, GPIO_PINCFG65_FNCSEL65_RESERVED15 = 15
} |
| |
| enum | GPIO_PINCFG66_NCEPOL66_Enum { GPIO_PINCFG66_NCEPOL66_LOW = 0
, GPIO_PINCFG66_NCEPOL66_HIGH = 1
} |
| |
| enum | GPIO_PINCFG66_NCESRC66_Enum {
GPIO_PINCFG66_NCESRC66_IOM0CE0 = 0
, GPIO_PINCFG66_NCESRC66_IOM0CE1 = 1
, GPIO_PINCFG66_NCESRC66_IOM0CE2 = 2
, GPIO_PINCFG66_NCESRC66_IOM0CE3 = 3
,
GPIO_PINCFG66_NCESRC66_IOM1CE0 = 4
, GPIO_PINCFG66_NCESRC66_IOM1CE1 = 5
, GPIO_PINCFG66_NCESRC66_IOM1CE2 = 6
, GPIO_PINCFG66_NCESRC66_IOM1CE3 = 7
,
GPIO_PINCFG66_NCESRC66_IOM2CE0 = 8
, GPIO_PINCFG66_NCESRC66_IOM2CE1 = 9
, GPIO_PINCFG66_NCESRC66_IOM2CE2 = 10
, GPIO_PINCFG66_NCESRC66_IOM2CE3 = 11
,
GPIO_PINCFG66_NCESRC66_IOM3CE0 = 12
, GPIO_PINCFG66_NCESRC66_IOM3CE1 = 13
, GPIO_PINCFG66_NCESRC66_IOM3CE2 = 14
, GPIO_PINCFG66_NCESRC66_IOM3CE3 = 15
,
GPIO_PINCFG66_NCESRC66_IOM4CE0 = 16
, GPIO_PINCFG66_NCESRC66_IOM4CE1 = 17
, GPIO_PINCFG66_NCESRC66_IOM4CE2 = 18
, GPIO_PINCFG66_NCESRC66_IOM4CE3 = 19
,
GPIO_PINCFG66_NCESRC66_IOM5CE0 = 20
, GPIO_PINCFG66_NCESRC66_IOM5CE1 = 21
, GPIO_PINCFG66_NCESRC66_IOM5CE2 = 22
, GPIO_PINCFG66_NCESRC66_IOM5CE3 = 23
,
GPIO_PINCFG66_NCESRC66_IOM6CE0 = 24
, GPIO_PINCFG66_NCESRC66_IOM6CE1 = 25
, GPIO_PINCFG66_NCESRC66_IOM6CE2 = 26
, GPIO_PINCFG66_NCESRC66_IOM6CE3 = 27
,
GPIO_PINCFG66_NCESRC66_IOM7CE0 = 28
, GPIO_PINCFG66_NCESRC66_IOM7CE1 = 29
, GPIO_PINCFG66_NCESRC66_IOM7CE2 = 30
, GPIO_PINCFG66_NCESRC66_IOM7CE3 = 31
,
GPIO_PINCFG66_NCESRC66_MSPI0CEN0 = 32
, GPIO_PINCFG66_NCESRC66_MSPI0CEN1 = 33
, GPIO_PINCFG66_NCESRC66_MSPI1CEN0 = 34
, GPIO_PINCFG66_NCESRC66_MSPI1CEN1 = 35
,
GPIO_PINCFG66_NCESRC66_MSPI2CEN0 = 36
, GPIO_PINCFG66_NCESRC66_MSPI2CEN1 = 37
, GPIO_PINCFG66_NCESRC66_DC_DPI_DE = 38
, GPIO_PINCFG66_NCESRC66_DISP_CONT_CSX = 39
,
GPIO_PINCFG66_NCESRC66_DC_SPI_CS_N = 40
, GPIO_PINCFG66_NCESRC66_DC_QSPI_CS_N = 41
, GPIO_PINCFG66_NCESRC66_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG66_PULLCFG66_Enum {
GPIO_PINCFG66_PULLCFG66_DIS = 0
, GPIO_PINCFG66_PULLCFG66_PD50K = 1
, GPIO_PINCFG66_PULLCFG66_PU15K = 2
, GPIO_PINCFG66_PULLCFG66_PU6K = 3
,
GPIO_PINCFG66_PULLCFG66_PU12K = 4
, GPIO_PINCFG66_PULLCFG66_PU24K = 5
, GPIO_PINCFG66_PULLCFG66_PU50K = 6
, GPIO_PINCFG66_PULLCFG66_PU100K = 7
} |
| |
| enum | GPIO_PINCFG66_DS66_Enum { GPIO_PINCFG66_DS66_0P1X = 0
, GPIO_PINCFG66_DS66_0P5X = 1
, GPIO_PINCFG66_DS66_0P75X = 2
, GPIO_PINCFG66_DS66_1P0X = 3
} |
| |
| enum | GPIO_PINCFG66_OUTCFG66_Enum { GPIO_PINCFG66_OUTCFG66_DIS = 0
, GPIO_PINCFG66_OUTCFG66_PUSHPULL = 1
, GPIO_PINCFG66_OUTCFG66_OD = 2
, GPIO_PINCFG66_OUTCFG66_TS = 3
} |
| |
| enum | GPIO_PINCFG66_IRPTEN66_Enum { GPIO_PINCFG66_IRPTEN66_DIS = 0
, GPIO_PINCFG66_IRPTEN66_INTFALL = 1
, GPIO_PINCFG66_IRPTEN66_INTRISE = 2
, GPIO_PINCFG66_IRPTEN66_INTANY = 3
} |
| |
| enum | GPIO_PINCFG66_FNCSEL66_Enum {
GPIO_PINCFG66_FNCSEL66_MSPI0_2 = 0
, GPIO_PINCFG66_FNCSEL66_CLKOUT = 1
, GPIO_PINCFG66_FNCSEL66_SWO = 2
, GPIO_PINCFG66_FNCSEL66_GPIO = 3
,
GPIO_PINCFG66_FNCSEL66_UART0TX = 4
, GPIO_PINCFG66_FNCSEL66_DISP_D2 = 5
, GPIO_PINCFG66_FNCSEL66_CT66 = 6
, GPIO_PINCFG66_FNCSEL66_NCE66 = 7
,
GPIO_PINCFG66_FNCSEL66_OBSBUS2 = 8
, GPIO_PINCFG66_FNCSEL66_RESERVED9 = 9
, GPIO_PINCFG66_FNCSEL66_RESERVED10 = 10
, GPIO_PINCFG66_FNCSEL66_FPIO = 11
,
GPIO_PINCFG66_FNCSEL66_RESERVED12 = 12
, GPIO_PINCFG66_FNCSEL66_RESERVED13 = 13
, GPIO_PINCFG66_FNCSEL66_RESERVED14 = 14
, GPIO_PINCFG66_FNCSEL66_RESERVED15 = 15
} |
| |
| enum | GPIO_PINCFG67_NCEPOL67_Enum { GPIO_PINCFG67_NCEPOL67_LOW = 0
, GPIO_PINCFG67_NCEPOL67_HIGH = 1
} |
| |
| enum | GPIO_PINCFG67_NCESRC67_Enum {
GPIO_PINCFG67_NCESRC67_IOM0CE0 = 0
, GPIO_PINCFG67_NCESRC67_IOM0CE1 = 1
, GPIO_PINCFG67_NCESRC67_IOM0CE2 = 2
, GPIO_PINCFG67_NCESRC67_IOM0CE3 = 3
,
GPIO_PINCFG67_NCESRC67_IOM1CE0 = 4
, GPIO_PINCFG67_NCESRC67_IOM1CE1 = 5
, GPIO_PINCFG67_NCESRC67_IOM1CE2 = 6
, GPIO_PINCFG67_NCESRC67_IOM1CE3 = 7
,
GPIO_PINCFG67_NCESRC67_IOM2CE0 = 8
, GPIO_PINCFG67_NCESRC67_IOM2CE1 = 9
, GPIO_PINCFG67_NCESRC67_IOM2CE2 = 10
, GPIO_PINCFG67_NCESRC67_IOM2CE3 = 11
,
GPIO_PINCFG67_NCESRC67_IOM3CE0 = 12
, GPIO_PINCFG67_NCESRC67_IOM3CE1 = 13
, GPIO_PINCFG67_NCESRC67_IOM3CE2 = 14
, GPIO_PINCFG67_NCESRC67_IOM3CE3 = 15
,
GPIO_PINCFG67_NCESRC67_IOM4CE0 = 16
, GPIO_PINCFG67_NCESRC67_IOM4CE1 = 17
, GPIO_PINCFG67_NCESRC67_IOM4CE2 = 18
, GPIO_PINCFG67_NCESRC67_IOM4CE3 = 19
,
GPIO_PINCFG67_NCESRC67_IOM5CE0 = 20
, GPIO_PINCFG67_NCESRC67_IOM5CE1 = 21
, GPIO_PINCFG67_NCESRC67_IOM5CE2 = 22
, GPIO_PINCFG67_NCESRC67_IOM5CE3 = 23
,
GPIO_PINCFG67_NCESRC67_IOM6CE0 = 24
, GPIO_PINCFG67_NCESRC67_IOM6CE1 = 25
, GPIO_PINCFG67_NCESRC67_IOM6CE2 = 26
, GPIO_PINCFG67_NCESRC67_IOM6CE3 = 27
,
GPIO_PINCFG67_NCESRC67_IOM7CE0 = 28
, GPIO_PINCFG67_NCESRC67_IOM7CE1 = 29
, GPIO_PINCFG67_NCESRC67_IOM7CE2 = 30
, GPIO_PINCFG67_NCESRC67_IOM7CE3 = 31
,
GPIO_PINCFG67_NCESRC67_MSPI0CEN0 = 32
, GPIO_PINCFG67_NCESRC67_MSPI0CEN1 = 33
, GPIO_PINCFG67_NCESRC67_MSPI1CEN0 = 34
, GPIO_PINCFG67_NCESRC67_MSPI1CEN1 = 35
,
GPIO_PINCFG67_NCESRC67_MSPI2CEN0 = 36
, GPIO_PINCFG67_NCESRC67_MSPI2CEN1 = 37
, GPIO_PINCFG67_NCESRC67_DC_DPI_DE = 38
, GPIO_PINCFG67_NCESRC67_DISP_CONT_CSX = 39
,
GPIO_PINCFG67_NCESRC67_DC_SPI_CS_N = 40
, GPIO_PINCFG67_NCESRC67_DC_QSPI_CS_N = 41
, GPIO_PINCFG67_NCESRC67_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG67_PULLCFG67_Enum {
GPIO_PINCFG67_PULLCFG67_DIS = 0
, GPIO_PINCFG67_PULLCFG67_PD50K = 1
, GPIO_PINCFG67_PULLCFG67_PU15K = 2
, GPIO_PINCFG67_PULLCFG67_PU6K = 3
,
GPIO_PINCFG67_PULLCFG67_PU12K = 4
, GPIO_PINCFG67_PULLCFG67_PU24K = 5
, GPIO_PINCFG67_PULLCFG67_PU50K = 6
, GPIO_PINCFG67_PULLCFG67_PU100K = 7
} |
| |
| enum | GPIO_PINCFG67_DS67_Enum { GPIO_PINCFG67_DS67_0P1X = 0
, GPIO_PINCFG67_DS67_0P5X = 1
, GPIO_PINCFG67_DS67_0P75X = 2
, GPIO_PINCFG67_DS67_1P0X = 3
} |
| |
| enum | GPIO_PINCFG67_OUTCFG67_Enum { GPIO_PINCFG67_OUTCFG67_DIS = 0
, GPIO_PINCFG67_OUTCFG67_PUSHPULL = 1
, GPIO_PINCFG67_OUTCFG67_OD = 2
, GPIO_PINCFG67_OUTCFG67_TS = 3
} |
| |
| enum | GPIO_PINCFG67_IRPTEN67_Enum { GPIO_PINCFG67_IRPTEN67_DIS = 0
, GPIO_PINCFG67_IRPTEN67_INTFALL = 1
, GPIO_PINCFG67_IRPTEN67_INTRISE = 2
, GPIO_PINCFG67_IRPTEN67_INTANY = 3
} |
| |
| enum | GPIO_PINCFG67_FNCSEL67_Enum {
GPIO_PINCFG67_FNCSEL67_MSPI0_3 = 0
, GPIO_PINCFG67_FNCSEL67_CLKOUT = 1
, GPIO_PINCFG67_FNCSEL67_SWO = 2
, GPIO_PINCFG67_FNCSEL67_GPIO = 3
,
GPIO_PINCFG67_FNCSEL67_UART2TX = 4
, GPIO_PINCFG67_FNCSEL67_DISP_D3 = 5
, GPIO_PINCFG67_FNCSEL67_CT67 = 6
, GPIO_PINCFG67_FNCSEL67_NCE67 = 7
,
GPIO_PINCFG67_FNCSEL67_OBSBUS3 = 8
, GPIO_PINCFG67_FNCSEL67_RESERVED9 = 9
, GPIO_PINCFG67_FNCSEL67_RESERVED10 = 10
, GPIO_PINCFG67_FNCSEL67_FPIO = 11
,
GPIO_PINCFG67_FNCSEL67_RESERVED12 = 12
, GPIO_PINCFG67_FNCSEL67_RESERVED13 = 13
, GPIO_PINCFG67_FNCSEL67_RESERVED14 = 14
, GPIO_PINCFG67_FNCSEL67_RESERVED15 = 15
} |
| |
| enum | GPIO_PINCFG68_NCEPOL68_Enum { GPIO_PINCFG68_NCEPOL68_LOW = 0
, GPIO_PINCFG68_NCEPOL68_HIGH = 1
} |
| |
| enum | GPIO_PINCFG68_NCESRC68_Enum {
GPIO_PINCFG68_NCESRC68_IOM0CE0 = 0
, GPIO_PINCFG68_NCESRC68_IOM0CE1 = 1
, GPIO_PINCFG68_NCESRC68_IOM0CE2 = 2
, GPIO_PINCFG68_NCESRC68_IOM0CE3 = 3
,
GPIO_PINCFG68_NCESRC68_IOM1CE0 = 4
, GPIO_PINCFG68_NCESRC68_IOM1CE1 = 5
, GPIO_PINCFG68_NCESRC68_IOM1CE2 = 6
, GPIO_PINCFG68_NCESRC68_IOM1CE3 = 7
,
GPIO_PINCFG68_NCESRC68_IOM2CE0 = 8
, GPIO_PINCFG68_NCESRC68_IOM2CE1 = 9
, GPIO_PINCFG68_NCESRC68_IOM2CE2 = 10
, GPIO_PINCFG68_NCESRC68_IOM2CE3 = 11
,
GPIO_PINCFG68_NCESRC68_IOM3CE0 = 12
, GPIO_PINCFG68_NCESRC68_IOM3CE1 = 13
, GPIO_PINCFG68_NCESRC68_IOM3CE2 = 14
, GPIO_PINCFG68_NCESRC68_IOM3CE3 = 15
,
GPIO_PINCFG68_NCESRC68_IOM4CE0 = 16
, GPIO_PINCFG68_NCESRC68_IOM4CE1 = 17
, GPIO_PINCFG68_NCESRC68_IOM4CE2 = 18
, GPIO_PINCFG68_NCESRC68_IOM4CE3 = 19
,
GPIO_PINCFG68_NCESRC68_IOM5CE0 = 20
, GPIO_PINCFG68_NCESRC68_IOM5CE1 = 21
, GPIO_PINCFG68_NCESRC68_IOM5CE2 = 22
, GPIO_PINCFG68_NCESRC68_IOM5CE3 = 23
,
GPIO_PINCFG68_NCESRC68_IOM6CE0 = 24
, GPIO_PINCFG68_NCESRC68_IOM6CE1 = 25
, GPIO_PINCFG68_NCESRC68_IOM6CE2 = 26
, GPIO_PINCFG68_NCESRC68_IOM6CE3 = 27
,
GPIO_PINCFG68_NCESRC68_IOM7CE0 = 28
, GPIO_PINCFG68_NCESRC68_IOM7CE1 = 29
, GPIO_PINCFG68_NCESRC68_IOM7CE2 = 30
, GPIO_PINCFG68_NCESRC68_IOM7CE3 = 31
,
GPIO_PINCFG68_NCESRC68_MSPI0CEN0 = 32
, GPIO_PINCFG68_NCESRC68_MSPI0CEN1 = 33
, GPIO_PINCFG68_NCESRC68_MSPI1CEN0 = 34
, GPIO_PINCFG68_NCESRC68_MSPI1CEN1 = 35
,
GPIO_PINCFG68_NCESRC68_MSPI2CEN0 = 36
, GPIO_PINCFG68_NCESRC68_MSPI2CEN1 = 37
, GPIO_PINCFG68_NCESRC68_DC_DPI_DE = 38
, GPIO_PINCFG68_NCESRC68_DISP_CONT_CSX = 39
,
GPIO_PINCFG68_NCESRC68_DC_SPI_CS_N = 40
, GPIO_PINCFG68_NCESRC68_DC_QSPI_CS_N = 41
, GPIO_PINCFG68_NCESRC68_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG68_PULLCFG68_Enum {
GPIO_PINCFG68_PULLCFG68_DIS = 0
, GPIO_PINCFG68_PULLCFG68_PD50K = 1
, GPIO_PINCFG68_PULLCFG68_PU15K = 2
, GPIO_PINCFG68_PULLCFG68_PU6K = 3
,
GPIO_PINCFG68_PULLCFG68_PU12K = 4
, GPIO_PINCFG68_PULLCFG68_PU24K = 5
, GPIO_PINCFG68_PULLCFG68_PU50K = 6
, GPIO_PINCFG68_PULLCFG68_PU100K = 7
} |
| |
| enum | GPIO_PINCFG68_DS68_Enum { GPIO_PINCFG68_DS68_0P1X = 0
, GPIO_PINCFG68_DS68_0P5X = 1
, GPIO_PINCFG68_DS68_0P75X = 2
, GPIO_PINCFG68_DS68_1P0X = 3
} |
| |
| enum | GPIO_PINCFG68_OUTCFG68_Enum { GPIO_PINCFG68_OUTCFG68_DIS = 0
, GPIO_PINCFG68_OUTCFG68_PUSHPULL = 1
, GPIO_PINCFG68_OUTCFG68_OD = 2
, GPIO_PINCFG68_OUTCFG68_TS = 3
} |
| |
| enum | GPIO_PINCFG68_IRPTEN68_Enum { GPIO_PINCFG68_IRPTEN68_DIS = 0
, GPIO_PINCFG68_IRPTEN68_INTFALL = 1
, GPIO_PINCFG68_IRPTEN68_INTRISE = 2
, GPIO_PINCFG68_IRPTEN68_INTANY = 3
} |
| |
| enum | GPIO_PINCFG68_FNCSEL68_Enum {
GPIO_PINCFG68_FNCSEL68_MSPI0_4 = 0
, GPIO_PINCFG68_FNCSEL68_SWO = 1
, GPIO_PINCFG68_FNCSEL68_RESERVED2 = 2
, GPIO_PINCFG68_FNCSEL68_GPIO = 3
,
GPIO_PINCFG68_FNCSEL68_UART0RX = 4
, GPIO_PINCFG68_FNCSEL68_DISP_D4 = 5
, GPIO_PINCFG68_FNCSEL68_CT68 = 6
, GPIO_PINCFG68_FNCSEL68_NCE68 = 7
,
GPIO_PINCFG68_FNCSEL68_OBSBUS4 = 8
, GPIO_PINCFG68_FNCSEL68_RESERVED9 = 9
, GPIO_PINCFG68_FNCSEL68_RESERVED10 = 10
, GPIO_PINCFG68_FNCSEL68_FPIO = 11
,
GPIO_PINCFG68_FNCSEL68_RESERVED12 = 12
, GPIO_PINCFG68_FNCSEL68_RESERVED13 = 13
, GPIO_PINCFG68_FNCSEL68_RESERVED14 = 14
, GPIO_PINCFG68_FNCSEL68_RESERVED15 = 15
} |
| |
| enum | GPIO_PINCFG69_NCEPOL69_Enum { GPIO_PINCFG69_NCEPOL69_LOW = 0
, GPIO_PINCFG69_NCEPOL69_HIGH = 1
} |
| |
| enum | GPIO_PINCFG69_NCESRC69_Enum {
GPIO_PINCFG69_NCESRC69_IOM0CE0 = 0
, GPIO_PINCFG69_NCESRC69_IOM0CE1 = 1
, GPIO_PINCFG69_NCESRC69_IOM0CE2 = 2
, GPIO_PINCFG69_NCESRC69_IOM0CE3 = 3
,
GPIO_PINCFG69_NCESRC69_IOM1CE0 = 4
, GPIO_PINCFG69_NCESRC69_IOM1CE1 = 5
, GPIO_PINCFG69_NCESRC69_IOM1CE2 = 6
, GPIO_PINCFG69_NCESRC69_IOM1CE3 = 7
,
GPIO_PINCFG69_NCESRC69_IOM2CE0 = 8
, GPIO_PINCFG69_NCESRC69_IOM2CE1 = 9
, GPIO_PINCFG69_NCESRC69_IOM2CE2 = 10
, GPIO_PINCFG69_NCESRC69_IOM2CE3 = 11
,
GPIO_PINCFG69_NCESRC69_IOM3CE0 = 12
, GPIO_PINCFG69_NCESRC69_IOM3CE1 = 13
, GPIO_PINCFG69_NCESRC69_IOM3CE2 = 14
, GPIO_PINCFG69_NCESRC69_IOM3CE3 = 15
,
GPIO_PINCFG69_NCESRC69_IOM4CE0 = 16
, GPIO_PINCFG69_NCESRC69_IOM4CE1 = 17
, GPIO_PINCFG69_NCESRC69_IOM4CE2 = 18
, GPIO_PINCFG69_NCESRC69_IOM4CE3 = 19
,
GPIO_PINCFG69_NCESRC69_IOM5CE0 = 20
, GPIO_PINCFG69_NCESRC69_IOM5CE1 = 21
, GPIO_PINCFG69_NCESRC69_IOM5CE2 = 22
, GPIO_PINCFG69_NCESRC69_IOM5CE3 = 23
,
GPIO_PINCFG69_NCESRC69_IOM6CE0 = 24
, GPIO_PINCFG69_NCESRC69_IOM6CE1 = 25
, GPIO_PINCFG69_NCESRC69_IOM6CE2 = 26
, GPIO_PINCFG69_NCESRC69_IOM6CE3 = 27
,
GPIO_PINCFG69_NCESRC69_IOM7CE0 = 28
, GPIO_PINCFG69_NCESRC69_IOM7CE1 = 29
, GPIO_PINCFG69_NCESRC69_IOM7CE2 = 30
, GPIO_PINCFG69_NCESRC69_IOM7CE3 = 31
,
GPIO_PINCFG69_NCESRC69_MSPI0CEN0 = 32
, GPIO_PINCFG69_NCESRC69_MSPI0CEN1 = 33
, GPIO_PINCFG69_NCESRC69_MSPI1CEN0 = 34
, GPIO_PINCFG69_NCESRC69_MSPI1CEN1 = 35
,
GPIO_PINCFG69_NCESRC69_MSPI2CEN0 = 36
, GPIO_PINCFG69_NCESRC69_MSPI2CEN1 = 37
, GPIO_PINCFG69_NCESRC69_DC_DPI_DE = 38
, GPIO_PINCFG69_NCESRC69_DISP_CONT_CSX = 39
,
GPIO_PINCFG69_NCESRC69_DC_SPI_CS_N = 40
, GPIO_PINCFG69_NCESRC69_DC_QSPI_CS_N = 41
, GPIO_PINCFG69_NCESRC69_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG69_PULLCFG69_Enum {
GPIO_PINCFG69_PULLCFG69_DIS = 0
, GPIO_PINCFG69_PULLCFG69_PD50K = 1
, GPIO_PINCFG69_PULLCFG69_PU15K = 2
, GPIO_PINCFG69_PULLCFG69_PU6K = 3
,
GPIO_PINCFG69_PULLCFG69_PU12K = 4
, GPIO_PINCFG69_PULLCFG69_PU24K = 5
, GPIO_PINCFG69_PULLCFG69_PU50K = 6
, GPIO_PINCFG69_PULLCFG69_PU100K = 7
} |
| |
| enum | GPIO_PINCFG69_DS69_Enum { GPIO_PINCFG69_DS69_0P1X = 0
, GPIO_PINCFG69_DS69_0P5X = 1
, GPIO_PINCFG69_DS69_0P75X = 2
, GPIO_PINCFG69_DS69_1P0X = 3
} |
| |
| enum | GPIO_PINCFG69_OUTCFG69_Enum { GPIO_PINCFG69_OUTCFG69_DIS = 0
, GPIO_PINCFG69_OUTCFG69_PUSHPULL = 1
, GPIO_PINCFG69_OUTCFG69_OD = 2
, GPIO_PINCFG69_OUTCFG69_TS = 3
} |
| |
| enum | GPIO_PINCFG69_IRPTEN69_Enum { GPIO_PINCFG69_IRPTEN69_DIS = 0
, GPIO_PINCFG69_IRPTEN69_INTFALL = 1
, GPIO_PINCFG69_IRPTEN69_INTRISE = 2
, GPIO_PINCFG69_IRPTEN69_INTANY = 3
} |
| |
| enum | GPIO_PINCFG69_FNCSEL69_Enum {
GPIO_PINCFG69_FNCSEL69_MSPI0_5 = 0
, GPIO_PINCFG69_FNCSEL69_32KHzXT = 1
, GPIO_PINCFG69_FNCSEL69_SWO = 2
, GPIO_PINCFG69_FNCSEL69_GPIO = 3
,
GPIO_PINCFG69_FNCSEL69_UART2RX = 4
, GPIO_PINCFG69_FNCSEL69_DISP_D5 = 5
, GPIO_PINCFG69_FNCSEL69_CT69 = 6
, GPIO_PINCFG69_FNCSEL69_NCE69 = 7
,
GPIO_PINCFG69_FNCSEL69_OBSBUS5 = 8
, GPIO_PINCFG69_FNCSEL69_RESERVED9 = 9
, GPIO_PINCFG69_FNCSEL69_RESERVED10 = 10
, GPIO_PINCFG69_FNCSEL69_FPIO = 11
,
GPIO_PINCFG69_FNCSEL69_RESERVED12 = 12
, GPIO_PINCFG69_FNCSEL69_RESERVED13 = 13
, GPIO_PINCFG69_FNCSEL69_RESERVED14 = 14
, GPIO_PINCFG69_FNCSEL69_RESERVED15 = 15
} |
| |
| enum | GPIO_PINCFG70_NCEPOL70_Enum { GPIO_PINCFG70_NCEPOL70_LOW = 0
, GPIO_PINCFG70_NCEPOL70_HIGH = 1
} |
| |
| enum | GPIO_PINCFG70_NCESRC70_Enum {
GPIO_PINCFG70_NCESRC70_IOM0CE0 = 0
, GPIO_PINCFG70_NCESRC70_IOM0CE1 = 1
, GPIO_PINCFG70_NCESRC70_IOM0CE2 = 2
, GPIO_PINCFG70_NCESRC70_IOM0CE3 = 3
,
GPIO_PINCFG70_NCESRC70_IOM1CE0 = 4
, GPIO_PINCFG70_NCESRC70_IOM1CE1 = 5
, GPIO_PINCFG70_NCESRC70_IOM1CE2 = 6
, GPIO_PINCFG70_NCESRC70_IOM1CE3 = 7
,
GPIO_PINCFG70_NCESRC70_IOM2CE0 = 8
, GPIO_PINCFG70_NCESRC70_IOM2CE1 = 9
, GPIO_PINCFG70_NCESRC70_IOM2CE2 = 10
, GPIO_PINCFG70_NCESRC70_IOM2CE3 = 11
,
GPIO_PINCFG70_NCESRC70_IOM3CE0 = 12
, GPIO_PINCFG70_NCESRC70_IOM3CE1 = 13
, GPIO_PINCFG70_NCESRC70_IOM3CE2 = 14
, GPIO_PINCFG70_NCESRC70_IOM3CE3 = 15
,
GPIO_PINCFG70_NCESRC70_IOM4CE0 = 16
, GPIO_PINCFG70_NCESRC70_IOM4CE1 = 17
, GPIO_PINCFG70_NCESRC70_IOM4CE2 = 18
, GPIO_PINCFG70_NCESRC70_IOM4CE3 = 19
,
GPIO_PINCFG70_NCESRC70_IOM5CE0 = 20
, GPIO_PINCFG70_NCESRC70_IOM5CE1 = 21
, GPIO_PINCFG70_NCESRC70_IOM5CE2 = 22
, GPIO_PINCFG70_NCESRC70_IOM5CE3 = 23
,
GPIO_PINCFG70_NCESRC70_IOM6CE0 = 24
, GPIO_PINCFG70_NCESRC70_IOM6CE1 = 25
, GPIO_PINCFG70_NCESRC70_IOM6CE2 = 26
, GPIO_PINCFG70_NCESRC70_IOM6CE3 = 27
,
GPIO_PINCFG70_NCESRC70_IOM7CE0 = 28
, GPIO_PINCFG70_NCESRC70_IOM7CE1 = 29
, GPIO_PINCFG70_NCESRC70_IOM7CE2 = 30
, GPIO_PINCFG70_NCESRC70_IOM7CE3 = 31
,
GPIO_PINCFG70_NCESRC70_MSPI0CEN0 = 32
, GPIO_PINCFG70_NCESRC70_MSPI0CEN1 = 33
, GPIO_PINCFG70_NCESRC70_MSPI1CEN0 = 34
, GPIO_PINCFG70_NCESRC70_MSPI1CEN1 = 35
,
GPIO_PINCFG70_NCESRC70_MSPI2CEN0 = 36
, GPIO_PINCFG70_NCESRC70_MSPI2CEN1 = 37
, GPIO_PINCFG70_NCESRC70_DC_DPI_DE = 38
, GPIO_PINCFG70_NCESRC70_DISP_CONT_CSX = 39
,
GPIO_PINCFG70_NCESRC70_DC_SPI_CS_N = 40
, GPIO_PINCFG70_NCESRC70_DC_QSPI_CS_N = 41
, GPIO_PINCFG70_NCESRC70_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG70_PULLCFG70_Enum {
GPIO_PINCFG70_PULLCFG70_DIS = 0
, GPIO_PINCFG70_PULLCFG70_PD50K = 1
, GPIO_PINCFG70_PULLCFG70_PU15K = 2
, GPIO_PINCFG70_PULLCFG70_PU6K = 3
,
GPIO_PINCFG70_PULLCFG70_PU12K = 4
, GPIO_PINCFG70_PULLCFG70_PU24K = 5
, GPIO_PINCFG70_PULLCFG70_PU50K = 6
, GPIO_PINCFG70_PULLCFG70_PU100K = 7
} |
| |
| enum | GPIO_PINCFG70_DS70_Enum { GPIO_PINCFG70_DS70_0P1X = 0
, GPIO_PINCFG70_DS70_0P5X = 1
, GPIO_PINCFG70_DS70_0P75X = 2
, GPIO_PINCFG70_DS70_1P0X = 3
} |
| |
| enum | GPIO_PINCFG70_OUTCFG70_Enum { GPIO_PINCFG70_OUTCFG70_DIS = 0
, GPIO_PINCFG70_OUTCFG70_PUSHPULL = 1
, GPIO_PINCFG70_OUTCFG70_OD = 2
, GPIO_PINCFG70_OUTCFG70_TS = 3
} |
| |
| enum | GPIO_PINCFG70_IRPTEN70_Enum { GPIO_PINCFG70_IRPTEN70_DIS = 0
, GPIO_PINCFG70_IRPTEN70_INTFALL = 1
, GPIO_PINCFG70_IRPTEN70_INTRISE = 2
, GPIO_PINCFG70_IRPTEN70_INTANY = 3
} |
| |
| enum | GPIO_PINCFG70_FNCSEL70_Enum {
GPIO_PINCFG70_FNCSEL70_MSPI0_6 = 0
, GPIO_PINCFG70_FNCSEL70_32KHzXT = 1
, GPIO_PINCFG70_FNCSEL70_SWTRACE0 = 2
, GPIO_PINCFG70_FNCSEL70_GPIO = 3
,
GPIO_PINCFG70_FNCSEL70_UART0RTS = 4
, GPIO_PINCFG70_FNCSEL70_DISP_D6 = 5
, GPIO_PINCFG70_FNCSEL70_CT70 = 6
, GPIO_PINCFG70_FNCSEL70_NCE70 = 7
,
GPIO_PINCFG70_FNCSEL70_OBSBUS6 = 8
, GPIO_PINCFG70_FNCSEL70_RESERVED9 = 9
, GPIO_PINCFG70_FNCSEL70_RESERVED10 = 10
, GPIO_PINCFG70_FNCSEL70_FPIO = 11
,
GPIO_PINCFG70_FNCSEL70_RESERVED12 = 12
, GPIO_PINCFG70_FNCSEL70_RESERVED13 = 13
, GPIO_PINCFG70_FNCSEL70_RESERVED14 = 14
, GPIO_PINCFG70_FNCSEL70_RESERVED15 = 15
} |
| |
| enum | GPIO_PINCFG71_NCEPOL71_Enum { GPIO_PINCFG71_NCEPOL71_LOW = 0
, GPIO_PINCFG71_NCEPOL71_HIGH = 1
} |
| |
| enum | GPIO_PINCFG71_NCESRC71_Enum {
GPIO_PINCFG71_NCESRC71_IOM0CE0 = 0
, GPIO_PINCFG71_NCESRC71_IOM0CE1 = 1
, GPIO_PINCFG71_NCESRC71_IOM0CE2 = 2
, GPIO_PINCFG71_NCESRC71_IOM0CE3 = 3
,
GPIO_PINCFG71_NCESRC71_IOM1CE0 = 4
, GPIO_PINCFG71_NCESRC71_IOM1CE1 = 5
, GPIO_PINCFG71_NCESRC71_IOM1CE2 = 6
, GPIO_PINCFG71_NCESRC71_IOM1CE3 = 7
,
GPIO_PINCFG71_NCESRC71_IOM2CE0 = 8
, GPIO_PINCFG71_NCESRC71_IOM2CE1 = 9
, GPIO_PINCFG71_NCESRC71_IOM2CE2 = 10
, GPIO_PINCFG71_NCESRC71_IOM2CE3 = 11
,
GPIO_PINCFG71_NCESRC71_IOM3CE0 = 12
, GPIO_PINCFG71_NCESRC71_IOM3CE1 = 13
, GPIO_PINCFG71_NCESRC71_IOM3CE2 = 14
, GPIO_PINCFG71_NCESRC71_IOM3CE3 = 15
,
GPIO_PINCFG71_NCESRC71_IOM4CE0 = 16
, GPIO_PINCFG71_NCESRC71_IOM4CE1 = 17
, GPIO_PINCFG71_NCESRC71_IOM4CE2 = 18
, GPIO_PINCFG71_NCESRC71_IOM4CE3 = 19
,
GPIO_PINCFG71_NCESRC71_IOM5CE0 = 20
, GPIO_PINCFG71_NCESRC71_IOM5CE1 = 21
, GPIO_PINCFG71_NCESRC71_IOM5CE2 = 22
, GPIO_PINCFG71_NCESRC71_IOM5CE3 = 23
,
GPIO_PINCFG71_NCESRC71_IOM6CE0 = 24
, GPIO_PINCFG71_NCESRC71_IOM6CE1 = 25
, GPIO_PINCFG71_NCESRC71_IOM6CE2 = 26
, GPIO_PINCFG71_NCESRC71_IOM6CE3 = 27
,
GPIO_PINCFG71_NCESRC71_IOM7CE0 = 28
, GPIO_PINCFG71_NCESRC71_IOM7CE1 = 29
, GPIO_PINCFG71_NCESRC71_IOM7CE2 = 30
, GPIO_PINCFG71_NCESRC71_IOM7CE3 = 31
,
GPIO_PINCFG71_NCESRC71_MSPI0CEN0 = 32
, GPIO_PINCFG71_NCESRC71_MSPI0CEN1 = 33
, GPIO_PINCFG71_NCESRC71_MSPI1CEN0 = 34
, GPIO_PINCFG71_NCESRC71_MSPI1CEN1 = 35
,
GPIO_PINCFG71_NCESRC71_MSPI2CEN0 = 36
, GPIO_PINCFG71_NCESRC71_MSPI2CEN1 = 37
, GPIO_PINCFG71_NCESRC71_DC_DPI_DE = 38
, GPIO_PINCFG71_NCESRC71_DISP_CONT_CSX = 39
,
GPIO_PINCFG71_NCESRC71_DC_SPI_CS_N = 40
, GPIO_PINCFG71_NCESRC71_DC_QSPI_CS_N = 41
, GPIO_PINCFG71_NCESRC71_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG71_PULLCFG71_Enum {
GPIO_PINCFG71_PULLCFG71_DIS = 0
, GPIO_PINCFG71_PULLCFG71_PD50K = 1
, GPIO_PINCFG71_PULLCFG71_PU15K = 2
, GPIO_PINCFG71_PULLCFG71_PU6K = 3
,
GPIO_PINCFG71_PULLCFG71_PU12K = 4
, GPIO_PINCFG71_PULLCFG71_PU24K = 5
, GPIO_PINCFG71_PULLCFG71_PU50K = 6
, GPIO_PINCFG71_PULLCFG71_PU100K = 7
} |
| |
| enum | GPIO_PINCFG71_DS71_Enum { GPIO_PINCFG71_DS71_0P1X = 0
, GPIO_PINCFG71_DS71_0P5X = 1
, GPIO_PINCFG71_DS71_0P75X = 2
, GPIO_PINCFG71_DS71_1P0X = 3
} |
| |
| enum | GPIO_PINCFG71_OUTCFG71_Enum { GPIO_PINCFG71_OUTCFG71_DIS = 0
, GPIO_PINCFG71_OUTCFG71_PUSHPULL = 1
, GPIO_PINCFG71_OUTCFG71_OD = 2
, GPIO_PINCFG71_OUTCFG71_TS = 3
} |
| |
| enum | GPIO_PINCFG71_IRPTEN71_Enum { GPIO_PINCFG71_IRPTEN71_DIS = 0
, GPIO_PINCFG71_IRPTEN71_INTFALL = 1
, GPIO_PINCFG71_IRPTEN71_INTRISE = 2
, GPIO_PINCFG71_IRPTEN71_INTANY = 3
} |
| |
| enum | GPIO_PINCFG71_FNCSEL71_Enum {
GPIO_PINCFG71_FNCSEL71_MSPI0_7 = 0
, GPIO_PINCFG71_FNCSEL71_CLKOUT = 1
, GPIO_PINCFG71_FNCSEL71_SWTRACE1 = 2
, GPIO_PINCFG71_FNCSEL71_GPIO = 3
,
GPIO_PINCFG71_FNCSEL71_UART0CTS = 4
, GPIO_PINCFG71_FNCSEL71_DISP_D7 = 5
, GPIO_PINCFG71_FNCSEL71_CT71 = 6
, GPIO_PINCFG71_FNCSEL71_NCE71 = 7
,
GPIO_PINCFG71_FNCSEL71_OBSBUS7 = 8
, GPIO_PINCFG71_FNCSEL71_RESERVED9 = 9
, GPIO_PINCFG71_FNCSEL71_RESERVED10 = 10
, GPIO_PINCFG71_FNCSEL71_FPIO = 11
,
GPIO_PINCFG71_FNCSEL71_RESERVED12 = 12
, GPIO_PINCFG71_FNCSEL71_RESERVED13 = 13
, GPIO_PINCFG71_FNCSEL71_RESERVED14 = 14
, GPIO_PINCFG71_FNCSEL71_RESERVED15 = 15
} |
| |
| enum | GPIO_PINCFG72_NCEPOL72_Enum { GPIO_PINCFG72_NCEPOL72_LOW = 0
, GPIO_PINCFG72_NCEPOL72_HIGH = 1
} |
| |
| enum | GPIO_PINCFG72_NCESRC72_Enum {
GPIO_PINCFG72_NCESRC72_IOM0CE0 = 0
, GPIO_PINCFG72_NCESRC72_IOM0CE1 = 1
, GPIO_PINCFG72_NCESRC72_IOM0CE2 = 2
, GPIO_PINCFG72_NCESRC72_IOM0CE3 = 3
,
GPIO_PINCFG72_NCESRC72_IOM1CE0 = 4
, GPIO_PINCFG72_NCESRC72_IOM1CE1 = 5
, GPIO_PINCFG72_NCESRC72_IOM1CE2 = 6
, GPIO_PINCFG72_NCESRC72_IOM1CE3 = 7
,
GPIO_PINCFG72_NCESRC72_IOM2CE0 = 8
, GPIO_PINCFG72_NCESRC72_IOM2CE1 = 9
, GPIO_PINCFG72_NCESRC72_IOM2CE2 = 10
, GPIO_PINCFG72_NCESRC72_IOM2CE3 = 11
,
GPIO_PINCFG72_NCESRC72_IOM3CE0 = 12
, GPIO_PINCFG72_NCESRC72_IOM3CE1 = 13
, GPIO_PINCFG72_NCESRC72_IOM3CE2 = 14
, GPIO_PINCFG72_NCESRC72_IOM3CE3 = 15
,
GPIO_PINCFG72_NCESRC72_IOM4CE0 = 16
, GPIO_PINCFG72_NCESRC72_IOM4CE1 = 17
, GPIO_PINCFG72_NCESRC72_IOM4CE2 = 18
, GPIO_PINCFG72_NCESRC72_IOM4CE3 = 19
,
GPIO_PINCFG72_NCESRC72_IOM5CE0 = 20
, GPIO_PINCFG72_NCESRC72_IOM5CE1 = 21
, GPIO_PINCFG72_NCESRC72_IOM5CE2 = 22
, GPIO_PINCFG72_NCESRC72_IOM5CE3 = 23
,
GPIO_PINCFG72_NCESRC72_IOM6CE0 = 24
, GPIO_PINCFG72_NCESRC72_IOM6CE1 = 25
, GPIO_PINCFG72_NCESRC72_IOM6CE2 = 26
, GPIO_PINCFG72_NCESRC72_IOM6CE3 = 27
,
GPIO_PINCFG72_NCESRC72_IOM7CE0 = 28
, GPIO_PINCFG72_NCESRC72_IOM7CE1 = 29
, GPIO_PINCFG72_NCESRC72_IOM7CE2 = 30
, GPIO_PINCFG72_NCESRC72_IOM7CE3 = 31
,
GPIO_PINCFG72_NCESRC72_MSPI0CEN0 = 32
, GPIO_PINCFG72_NCESRC72_MSPI0CEN1 = 33
, GPIO_PINCFG72_NCESRC72_MSPI1CEN0 = 34
, GPIO_PINCFG72_NCESRC72_MSPI1CEN1 = 35
,
GPIO_PINCFG72_NCESRC72_MSPI2CEN0 = 36
, GPIO_PINCFG72_NCESRC72_MSPI2CEN1 = 37
, GPIO_PINCFG72_NCESRC72_DC_DPI_DE = 38
, GPIO_PINCFG72_NCESRC72_DISP_CONT_CSX = 39
,
GPIO_PINCFG72_NCESRC72_DC_SPI_CS_N = 40
, GPIO_PINCFG72_NCESRC72_DC_QSPI_CS_N = 41
, GPIO_PINCFG72_NCESRC72_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG72_PULLCFG72_Enum {
GPIO_PINCFG72_PULLCFG72_DIS = 0
, GPIO_PINCFG72_PULLCFG72_PD50K = 1
, GPIO_PINCFG72_PULLCFG72_PU15K = 2
, GPIO_PINCFG72_PULLCFG72_PU6K = 3
,
GPIO_PINCFG72_PULLCFG72_PU12K = 4
, GPIO_PINCFG72_PULLCFG72_PU24K = 5
, GPIO_PINCFG72_PULLCFG72_PU50K = 6
, GPIO_PINCFG72_PULLCFG72_PU100K = 7
} |
| |
| enum | GPIO_PINCFG72_DS72_Enum { GPIO_PINCFG72_DS72_0P1X = 0
, GPIO_PINCFG72_DS72_0P5X = 1
, GPIO_PINCFG72_DS72_0P75X = 2
, GPIO_PINCFG72_DS72_1P0X = 3
} |
| |
| enum | GPIO_PINCFG72_OUTCFG72_Enum { GPIO_PINCFG72_OUTCFG72_DIS = 0
, GPIO_PINCFG72_OUTCFG72_PUSHPULL = 1
, GPIO_PINCFG72_OUTCFG72_OD = 2
, GPIO_PINCFG72_OUTCFG72_TS = 3
} |
| |
| enum | GPIO_PINCFG72_IRPTEN72_Enum { GPIO_PINCFG72_IRPTEN72_DIS = 0
, GPIO_PINCFG72_IRPTEN72_INTFALL = 1
, GPIO_PINCFG72_IRPTEN72_INTRISE = 2
, GPIO_PINCFG72_IRPTEN72_INTANY = 3
} |
| |
| enum | GPIO_PINCFG72_FNCSEL72_Enum {
GPIO_PINCFG72_FNCSEL72_MSPI0_8 = 0
, GPIO_PINCFG72_FNCSEL72_CLKOUT = 1
, GPIO_PINCFG72_FNCSEL72_SWTRACE2 = 2
, GPIO_PINCFG72_FNCSEL72_GPIO = 3
,
GPIO_PINCFG72_FNCSEL72_UART0TX = 4
, GPIO_PINCFG72_FNCSEL72_DISP_D8 = 5
, GPIO_PINCFG72_FNCSEL72_CT72 = 6
, GPIO_PINCFG72_FNCSEL72_NCE72 = 7
,
GPIO_PINCFG72_FNCSEL72_OBSBUS8 = 8
, GPIO_PINCFG72_FNCSEL72_VCMPO = 9
, GPIO_PINCFG72_FNCSEL72_RESERVED10 = 10
, GPIO_PINCFG72_FNCSEL72_FPIO = 11
,
GPIO_PINCFG72_FNCSEL72_RESERVED12 = 12
, GPIO_PINCFG72_FNCSEL72_RESERVED13 = 13
, GPIO_PINCFG72_FNCSEL72_RESERVED14 = 14
, GPIO_PINCFG72_FNCSEL72_RESERVED15 = 15
} |
| |
| enum | GPIO_PINCFG73_NCEPOL73_Enum { GPIO_PINCFG73_NCEPOL73_LOW = 0
, GPIO_PINCFG73_NCEPOL73_HIGH = 1
} |
| |
| enum | GPIO_PINCFG73_NCESRC73_Enum {
GPIO_PINCFG73_NCESRC73_IOM0CE0 = 0
, GPIO_PINCFG73_NCESRC73_IOM0CE1 = 1
, GPIO_PINCFG73_NCESRC73_IOM0CE2 = 2
, GPIO_PINCFG73_NCESRC73_IOM0CE3 = 3
,
GPIO_PINCFG73_NCESRC73_IOM1CE0 = 4
, GPIO_PINCFG73_NCESRC73_IOM1CE1 = 5
, GPIO_PINCFG73_NCESRC73_IOM1CE2 = 6
, GPIO_PINCFG73_NCESRC73_IOM1CE3 = 7
,
GPIO_PINCFG73_NCESRC73_IOM2CE0 = 8
, GPIO_PINCFG73_NCESRC73_IOM2CE1 = 9
, GPIO_PINCFG73_NCESRC73_IOM2CE2 = 10
, GPIO_PINCFG73_NCESRC73_IOM2CE3 = 11
,
GPIO_PINCFG73_NCESRC73_IOM3CE0 = 12
, GPIO_PINCFG73_NCESRC73_IOM3CE1 = 13
, GPIO_PINCFG73_NCESRC73_IOM3CE2 = 14
, GPIO_PINCFG73_NCESRC73_IOM3CE3 = 15
,
GPIO_PINCFG73_NCESRC73_IOM4CE0 = 16
, GPIO_PINCFG73_NCESRC73_IOM4CE1 = 17
, GPIO_PINCFG73_NCESRC73_IOM4CE2 = 18
, GPIO_PINCFG73_NCESRC73_IOM4CE3 = 19
,
GPIO_PINCFG73_NCESRC73_IOM5CE0 = 20
, GPIO_PINCFG73_NCESRC73_IOM5CE1 = 21
, GPIO_PINCFG73_NCESRC73_IOM5CE2 = 22
, GPIO_PINCFG73_NCESRC73_IOM5CE3 = 23
,
GPIO_PINCFG73_NCESRC73_IOM6CE0 = 24
, GPIO_PINCFG73_NCESRC73_IOM6CE1 = 25
, GPIO_PINCFG73_NCESRC73_IOM6CE2 = 26
, GPIO_PINCFG73_NCESRC73_IOM6CE3 = 27
,
GPIO_PINCFG73_NCESRC73_IOM7CE0 = 28
, GPIO_PINCFG73_NCESRC73_IOM7CE1 = 29
, GPIO_PINCFG73_NCESRC73_IOM7CE2 = 30
, GPIO_PINCFG73_NCESRC73_IOM7CE3 = 31
,
GPIO_PINCFG73_NCESRC73_MSPI0CEN0 = 32
, GPIO_PINCFG73_NCESRC73_MSPI0CEN1 = 33
, GPIO_PINCFG73_NCESRC73_MSPI1CEN0 = 34
, GPIO_PINCFG73_NCESRC73_MSPI1CEN1 = 35
,
GPIO_PINCFG73_NCESRC73_MSPI2CEN0 = 36
, GPIO_PINCFG73_NCESRC73_MSPI2CEN1 = 37
, GPIO_PINCFG73_NCESRC73_DC_DPI_DE = 38
, GPIO_PINCFG73_NCESRC73_DISP_CONT_CSX = 39
,
GPIO_PINCFG73_NCESRC73_DC_SPI_CS_N = 40
, GPIO_PINCFG73_NCESRC73_DC_QSPI_CS_N = 41
, GPIO_PINCFG73_NCESRC73_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG73_PULLCFG73_Enum {
GPIO_PINCFG73_PULLCFG73_DIS = 0
, GPIO_PINCFG73_PULLCFG73_PD50K = 1
, GPIO_PINCFG73_PULLCFG73_PU15K = 2
, GPIO_PINCFG73_PULLCFG73_PU6K = 3
,
GPIO_PINCFG73_PULLCFG73_PU12K = 4
, GPIO_PINCFG73_PULLCFG73_PU24K = 5
, GPIO_PINCFG73_PULLCFG73_PU50K = 6
, GPIO_PINCFG73_PULLCFG73_PU100K = 7
} |
| |
| enum | GPIO_PINCFG73_DS73_Enum { GPIO_PINCFG73_DS73_0P1X = 0
, GPIO_PINCFG73_DS73_0P5X = 1
, GPIO_PINCFG73_DS73_0P75X = 2
, GPIO_PINCFG73_DS73_1P0X = 3
} |
| |
| enum | GPIO_PINCFG73_OUTCFG73_Enum { GPIO_PINCFG73_OUTCFG73_DIS = 0
, GPIO_PINCFG73_OUTCFG73_PUSHPULL = 1
, GPIO_PINCFG73_OUTCFG73_OD = 2
, GPIO_PINCFG73_OUTCFG73_TS = 3
} |
| |
| enum | GPIO_PINCFG73_IRPTEN73_Enum { GPIO_PINCFG73_IRPTEN73_DIS = 0
, GPIO_PINCFG73_IRPTEN73_INTFALL = 1
, GPIO_PINCFG73_IRPTEN73_INTRISE = 2
, GPIO_PINCFG73_IRPTEN73_INTANY = 3
} |
| |
| enum | GPIO_PINCFG73_FNCSEL73_Enum {
GPIO_PINCFG73_FNCSEL73_MSPI0_9 = 0
, GPIO_PINCFG73_FNCSEL73_RESERVED1 = 1
, GPIO_PINCFG73_FNCSEL73_SWTRACE3 = 2
, GPIO_PINCFG73_FNCSEL73_GPIO = 3
,
GPIO_PINCFG73_FNCSEL73_UART2TX = 4
, GPIO_PINCFG73_FNCSEL73_DISP_D9 = 5
, GPIO_PINCFG73_FNCSEL73_CT73 = 6
, GPIO_PINCFG73_FNCSEL73_NCE73 = 7
,
GPIO_PINCFG73_FNCSEL73_OBSBUS9 = 8
, GPIO_PINCFG73_FNCSEL73_RESERVED9 = 9
, GPIO_PINCFG73_FNCSEL73_RESERVED10 = 10
, GPIO_PINCFG73_FNCSEL73_FPIO = 11
,
GPIO_PINCFG73_FNCSEL73_RESERVED12 = 12
, GPIO_PINCFG73_FNCSEL73_RESERVED13 = 13
, GPIO_PINCFG73_FNCSEL73_RESERVED14 = 14
, GPIO_PINCFG73_FNCSEL73_RESERVED15 = 15
} |
| |
| enum | GPIO_PINCFG74_NCEPOL74_Enum { GPIO_PINCFG74_NCEPOL74_LOW = 0
, GPIO_PINCFG74_NCEPOL74_HIGH = 1
} |
| |
| enum | GPIO_PINCFG74_NCESRC74_Enum {
GPIO_PINCFG74_NCESRC74_IOM0CE0 = 0
, GPIO_PINCFG74_NCESRC74_IOM0CE1 = 1
, GPIO_PINCFG74_NCESRC74_IOM0CE2 = 2
, GPIO_PINCFG74_NCESRC74_IOM0CE3 = 3
,
GPIO_PINCFG74_NCESRC74_IOM1CE0 = 4
, GPIO_PINCFG74_NCESRC74_IOM1CE1 = 5
, GPIO_PINCFG74_NCESRC74_IOM1CE2 = 6
, GPIO_PINCFG74_NCESRC74_IOM1CE3 = 7
,
GPIO_PINCFG74_NCESRC74_IOM2CE0 = 8
, GPIO_PINCFG74_NCESRC74_IOM2CE1 = 9
, GPIO_PINCFG74_NCESRC74_IOM2CE2 = 10
, GPIO_PINCFG74_NCESRC74_IOM2CE3 = 11
,
GPIO_PINCFG74_NCESRC74_IOM3CE0 = 12
, GPIO_PINCFG74_NCESRC74_IOM3CE1 = 13
, GPIO_PINCFG74_NCESRC74_IOM3CE2 = 14
, GPIO_PINCFG74_NCESRC74_IOM3CE3 = 15
,
GPIO_PINCFG74_NCESRC74_IOM4CE0 = 16
, GPIO_PINCFG74_NCESRC74_IOM4CE1 = 17
, GPIO_PINCFG74_NCESRC74_IOM4CE2 = 18
, GPIO_PINCFG74_NCESRC74_IOM4CE3 = 19
,
GPIO_PINCFG74_NCESRC74_IOM5CE0 = 20
, GPIO_PINCFG74_NCESRC74_IOM5CE1 = 21
, GPIO_PINCFG74_NCESRC74_IOM5CE2 = 22
, GPIO_PINCFG74_NCESRC74_IOM5CE3 = 23
,
GPIO_PINCFG74_NCESRC74_IOM6CE0 = 24
, GPIO_PINCFG74_NCESRC74_IOM6CE1 = 25
, GPIO_PINCFG74_NCESRC74_IOM6CE2 = 26
, GPIO_PINCFG74_NCESRC74_IOM6CE3 = 27
,
GPIO_PINCFG74_NCESRC74_IOM7CE0 = 28
, GPIO_PINCFG74_NCESRC74_IOM7CE1 = 29
, GPIO_PINCFG74_NCESRC74_IOM7CE2 = 30
, GPIO_PINCFG74_NCESRC74_IOM7CE3 = 31
,
GPIO_PINCFG74_NCESRC74_MSPI0CEN0 = 32
, GPIO_PINCFG74_NCESRC74_MSPI0CEN1 = 33
, GPIO_PINCFG74_NCESRC74_MSPI1CEN0 = 34
, GPIO_PINCFG74_NCESRC74_MSPI1CEN1 = 35
,
GPIO_PINCFG74_NCESRC74_MSPI2CEN0 = 36
, GPIO_PINCFG74_NCESRC74_MSPI2CEN1 = 37
, GPIO_PINCFG74_NCESRC74_DC_DPI_DE = 38
, GPIO_PINCFG74_NCESRC74_DISP_CONT_CSX = 39
,
GPIO_PINCFG74_NCESRC74_DC_SPI_CS_N = 40
, GPIO_PINCFG74_NCESRC74_DC_QSPI_CS_N = 41
, GPIO_PINCFG74_NCESRC74_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG74_PULLCFG74_Enum {
GPIO_PINCFG74_PULLCFG74_DIS = 0
, GPIO_PINCFG74_PULLCFG74_PD50K = 1
, GPIO_PINCFG74_PULLCFG74_PU15K = 2
, GPIO_PINCFG74_PULLCFG74_PU6K = 3
,
GPIO_PINCFG74_PULLCFG74_PU12K = 4
, GPIO_PINCFG74_PULLCFG74_PU24K = 5
, GPIO_PINCFG74_PULLCFG74_PU50K = 6
, GPIO_PINCFG74_PULLCFG74_PU100K = 7
} |
| |
| enum | GPIO_PINCFG74_DS74_Enum { GPIO_PINCFG74_DS74_0P1X = 0
, GPIO_PINCFG74_DS74_0P5X = 1
, GPIO_PINCFG74_DS74_0P75X = 2
, GPIO_PINCFG74_DS74_1P0X = 3
} |
| |
| enum | GPIO_PINCFG74_OUTCFG74_Enum { GPIO_PINCFG74_OUTCFG74_DIS = 0
, GPIO_PINCFG74_OUTCFG74_PUSHPULL = 1
, GPIO_PINCFG74_OUTCFG74_OD = 2
, GPIO_PINCFG74_OUTCFG74_TS = 3
} |
| |
| enum | GPIO_PINCFG74_IRPTEN74_Enum { GPIO_PINCFG74_IRPTEN74_DIS = 0
, GPIO_PINCFG74_IRPTEN74_INTFALL = 1
, GPIO_PINCFG74_IRPTEN74_INTRISE = 2
, GPIO_PINCFG74_IRPTEN74_INTANY = 3
} |
| |
| enum | GPIO_PINCFG74_FNCSEL74_Enum {
GPIO_PINCFG74_FNCSEL74_MSPI2_0 = 0
, GPIO_PINCFG74_FNCSEL74_DISP_QSPI_D0_OUT = 1
, GPIO_PINCFG74_FNCSEL74_DISP_QSPI_D0 = 2
, GPIO_PINCFG74_FNCSEL74_GPIO = 3
,
GPIO_PINCFG74_FNCSEL74_UART0RX = 4
, GPIO_PINCFG74_FNCSEL74_DISP_D10 = 5
, GPIO_PINCFG74_FNCSEL74_CT74 = 6
, GPIO_PINCFG74_FNCSEL74_NCE74 = 7
,
GPIO_PINCFG74_FNCSEL74_OBSBUS10 = 8
, GPIO_PINCFG74_FNCSEL74_DISP_SPI_SD = 9
, GPIO_PINCFG74_FNCSEL74_DISP_SPI_SDO = 10
, GPIO_PINCFG74_FNCSEL74_FPIO = 11
,
GPIO_PINCFG74_FNCSEL74_RESERVED12 = 12
, GPIO_PINCFG74_FNCSEL74_RESERVED13 = 13
, GPIO_PINCFG74_FNCSEL74_RESERVED14 = 14
, GPIO_PINCFG74_FNCSEL74_RESERVED15 = 15
} |
| |
| enum | GPIO_PINCFG75_NCEPOL75_Enum { GPIO_PINCFG75_NCEPOL75_LOW = 0
, GPIO_PINCFG75_NCEPOL75_HIGH = 1
} |
| |
| enum | GPIO_PINCFG75_NCESRC75_Enum {
GPIO_PINCFG75_NCESRC75_IOM0CE0 = 0
, GPIO_PINCFG75_NCESRC75_IOM0CE1 = 1
, GPIO_PINCFG75_NCESRC75_IOM0CE2 = 2
, GPIO_PINCFG75_NCESRC75_IOM0CE3 = 3
,
GPIO_PINCFG75_NCESRC75_IOM1CE0 = 4
, GPIO_PINCFG75_NCESRC75_IOM1CE1 = 5
, GPIO_PINCFG75_NCESRC75_IOM1CE2 = 6
, GPIO_PINCFG75_NCESRC75_IOM1CE3 = 7
,
GPIO_PINCFG75_NCESRC75_IOM2CE0 = 8
, GPIO_PINCFG75_NCESRC75_IOM2CE1 = 9
, GPIO_PINCFG75_NCESRC75_IOM2CE2 = 10
, GPIO_PINCFG75_NCESRC75_IOM2CE3 = 11
,
GPIO_PINCFG75_NCESRC75_IOM3CE0 = 12
, GPIO_PINCFG75_NCESRC75_IOM3CE1 = 13
, GPIO_PINCFG75_NCESRC75_IOM3CE2 = 14
, GPIO_PINCFG75_NCESRC75_IOM3CE3 = 15
,
GPIO_PINCFG75_NCESRC75_IOM4CE0 = 16
, GPIO_PINCFG75_NCESRC75_IOM4CE1 = 17
, GPIO_PINCFG75_NCESRC75_IOM4CE2 = 18
, GPIO_PINCFG75_NCESRC75_IOM4CE3 = 19
,
GPIO_PINCFG75_NCESRC75_IOM5CE0 = 20
, GPIO_PINCFG75_NCESRC75_IOM5CE1 = 21
, GPIO_PINCFG75_NCESRC75_IOM5CE2 = 22
, GPIO_PINCFG75_NCESRC75_IOM5CE3 = 23
,
GPIO_PINCFG75_NCESRC75_IOM6CE0 = 24
, GPIO_PINCFG75_NCESRC75_IOM6CE1 = 25
, GPIO_PINCFG75_NCESRC75_IOM6CE2 = 26
, GPIO_PINCFG75_NCESRC75_IOM6CE3 = 27
,
GPIO_PINCFG75_NCESRC75_IOM7CE0 = 28
, GPIO_PINCFG75_NCESRC75_IOM7CE1 = 29
, GPIO_PINCFG75_NCESRC75_IOM7CE2 = 30
, GPIO_PINCFG75_NCESRC75_IOM7CE3 = 31
,
GPIO_PINCFG75_NCESRC75_MSPI0CEN0 = 32
, GPIO_PINCFG75_NCESRC75_MSPI0CEN1 = 33
, GPIO_PINCFG75_NCESRC75_MSPI1CEN0 = 34
, GPIO_PINCFG75_NCESRC75_MSPI1CEN1 = 35
,
GPIO_PINCFG75_NCESRC75_MSPI2CEN0 = 36
, GPIO_PINCFG75_NCESRC75_MSPI2CEN1 = 37
, GPIO_PINCFG75_NCESRC75_DC_DPI_DE = 38
, GPIO_PINCFG75_NCESRC75_DISP_CONT_CSX = 39
,
GPIO_PINCFG75_NCESRC75_DC_SPI_CS_N = 40
, GPIO_PINCFG75_NCESRC75_DC_QSPI_CS_N = 41
, GPIO_PINCFG75_NCESRC75_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG75_PULLCFG75_Enum {
GPIO_PINCFG75_PULLCFG75_DIS = 0
, GPIO_PINCFG75_PULLCFG75_PD50K = 1
, GPIO_PINCFG75_PULLCFG75_PU15K = 2
, GPIO_PINCFG75_PULLCFG75_PU6K = 3
,
GPIO_PINCFG75_PULLCFG75_PU12K = 4
, GPIO_PINCFG75_PULLCFG75_PU24K = 5
, GPIO_PINCFG75_PULLCFG75_PU50K = 6
, GPIO_PINCFG75_PULLCFG75_PU100K = 7
} |
| |
| enum | GPIO_PINCFG75_DS75_Enum { GPIO_PINCFG75_DS75_0P1X = 0
, GPIO_PINCFG75_DS75_0P5X = 1
, GPIO_PINCFG75_DS75_0P75X = 2
, GPIO_PINCFG75_DS75_1P0X = 3
} |
| |
| enum | GPIO_PINCFG75_OUTCFG75_Enum { GPIO_PINCFG75_OUTCFG75_DIS = 0
, GPIO_PINCFG75_OUTCFG75_PUSHPULL = 1
, GPIO_PINCFG75_OUTCFG75_OD = 2
, GPIO_PINCFG75_OUTCFG75_TS = 3
} |
| |
| enum | GPIO_PINCFG75_IRPTEN75_Enum { GPIO_PINCFG75_IRPTEN75_DIS = 0
, GPIO_PINCFG75_IRPTEN75_INTFALL = 1
, GPIO_PINCFG75_IRPTEN75_INTRISE = 2
, GPIO_PINCFG75_IRPTEN75_INTANY = 3
} |
| |
| enum | GPIO_PINCFG75_FNCSEL75_Enum {
GPIO_PINCFG75_FNCSEL75_MSPI2_1 = 0
, GPIO_PINCFG75_FNCSEL75_32KHzXT = 1
, GPIO_PINCFG75_FNCSEL75_DISP_QSPI_D1 = 2
, GPIO_PINCFG75_FNCSEL75_GPIO = 3
,
GPIO_PINCFG75_FNCSEL75_UART2RX = 4
, GPIO_PINCFG75_FNCSEL75_DISP_D11 = 5
, GPIO_PINCFG75_FNCSEL75_CT75 = 6
, GPIO_PINCFG75_FNCSEL75_NCE75 = 7
,
GPIO_PINCFG75_FNCSEL75_OBSBUS11 = 8
, GPIO_PINCFG75_FNCSEL75_DISP_SPI_DCX = 9
, GPIO_PINCFG75_FNCSEL75_RESERVED10 = 10
, GPIO_PINCFG75_FNCSEL75_FPIO = 11
,
GPIO_PINCFG75_FNCSEL75_RESERVED12 = 12
, GPIO_PINCFG75_FNCSEL75_RESERVED13 = 13
, GPIO_PINCFG75_FNCSEL75_RESERVED14 = 14
, GPIO_PINCFG75_FNCSEL75_RESERVED15 = 15
} |
| |
| enum | GPIO_PINCFG76_NCEPOL76_Enum { GPIO_PINCFG76_NCEPOL76_LOW = 0
, GPIO_PINCFG76_NCEPOL76_HIGH = 1
} |
| |
| enum | GPIO_PINCFG76_NCESRC76_Enum {
GPIO_PINCFG76_NCESRC76_IOM0CE0 = 0
, GPIO_PINCFG76_NCESRC76_IOM0CE1 = 1
, GPIO_PINCFG76_NCESRC76_IOM0CE2 = 2
, GPIO_PINCFG76_NCESRC76_IOM0CE3 = 3
,
GPIO_PINCFG76_NCESRC76_IOM1CE0 = 4
, GPIO_PINCFG76_NCESRC76_IOM1CE1 = 5
, GPIO_PINCFG76_NCESRC76_IOM1CE2 = 6
, GPIO_PINCFG76_NCESRC76_IOM1CE3 = 7
,
GPIO_PINCFG76_NCESRC76_IOM2CE0 = 8
, GPIO_PINCFG76_NCESRC76_IOM2CE1 = 9
, GPIO_PINCFG76_NCESRC76_IOM2CE2 = 10
, GPIO_PINCFG76_NCESRC76_IOM2CE3 = 11
,
GPIO_PINCFG76_NCESRC76_IOM3CE0 = 12
, GPIO_PINCFG76_NCESRC76_IOM3CE1 = 13
, GPIO_PINCFG76_NCESRC76_IOM3CE2 = 14
, GPIO_PINCFG76_NCESRC76_IOM3CE3 = 15
,
GPIO_PINCFG76_NCESRC76_IOM4CE0 = 16
, GPIO_PINCFG76_NCESRC76_IOM4CE1 = 17
, GPIO_PINCFG76_NCESRC76_IOM4CE2 = 18
, GPIO_PINCFG76_NCESRC76_IOM4CE3 = 19
,
GPIO_PINCFG76_NCESRC76_IOM5CE0 = 20
, GPIO_PINCFG76_NCESRC76_IOM5CE1 = 21
, GPIO_PINCFG76_NCESRC76_IOM5CE2 = 22
, GPIO_PINCFG76_NCESRC76_IOM5CE3 = 23
,
GPIO_PINCFG76_NCESRC76_IOM6CE0 = 24
, GPIO_PINCFG76_NCESRC76_IOM6CE1 = 25
, GPIO_PINCFG76_NCESRC76_IOM6CE2 = 26
, GPIO_PINCFG76_NCESRC76_IOM6CE3 = 27
,
GPIO_PINCFG76_NCESRC76_IOM7CE0 = 28
, GPIO_PINCFG76_NCESRC76_IOM7CE1 = 29
, GPIO_PINCFG76_NCESRC76_IOM7CE2 = 30
, GPIO_PINCFG76_NCESRC76_IOM7CE3 = 31
,
GPIO_PINCFG76_NCESRC76_MSPI0CEN0 = 32
, GPIO_PINCFG76_NCESRC76_MSPI0CEN1 = 33
, GPIO_PINCFG76_NCESRC76_MSPI1CEN0 = 34
, GPIO_PINCFG76_NCESRC76_MSPI1CEN1 = 35
,
GPIO_PINCFG76_NCESRC76_MSPI2CEN0 = 36
, GPIO_PINCFG76_NCESRC76_MSPI2CEN1 = 37
, GPIO_PINCFG76_NCESRC76_DC_DPI_DE = 38
, GPIO_PINCFG76_NCESRC76_DISP_CONT_CSX = 39
,
GPIO_PINCFG76_NCESRC76_DC_SPI_CS_N = 40
, GPIO_PINCFG76_NCESRC76_DC_QSPI_CS_N = 41
, GPIO_PINCFG76_NCESRC76_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG76_PULLCFG76_Enum {
GPIO_PINCFG76_PULLCFG76_DIS = 0
, GPIO_PINCFG76_PULLCFG76_PD50K = 1
, GPIO_PINCFG76_PULLCFG76_PU15K = 2
, GPIO_PINCFG76_PULLCFG76_PU6K = 3
,
GPIO_PINCFG76_PULLCFG76_PU12K = 4
, GPIO_PINCFG76_PULLCFG76_PU24K = 5
, GPIO_PINCFG76_PULLCFG76_PU50K = 6
, GPIO_PINCFG76_PULLCFG76_PU100K = 7
} |
| |
| enum | GPIO_PINCFG76_DS76_Enum { GPIO_PINCFG76_DS76_0P1X = 0
, GPIO_PINCFG76_DS76_0P5X = 1
, GPIO_PINCFG76_DS76_0P75X = 2
, GPIO_PINCFG76_DS76_1P0X = 3
} |
| |
| enum | GPIO_PINCFG76_OUTCFG76_Enum { GPIO_PINCFG76_OUTCFG76_DIS = 0
, GPIO_PINCFG76_OUTCFG76_PUSHPULL = 1
, GPIO_PINCFG76_OUTCFG76_OD = 2
, GPIO_PINCFG76_OUTCFG76_TS = 3
} |
| |
| enum | GPIO_PINCFG76_IRPTEN76_Enum { GPIO_PINCFG76_IRPTEN76_DIS = 0
, GPIO_PINCFG76_IRPTEN76_INTFALL = 1
, GPIO_PINCFG76_IRPTEN76_INTRISE = 2
, GPIO_PINCFG76_IRPTEN76_INTANY = 3
} |
| |
| enum | GPIO_PINCFG76_FNCSEL76_Enum {
GPIO_PINCFG76_FNCSEL76_MSPI2_2 = 0
, GPIO_PINCFG76_FNCSEL76_32KHzXT = 1
, GPIO_PINCFG76_FNCSEL76_DISP_QSPI_D2 = 2
, GPIO_PINCFG76_FNCSEL76_GPIO = 3
,
GPIO_PINCFG76_FNCSEL76_UART0RTS = 4
, GPIO_PINCFG76_FNCSEL76_DISP_D12 = 5
, GPIO_PINCFG76_FNCSEL76_CT76 = 6
, GPIO_PINCFG76_FNCSEL76_NCE76 = 7
,
GPIO_PINCFG76_FNCSEL76_OBSBUS12 = 8
, GPIO_PINCFG76_FNCSEL76_RESERVED9 = 9
, GPIO_PINCFG76_FNCSEL76_RESERVED10 = 10
, GPIO_PINCFG76_FNCSEL76_FPIO = 11
,
GPIO_PINCFG76_FNCSEL76_RESERVED12 = 12
, GPIO_PINCFG76_FNCSEL76_RESERVED13 = 13
, GPIO_PINCFG76_FNCSEL76_RESERVED14 = 14
, GPIO_PINCFG76_FNCSEL76_RESERVED15 = 15
} |
| |
| enum | GPIO_PINCFG77_NCEPOL77_Enum { GPIO_PINCFG77_NCEPOL77_LOW = 0
, GPIO_PINCFG77_NCEPOL77_HIGH = 1
} |
| |
| enum | GPIO_PINCFG77_NCESRC77_Enum {
GPIO_PINCFG77_NCESRC77_IOM0CE0 = 0
, GPIO_PINCFG77_NCESRC77_IOM0CE1 = 1
, GPIO_PINCFG77_NCESRC77_IOM0CE2 = 2
, GPIO_PINCFG77_NCESRC77_IOM0CE3 = 3
,
GPIO_PINCFG77_NCESRC77_IOM1CE0 = 4
, GPIO_PINCFG77_NCESRC77_IOM1CE1 = 5
, GPIO_PINCFG77_NCESRC77_IOM1CE2 = 6
, GPIO_PINCFG77_NCESRC77_IOM1CE3 = 7
,
GPIO_PINCFG77_NCESRC77_IOM2CE0 = 8
, GPIO_PINCFG77_NCESRC77_IOM2CE1 = 9
, GPIO_PINCFG77_NCESRC77_IOM2CE2 = 10
, GPIO_PINCFG77_NCESRC77_IOM2CE3 = 11
,
GPIO_PINCFG77_NCESRC77_IOM3CE0 = 12
, GPIO_PINCFG77_NCESRC77_IOM3CE1 = 13
, GPIO_PINCFG77_NCESRC77_IOM3CE2 = 14
, GPIO_PINCFG77_NCESRC77_IOM3CE3 = 15
,
GPIO_PINCFG77_NCESRC77_IOM4CE0 = 16
, GPIO_PINCFG77_NCESRC77_IOM4CE1 = 17
, GPIO_PINCFG77_NCESRC77_IOM4CE2 = 18
, GPIO_PINCFG77_NCESRC77_IOM4CE3 = 19
,
GPIO_PINCFG77_NCESRC77_IOM5CE0 = 20
, GPIO_PINCFG77_NCESRC77_IOM5CE1 = 21
, GPIO_PINCFG77_NCESRC77_IOM5CE2 = 22
, GPIO_PINCFG77_NCESRC77_IOM5CE3 = 23
,
GPIO_PINCFG77_NCESRC77_IOM6CE0 = 24
, GPIO_PINCFG77_NCESRC77_IOM6CE1 = 25
, GPIO_PINCFG77_NCESRC77_IOM6CE2 = 26
, GPIO_PINCFG77_NCESRC77_IOM6CE3 = 27
,
GPIO_PINCFG77_NCESRC77_IOM7CE0 = 28
, GPIO_PINCFG77_NCESRC77_IOM7CE1 = 29
, GPIO_PINCFG77_NCESRC77_IOM7CE2 = 30
, GPIO_PINCFG77_NCESRC77_IOM7CE3 = 31
,
GPIO_PINCFG77_NCESRC77_MSPI0CEN0 = 32
, GPIO_PINCFG77_NCESRC77_MSPI0CEN1 = 33
, GPIO_PINCFG77_NCESRC77_MSPI1CEN0 = 34
, GPIO_PINCFG77_NCESRC77_MSPI1CEN1 = 35
,
GPIO_PINCFG77_NCESRC77_MSPI2CEN0 = 36
, GPIO_PINCFG77_NCESRC77_MSPI2CEN1 = 37
, GPIO_PINCFG77_NCESRC77_DC_DPI_DE = 38
, GPIO_PINCFG77_NCESRC77_DISP_CONT_CSX = 39
,
GPIO_PINCFG77_NCESRC77_DC_SPI_CS_N = 40
, GPIO_PINCFG77_NCESRC77_DC_QSPI_CS_N = 41
, GPIO_PINCFG77_NCESRC77_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG77_PULLCFG77_Enum {
GPIO_PINCFG77_PULLCFG77_DIS = 0
, GPIO_PINCFG77_PULLCFG77_PD50K = 1
, GPIO_PINCFG77_PULLCFG77_PU15K = 2
, GPIO_PINCFG77_PULLCFG77_PU6K = 3
,
GPIO_PINCFG77_PULLCFG77_PU12K = 4
, GPIO_PINCFG77_PULLCFG77_PU24K = 5
, GPIO_PINCFG77_PULLCFG77_PU50K = 6
, GPIO_PINCFG77_PULLCFG77_PU100K = 7
} |
| |
| enum | GPIO_PINCFG77_DS77_Enum { GPIO_PINCFG77_DS77_0P1X = 0
, GPIO_PINCFG77_DS77_0P5X = 1
, GPIO_PINCFG77_DS77_0P75X = 2
, GPIO_PINCFG77_DS77_1P0X = 3
} |
| |
| enum | GPIO_PINCFG77_OUTCFG77_Enum { GPIO_PINCFG77_OUTCFG77_DIS = 0
, GPIO_PINCFG77_OUTCFG77_PUSHPULL = 1
, GPIO_PINCFG77_OUTCFG77_OD = 2
, GPIO_PINCFG77_OUTCFG77_TS = 3
} |
| |
| enum | GPIO_PINCFG77_IRPTEN77_Enum { GPIO_PINCFG77_IRPTEN77_DIS = 0
, GPIO_PINCFG77_IRPTEN77_INTFALL = 1
, GPIO_PINCFG77_IRPTEN77_INTRISE = 2
, GPIO_PINCFG77_IRPTEN77_INTANY = 3
} |
| |
| enum | GPIO_PINCFG77_FNCSEL77_Enum {
GPIO_PINCFG77_FNCSEL77_MSPI2_3 = 0
, GPIO_PINCFG77_FNCSEL77_RESERVED1 = 1
, GPIO_PINCFG77_FNCSEL77_DISP_QSPI_D3 = 2
, GPIO_PINCFG77_FNCSEL77_GPIO = 3
,
GPIO_PINCFG77_FNCSEL77_UART0CTS = 4
, GPIO_PINCFG77_FNCSEL77_DISP_D13 = 5
, GPIO_PINCFG77_FNCSEL77_CT77 = 6
, GPIO_PINCFG77_FNCSEL77_NCE77 = 7
,
GPIO_PINCFG77_FNCSEL77_OBSBUS13 = 8
, GPIO_PINCFG77_FNCSEL77_RESERVED9 = 9
, GPIO_PINCFG77_FNCSEL77_RESERVED10 = 10
, GPIO_PINCFG77_FNCSEL77_FPIO = 11
,
GPIO_PINCFG77_FNCSEL77_RESERVED12 = 12
, GPIO_PINCFG77_FNCSEL77_RESERVED13 = 13
, GPIO_PINCFG77_FNCSEL77_RESERVED14 = 14
, GPIO_PINCFG77_FNCSEL77_RESERVED15 = 15
} |
| |
| enum | GPIO_PINCFG78_NCEPOL78_Enum { GPIO_PINCFG78_NCEPOL78_LOW = 0
, GPIO_PINCFG78_NCEPOL78_HIGH = 1
} |
| |
| enum | GPIO_PINCFG78_NCESRC78_Enum {
GPIO_PINCFG78_NCESRC78_IOM0CE0 = 0
, GPIO_PINCFG78_NCESRC78_IOM0CE1 = 1
, GPIO_PINCFG78_NCESRC78_IOM0CE2 = 2
, GPIO_PINCFG78_NCESRC78_IOM0CE3 = 3
,
GPIO_PINCFG78_NCESRC78_IOM1CE0 = 4
, GPIO_PINCFG78_NCESRC78_IOM1CE1 = 5
, GPIO_PINCFG78_NCESRC78_IOM1CE2 = 6
, GPIO_PINCFG78_NCESRC78_IOM1CE3 = 7
,
GPIO_PINCFG78_NCESRC78_IOM2CE0 = 8
, GPIO_PINCFG78_NCESRC78_IOM2CE1 = 9
, GPIO_PINCFG78_NCESRC78_IOM2CE2 = 10
, GPIO_PINCFG78_NCESRC78_IOM2CE3 = 11
,
GPIO_PINCFG78_NCESRC78_IOM3CE0 = 12
, GPIO_PINCFG78_NCESRC78_IOM3CE1 = 13
, GPIO_PINCFG78_NCESRC78_IOM3CE2 = 14
, GPIO_PINCFG78_NCESRC78_IOM3CE3 = 15
,
GPIO_PINCFG78_NCESRC78_IOM4CE0 = 16
, GPIO_PINCFG78_NCESRC78_IOM4CE1 = 17
, GPIO_PINCFG78_NCESRC78_IOM4CE2 = 18
, GPIO_PINCFG78_NCESRC78_IOM4CE3 = 19
,
GPIO_PINCFG78_NCESRC78_IOM5CE0 = 20
, GPIO_PINCFG78_NCESRC78_IOM5CE1 = 21
, GPIO_PINCFG78_NCESRC78_IOM5CE2 = 22
, GPIO_PINCFG78_NCESRC78_IOM5CE3 = 23
,
GPIO_PINCFG78_NCESRC78_IOM6CE0 = 24
, GPIO_PINCFG78_NCESRC78_IOM6CE1 = 25
, GPIO_PINCFG78_NCESRC78_IOM6CE2 = 26
, GPIO_PINCFG78_NCESRC78_IOM6CE3 = 27
,
GPIO_PINCFG78_NCESRC78_IOM7CE0 = 28
, GPIO_PINCFG78_NCESRC78_IOM7CE1 = 29
, GPIO_PINCFG78_NCESRC78_IOM7CE2 = 30
, GPIO_PINCFG78_NCESRC78_IOM7CE3 = 31
,
GPIO_PINCFG78_NCESRC78_MSPI0CEN0 = 32
, GPIO_PINCFG78_NCESRC78_MSPI0CEN1 = 33
, GPIO_PINCFG78_NCESRC78_MSPI1CEN0 = 34
, GPIO_PINCFG78_NCESRC78_MSPI1CEN1 = 35
,
GPIO_PINCFG78_NCESRC78_MSPI2CEN0 = 36
, GPIO_PINCFG78_NCESRC78_MSPI2CEN1 = 37
, GPIO_PINCFG78_NCESRC78_DC_DPI_DE = 38
, GPIO_PINCFG78_NCESRC78_DISP_CONT_CSX = 39
,
GPIO_PINCFG78_NCESRC78_DC_SPI_CS_N = 40
, GPIO_PINCFG78_NCESRC78_DC_QSPI_CS_N = 41
, GPIO_PINCFG78_NCESRC78_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG78_PULLCFG78_Enum {
GPIO_PINCFG78_PULLCFG78_DIS = 0
, GPIO_PINCFG78_PULLCFG78_PD50K = 1
, GPIO_PINCFG78_PULLCFG78_PU15K = 2
, GPIO_PINCFG78_PULLCFG78_PU6K = 3
,
GPIO_PINCFG78_PULLCFG78_PU12K = 4
, GPIO_PINCFG78_PULLCFG78_PU24K = 5
, GPIO_PINCFG78_PULLCFG78_PU50K = 6
, GPIO_PINCFG78_PULLCFG78_PU100K = 7
} |
| |
| enum | GPIO_PINCFG78_DS78_Enum { GPIO_PINCFG78_DS78_0P1X = 0
, GPIO_PINCFG78_DS78_0P5X = 1
, GPIO_PINCFG78_DS78_0P75X = 2
, GPIO_PINCFG78_DS78_1P0X = 3
} |
| |
| enum | GPIO_PINCFG78_OUTCFG78_Enum { GPIO_PINCFG78_OUTCFG78_DIS = 0
, GPIO_PINCFG78_OUTCFG78_PUSHPULL = 1
, GPIO_PINCFG78_OUTCFG78_OD = 2
, GPIO_PINCFG78_OUTCFG78_TS = 3
} |
| |
| enum | GPIO_PINCFG78_IRPTEN78_Enum { GPIO_PINCFG78_IRPTEN78_DIS = 0
, GPIO_PINCFG78_IRPTEN78_INTFALL = 1
, GPIO_PINCFG78_IRPTEN78_INTRISE = 2
, GPIO_PINCFG78_IRPTEN78_INTANY = 3
} |
| |
| enum | GPIO_PINCFG78_FNCSEL78_Enum {
GPIO_PINCFG78_FNCSEL78_MSPI2_4 = 0
, GPIO_PINCFG78_FNCSEL78_RESERVED1 = 1
, GPIO_PINCFG78_FNCSEL78_DISP_QSPI_SCK = 2
, GPIO_PINCFG78_FNCSEL78_GPIO = 3
,
GPIO_PINCFG78_FNCSEL78_UART0TX = 4
, GPIO_PINCFG78_FNCSEL78_DISP_D14 = 5
, GPIO_PINCFG78_FNCSEL78_CT78 = 6
, GPIO_PINCFG78_FNCSEL78_NCE78 = 7
,
GPIO_PINCFG78_FNCSEL78_OBSBUS14 = 8
, GPIO_PINCFG78_FNCSEL78_DISP_SPI_SCK = 9
, GPIO_PINCFG78_FNCSEL78_RESERVED10 = 10
, GPIO_PINCFG78_FNCSEL78_FPIO = 11
,
GPIO_PINCFG78_FNCSEL78_RESERVED12 = 12
, GPIO_PINCFG78_FNCSEL78_RESERVED13 = 13
, GPIO_PINCFG78_FNCSEL78_RESERVED14 = 14
, GPIO_PINCFG78_FNCSEL78_RESERVED15 = 15
} |
| |
| enum | GPIO_PINCFG79_NCEPOL79_Enum { GPIO_PINCFG79_NCEPOL79_LOW = 0
, GPIO_PINCFG79_NCEPOL79_HIGH = 1
} |
| |
| enum | GPIO_PINCFG79_NCESRC79_Enum {
GPIO_PINCFG79_NCESRC79_IOM0CE0 = 0
, GPIO_PINCFG79_NCESRC79_IOM0CE1 = 1
, GPIO_PINCFG79_NCESRC79_IOM0CE2 = 2
, GPIO_PINCFG79_NCESRC79_IOM0CE3 = 3
,
GPIO_PINCFG79_NCESRC79_IOM1CE0 = 4
, GPIO_PINCFG79_NCESRC79_IOM1CE1 = 5
, GPIO_PINCFG79_NCESRC79_IOM1CE2 = 6
, GPIO_PINCFG79_NCESRC79_IOM1CE3 = 7
,
GPIO_PINCFG79_NCESRC79_IOM2CE0 = 8
, GPIO_PINCFG79_NCESRC79_IOM2CE1 = 9
, GPIO_PINCFG79_NCESRC79_IOM2CE2 = 10
, GPIO_PINCFG79_NCESRC79_IOM2CE3 = 11
,
GPIO_PINCFG79_NCESRC79_IOM3CE0 = 12
, GPIO_PINCFG79_NCESRC79_IOM3CE1 = 13
, GPIO_PINCFG79_NCESRC79_IOM3CE2 = 14
, GPIO_PINCFG79_NCESRC79_IOM3CE3 = 15
,
GPIO_PINCFG79_NCESRC79_IOM4CE0 = 16
, GPIO_PINCFG79_NCESRC79_IOM4CE1 = 17
, GPIO_PINCFG79_NCESRC79_IOM4CE2 = 18
, GPIO_PINCFG79_NCESRC79_IOM4CE3 = 19
,
GPIO_PINCFG79_NCESRC79_IOM5CE0 = 20
, GPIO_PINCFG79_NCESRC79_IOM5CE1 = 21
, GPIO_PINCFG79_NCESRC79_IOM5CE2 = 22
, GPIO_PINCFG79_NCESRC79_IOM5CE3 = 23
,
GPIO_PINCFG79_NCESRC79_IOM6CE0 = 24
, GPIO_PINCFG79_NCESRC79_IOM6CE1 = 25
, GPIO_PINCFG79_NCESRC79_IOM6CE2 = 26
, GPIO_PINCFG79_NCESRC79_IOM6CE3 = 27
,
GPIO_PINCFG79_NCESRC79_IOM7CE0 = 28
, GPIO_PINCFG79_NCESRC79_IOM7CE1 = 29
, GPIO_PINCFG79_NCESRC79_IOM7CE2 = 30
, GPIO_PINCFG79_NCESRC79_IOM7CE3 = 31
,
GPIO_PINCFG79_NCESRC79_MSPI0CEN0 = 32
, GPIO_PINCFG79_NCESRC79_MSPI0CEN1 = 33
, GPIO_PINCFG79_NCESRC79_MSPI1CEN0 = 34
, GPIO_PINCFG79_NCESRC79_MSPI1CEN1 = 35
,
GPIO_PINCFG79_NCESRC79_MSPI2CEN0 = 36
, GPIO_PINCFG79_NCESRC79_MSPI2CEN1 = 37
, GPIO_PINCFG79_NCESRC79_DC_DPI_DE = 38
, GPIO_PINCFG79_NCESRC79_DISP_CONT_CSX = 39
,
GPIO_PINCFG79_NCESRC79_DC_SPI_CS_N = 40
, GPIO_PINCFG79_NCESRC79_DC_QSPI_CS_N = 41
, GPIO_PINCFG79_NCESRC79_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG79_PULLCFG79_Enum {
GPIO_PINCFG79_PULLCFG79_DIS = 0
, GPIO_PINCFG79_PULLCFG79_PD50K = 1
, GPIO_PINCFG79_PULLCFG79_PU15K = 2
, GPIO_PINCFG79_PULLCFG79_PU6K = 3
,
GPIO_PINCFG79_PULLCFG79_PU12K = 4
, GPIO_PINCFG79_PULLCFG79_PU24K = 5
, GPIO_PINCFG79_PULLCFG79_PU50K = 6
, GPIO_PINCFG79_PULLCFG79_PU100K = 7
} |
| |
| enum | GPIO_PINCFG79_DS79_Enum { GPIO_PINCFG79_DS79_0P1X = 0
, GPIO_PINCFG79_DS79_0P5X = 1
, GPIO_PINCFG79_DS79_0P75X = 2
, GPIO_PINCFG79_DS79_1P0X = 3
} |
| |
| enum | GPIO_PINCFG79_OUTCFG79_Enum { GPIO_PINCFG79_OUTCFG79_DIS = 0
, GPIO_PINCFG79_OUTCFG79_PUSHPULL = 1
, GPIO_PINCFG79_OUTCFG79_OD = 2
, GPIO_PINCFG79_OUTCFG79_TS = 3
} |
| |
| enum | GPIO_PINCFG79_IRPTEN79_Enum { GPIO_PINCFG79_IRPTEN79_DIS = 0
, GPIO_PINCFG79_IRPTEN79_INTFALL = 1
, GPIO_PINCFG79_IRPTEN79_INTRISE = 2
, GPIO_PINCFG79_IRPTEN79_INTANY = 3
} |
| |
| enum | GPIO_PINCFG79_FNCSEL79_Enum {
GPIO_PINCFG79_FNCSEL79_MSPI2_5 = 0
, GPIO_PINCFG79_FNCSEL79_RESERVED1 = 1
, GPIO_PINCFG79_FNCSEL79_SDIF_DAT4 = 2
, GPIO_PINCFG79_FNCSEL79_GPIO = 3
,
GPIO_PINCFG79_FNCSEL79_SWO = 4
, GPIO_PINCFG79_FNCSEL79_DISP_VS = 5
, GPIO_PINCFG79_FNCSEL79_CT79 = 6
, GPIO_PINCFG79_FNCSEL79_NCE79 = 7
,
GPIO_PINCFG79_FNCSEL79_OBSBUS15 = 8
, GPIO_PINCFG79_FNCSEL79_DISP_SPI_SDI = 9
, GPIO_PINCFG79_FNCSEL79_RESERVED10 = 10
, GPIO_PINCFG79_FNCSEL79_FPIO = 11
,
GPIO_PINCFG79_FNCSEL79_RESERVED12 = 12
, GPIO_PINCFG79_FNCSEL79_RESERVED13 = 13
, GPIO_PINCFG79_FNCSEL79_RESERVED14 = 14
, GPIO_PINCFG79_FNCSEL79_RESERVED15 = 15
} |
| |
| enum | GPIO_PINCFG80_NCEPOL80_Enum { GPIO_PINCFG80_NCEPOL80_LOW = 0
, GPIO_PINCFG80_NCEPOL80_HIGH = 1
} |
| |
| enum | GPIO_PINCFG80_NCESRC80_Enum {
GPIO_PINCFG80_NCESRC80_IOM0CE0 = 0
, GPIO_PINCFG80_NCESRC80_IOM0CE1 = 1
, GPIO_PINCFG80_NCESRC80_IOM0CE2 = 2
, GPIO_PINCFG80_NCESRC80_IOM0CE3 = 3
,
GPIO_PINCFG80_NCESRC80_IOM1CE0 = 4
, GPIO_PINCFG80_NCESRC80_IOM1CE1 = 5
, GPIO_PINCFG80_NCESRC80_IOM1CE2 = 6
, GPIO_PINCFG80_NCESRC80_IOM1CE3 = 7
,
GPIO_PINCFG80_NCESRC80_IOM2CE0 = 8
, GPIO_PINCFG80_NCESRC80_IOM2CE1 = 9
, GPIO_PINCFG80_NCESRC80_IOM2CE2 = 10
, GPIO_PINCFG80_NCESRC80_IOM2CE3 = 11
,
GPIO_PINCFG80_NCESRC80_IOM3CE0 = 12
, GPIO_PINCFG80_NCESRC80_IOM3CE1 = 13
, GPIO_PINCFG80_NCESRC80_IOM3CE2 = 14
, GPIO_PINCFG80_NCESRC80_IOM3CE3 = 15
,
GPIO_PINCFG80_NCESRC80_IOM4CE0 = 16
, GPIO_PINCFG80_NCESRC80_IOM4CE1 = 17
, GPIO_PINCFG80_NCESRC80_IOM4CE2 = 18
, GPIO_PINCFG80_NCESRC80_IOM4CE3 = 19
,
GPIO_PINCFG80_NCESRC80_IOM5CE0 = 20
, GPIO_PINCFG80_NCESRC80_IOM5CE1 = 21
, GPIO_PINCFG80_NCESRC80_IOM5CE2 = 22
, GPIO_PINCFG80_NCESRC80_IOM5CE3 = 23
,
GPIO_PINCFG80_NCESRC80_IOM6CE0 = 24
, GPIO_PINCFG80_NCESRC80_IOM6CE1 = 25
, GPIO_PINCFG80_NCESRC80_IOM6CE2 = 26
, GPIO_PINCFG80_NCESRC80_IOM6CE3 = 27
,
GPIO_PINCFG80_NCESRC80_IOM7CE0 = 28
, GPIO_PINCFG80_NCESRC80_IOM7CE1 = 29
, GPIO_PINCFG80_NCESRC80_IOM7CE2 = 30
, GPIO_PINCFG80_NCESRC80_IOM7CE3 = 31
,
GPIO_PINCFG80_NCESRC80_MSPI0CEN0 = 32
, GPIO_PINCFG80_NCESRC80_MSPI0CEN1 = 33
, GPIO_PINCFG80_NCESRC80_MSPI1CEN0 = 34
, GPIO_PINCFG80_NCESRC80_MSPI1CEN1 = 35
,
GPIO_PINCFG80_NCESRC80_MSPI2CEN0 = 36
, GPIO_PINCFG80_NCESRC80_MSPI2CEN1 = 37
, GPIO_PINCFG80_NCESRC80_DC_DPI_DE = 38
, GPIO_PINCFG80_NCESRC80_DISP_CONT_CSX = 39
,
GPIO_PINCFG80_NCESRC80_DC_SPI_CS_N = 40
, GPIO_PINCFG80_NCESRC80_DC_QSPI_CS_N = 41
, GPIO_PINCFG80_NCESRC80_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG80_PULLCFG80_Enum {
GPIO_PINCFG80_PULLCFG80_DIS = 0
, GPIO_PINCFG80_PULLCFG80_PD50K = 1
, GPIO_PINCFG80_PULLCFG80_PU15K = 2
, GPIO_PINCFG80_PULLCFG80_PU6K = 3
,
GPIO_PINCFG80_PULLCFG80_PU12K = 4
, GPIO_PINCFG80_PULLCFG80_PU24K = 5
, GPIO_PINCFG80_PULLCFG80_PU50K = 6
, GPIO_PINCFG80_PULLCFG80_PU100K = 7
} |
| |
| enum | GPIO_PINCFG80_DS80_Enum { GPIO_PINCFG80_DS80_0P1X = 0
, GPIO_PINCFG80_DS80_0P5X = 1
, GPIO_PINCFG80_DS80_0P75X = 2
, GPIO_PINCFG80_DS80_1P0X = 3
} |
| |
| enum | GPIO_PINCFG80_OUTCFG80_Enum { GPIO_PINCFG80_OUTCFG80_DIS = 0
, GPIO_PINCFG80_OUTCFG80_PUSHPULL = 1
, GPIO_PINCFG80_OUTCFG80_OD = 2
, GPIO_PINCFG80_OUTCFG80_TS = 3
} |
| |
| enum | GPIO_PINCFG80_IRPTEN80_Enum { GPIO_PINCFG80_IRPTEN80_DIS = 0
, GPIO_PINCFG80_IRPTEN80_INTFALL = 1
, GPIO_PINCFG80_IRPTEN80_INTRISE = 2
, GPIO_PINCFG80_IRPTEN80_INTANY = 3
} |
| |
| enum | GPIO_PINCFG80_FNCSEL80_Enum {
GPIO_PINCFG80_FNCSEL80_MSPI2_6 = 0
, GPIO_PINCFG80_FNCSEL80_CLKOUT = 1
, GPIO_PINCFG80_FNCSEL80_SDIF_DAT5 = 2
, GPIO_PINCFG80_FNCSEL80_GPIO = 3
,
GPIO_PINCFG80_FNCSEL80_SWTRACE0 = 4
, GPIO_PINCFG80_FNCSEL80_DISP_HS = 5
, GPIO_PINCFG80_FNCSEL80_CT80 = 6
, GPIO_PINCFG80_FNCSEL80_NCE80 = 7
,
GPIO_PINCFG80_FNCSEL80_OBSBUS0 = 8
, GPIO_PINCFG80_FNCSEL80_RESERVED9 = 9
, GPIO_PINCFG80_FNCSEL80_RESERVED10 = 10
, GPIO_PINCFG80_FNCSEL80_FPIO = 11
,
GPIO_PINCFG80_FNCSEL80_RESERVED12 = 12
, GPIO_PINCFG80_FNCSEL80_RESERVED13 = 13
, GPIO_PINCFG80_FNCSEL80_RESERVED14 = 14
, GPIO_PINCFG80_FNCSEL80_RESERVED15 = 15
} |
| |
| enum | GPIO_PINCFG81_NCEPOL81_Enum { GPIO_PINCFG81_NCEPOL81_LOW = 0
, GPIO_PINCFG81_NCEPOL81_HIGH = 1
} |
| |
| enum | GPIO_PINCFG81_NCESRC81_Enum {
GPIO_PINCFG81_NCESRC81_IOM0CE0 = 0
, GPIO_PINCFG81_NCESRC81_IOM0CE1 = 1
, GPIO_PINCFG81_NCESRC81_IOM0CE2 = 2
, GPIO_PINCFG81_NCESRC81_IOM0CE3 = 3
,
GPIO_PINCFG81_NCESRC81_IOM1CE0 = 4
, GPIO_PINCFG81_NCESRC81_IOM1CE1 = 5
, GPIO_PINCFG81_NCESRC81_IOM1CE2 = 6
, GPIO_PINCFG81_NCESRC81_IOM1CE3 = 7
,
GPIO_PINCFG81_NCESRC81_IOM2CE0 = 8
, GPIO_PINCFG81_NCESRC81_IOM2CE1 = 9
, GPIO_PINCFG81_NCESRC81_IOM2CE2 = 10
, GPIO_PINCFG81_NCESRC81_IOM2CE3 = 11
,
GPIO_PINCFG81_NCESRC81_IOM3CE0 = 12
, GPIO_PINCFG81_NCESRC81_IOM3CE1 = 13
, GPIO_PINCFG81_NCESRC81_IOM3CE2 = 14
, GPIO_PINCFG81_NCESRC81_IOM3CE3 = 15
,
GPIO_PINCFG81_NCESRC81_IOM4CE0 = 16
, GPIO_PINCFG81_NCESRC81_IOM4CE1 = 17
, GPIO_PINCFG81_NCESRC81_IOM4CE2 = 18
, GPIO_PINCFG81_NCESRC81_IOM4CE3 = 19
,
GPIO_PINCFG81_NCESRC81_IOM5CE0 = 20
, GPIO_PINCFG81_NCESRC81_IOM5CE1 = 21
, GPIO_PINCFG81_NCESRC81_IOM5CE2 = 22
, GPIO_PINCFG81_NCESRC81_IOM5CE3 = 23
,
GPIO_PINCFG81_NCESRC81_IOM6CE0 = 24
, GPIO_PINCFG81_NCESRC81_IOM6CE1 = 25
, GPIO_PINCFG81_NCESRC81_IOM6CE2 = 26
, GPIO_PINCFG81_NCESRC81_IOM6CE3 = 27
,
GPIO_PINCFG81_NCESRC81_IOM7CE0 = 28
, GPIO_PINCFG81_NCESRC81_IOM7CE1 = 29
, GPIO_PINCFG81_NCESRC81_IOM7CE2 = 30
, GPIO_PINCFG81_NCESRC81_IOM7CE3 = 31
,
GPIO_PINCFG81_NCESRC81_MSPI0CEN0 = 32
, GPIO_PINCFG81_NCESRC81_MSPI0CEN1 = 33
, GPIO_PINCFG81_NCESRC81_MSPI1CEN0 = 34
, GPIO_PINCFG81_NCESRC81_MSPI1CEN1 = 35
,
GPIO_PINCFG81_NCESRC81_MSPI2CEN0 = 36
, GPIO_PINCFG81_NCESRC81_MSPI2CEN1 = 37
, GPIO_PINCFG81_NCESRC81_DC_DPI_DE = 38
, GPIO_PINCFG81_NCESRC81_DISP_CONT_CSX = 39
,
GPIO_PINCFG81_NCESRC81_DC_SPI_CS_N = 40
, GPIO_PINCFG81_NCESRC81_DC_QSPI_CS_N = 41
, GPIO_PINCFG81_NCESRC81_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG81_PULLCFG81_Enum {
GPIO_PINCFG81_PULLCFG81_DIS = 0
, GPIO_PINCFG81_PULLCFG81_PD50K = 1
, GPIO_PINCFG81_PULLCFG81_PU15K = 2
, GPIO_PINCFG81_PULLCFG81_PU6K = 3
,
GPIO_PINCFG81_PULLCFG81_PU12K = 4
, GPIO_PINCFG81_PULLCFG81_PU24K = 5
, GPIO_PINCFG81_PULLCFG81_PU50K = 6
, GPIO_PINCFG81_PULLCFG81_PU100K = 7
} |
| |
| enum | GPIO_PINCFG81_DS81_Enum { GPIO_PINCFG81_DS81_0P1X = 0
, GPIO_PINCFG81_DS81_0P5X = 1
, GPIO_PINCFG81_DS81_0P75X = 2
, GPIO_PINCFG81_DS81_1P0X = 3
} |
| |
| enum | GPIO_PINCFG81_OUTCFG81_Enum { GPIO_PINCFG81_OUTCFG81_DIS = 0
, GPIO_PINCFG81_OUTCFG81_PUSHPULL = 1
, GPIO_PINCFG81_OUTCFG81_OD = 2
, GPIO_PINCFG81_OUTCFG81_TS = 3
} |
| |
| enum | GPIO_PINCFG81_IRPTEN81_Enum { GPIO_PINCFG81_IRPTEN81_DIS = 0
, GPIO_PINCFG81_IRPTEN81_INTFALL = 1
, GPIO_PINCFG81_IRPTEN81_INTRISE = 2
, GPIO_PINCFG81_IRPTEN81_INTANY = 3
} |
| |
| enum | GPIO_PINCFG81_FNCSEL81_Enum {
GPIO_PINCFG81_FNCSEL81_MSPI2_7 = 0
, GPIO_PINCFG81_FNCSEL81_CLKOUT = 1
, GPIO_PINCFG81_FNCSEL81_SDIF_DAT6 = 2
, GPIO_PINCFG81_FNCSEL81_GPIO = 3
,
GPIO_PINCFG81_FNCSEL81_SWTRACE1 = 4
, GPIO_PINCFG81_FNCSEL81_DISP_DE = 5
, GPIO_PINCFG81_FNCSEL81_CT81 = 6
, GPIO_PINCFG81_FNCSEL81_NCE81 = 7
,
GPIO_PINCFG81_FNCSEL81_OBSBUS1 = 8
, GPIO_PINCFG81_FNCSEL81_RESERVED9 = 9
, GPIO_PINCFG81_FNCSEL81_RESERVED10 = 10
, GPIO_PINCFG81_FNCSEL81_FPIO = 11
,
GPIO_PINCFG81_FNCSEL81_RESERVED12 = 12
, GPIO_PINCFG81_FNCSEL81_RESERVED13 = 13
, GPIO_PINCFG81_FNCSEL81_RESERVED14 = 14
, GPIO_PINCFG81_FNCSEL81_RESERVED15 = 15
} |
| |
| enum | GPIO_PINCFG82_NCEPOL82_Enum { GPIO_PINCFG82_NCEPOL82_LOW = 0
, GPIO_PINCFG82_NCEPOL82_HIGH = 1
} |
| |
| enum | GPIO_PINCFG82_NCESRC82_Enum {
GPIO_PINCFG82_NCESRC82_IOM0CE0 = 0
, GPIO_PINCFG82_NCESRC82_IOM0CE1 = 1
, GPIO_PINCFG82_NCESRC82_IOM0CE2 = 2
, GPIO_PINCFG82_NCESRC82_IOM0CE3 = 3
,
GPIO_PINCFG82_NCESRC82_IOM1CE0 = 4
, GPIO_PINCFG82_NCESRC82_IOM1CE1 = 5
, GPIO_PINCFG82_NCESRC82_IOM1CE2 = 6
, GPIO_PINCFG82_NCESRC82_IOM1CE3 = 7
,
GPIO_PINCFG82_NCESRC82_IOM2CE0 = 8
, GPIO_PINCFG82_NCESRC82_IOM2CE1 = 9
, GPIO_PINCFG82_NCESRC82_IOM2CE2 = 10
, GPIO_PINCFG82_NCESRC82_IOM2CE3 = 11
,
GPIO_PINCFG82_NCESRC82_IOM3CE0 = 12
, GPIO_PINCFG82_NCESRC82_IOM3CE1 = 13
, GPIO_PINCFG82_NCESRC82_IOM3CE2 = 14
, GPIO_PINCFG82_NCESRC82_IOM3CE3 = 15
,
GPIO_PINCFG82_NCESRC82_IOM4CE0 = 16
, GPIO_PINCFG82_NCESRC82_IOM4CE1 = 17
, GPIO_PINCFG82_NCESRC82_IOM4CE2 = 18
, GPIO_PINCFG82_NCESRC82_IOM4CE3 = 19
,
GPIO_PINCFG82_NCESRC82_IOM5CE0 = 20
, GPIO_PINCFG82_NCESRC82_IOM5CE1 = 21
, GPIO_PINCFG82_NCESRC82_IOM5CE2 = 22
, GPIO_PINCFG82_NCESRC82_IOM5CE3 = 23
,
GPIO_PINCFG82_NCESRC82_IOM6CE0 = 24
, GPIO_PINCFG82_NCESRC82_IOM6CE1 = 25
, GPIO_PINCFG82_NCESRC82_IOM6CE2 = 26
, GPIO_PINCFG82_NCESRC82_IOM6CE3 = 27
,
GPIO_PINCFG82_NCESRC82_IOM7CE0 = 28
, GPIO_PINCFG82_NCESRC82_IOM7CE1 = 29
, GPIO_PINCFG82_NCESRC82_IOM7CE2 = 30
, GPIO_PINCFG82_NCESRC82_IOM7CE3 = 31
,
GPIO_PINCFG82_NCESRC82_MSPI0CEN0 = 32
, GPIO_PINCFG82_NCESRC82_MSPI0CEN1 = 33
, GPIO_PINCFG82_NCESRC82_MSPI1CEN0 = 34
, GPIO_PINCFG82_NCESRC82_MSPI1CEN1 = 35
,
GPIO_PINCFG82_NCESRC82_MSPI2CEN0 = 36
, GPIO_PINCFG82_NCESRC82_MSPI2CEN1 = 37
, GPIO_PINCFG82_NCESRC82_DC_DPI_DE = 38
, GPIO_PINCFG82_NCESRC82_DISP_CONT_CSX = 39
,
GPIO_PINCFG82_NCESRC82_DC_SPI_CS_N = 40
, GPIO_PINCFG82_NCESRC82_DC_QSPI_CS_N = 41
, GPIO_PINCFG82_NCESRC82_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG82_PULLCFG82_Enum {
GPIO_PINCFG82_PULLCFG82_DIS = 0
, GPIO_PINCFG82_PULLCFG82_PD50K = 1
, GPIO_PINCFG82_PULLCFG82_PU15K = 2
, GPIO_PINCFG82_PULLCFG82_PU6K = 3
,
GPIO_PINCFG82_PULLCFG82_PU12K = 4
, GPIO_PINCFG82_PULLCFG82_PU24K = 5
, GPIO_PINCFG82_PULLCFG82_PU50K = 6
, GPIO_PINCFG82_PULLCFG82_PU100K = 7
} |
| |
| enum | GPIO_PINCFG82_DS82_Enum { GPIO_PINCFG82_DS82_0P1X = 0
, GPIO_PINCFG82_DS82_0P5X = 1
, GPIO_PINCFG82_DS82_0P75X = 2
, GPIO_PINCFG82_DS82_1P0X = 3
} |
| |
| enum | GPIO_PINCFG82_OUTCFG82_Enum { GPIO_PINCFG82_OUTCFG82_DIS = 0
, GPIO_PINCFG82_OUTCFG82_PUSHPULL = 1
, GPIO_PINCFG82_OUTCFG82_OD = 2
, GPIO_PINCFG82_OUTCFG82_TS = 3
} |
| |
| enum | GPIO_PINCFG82_IRPTEN82_Enum { GPIO_PINCFG82_IRPTEN82_DIS = 0
, GPIO_PINCFG82_IRPTEN82_INTFALL = 1
, GPIO_PINCFG82_IRPTEN82_INTRISE = 2
, GPIO_PINCFG82_IRPTEN82_INTANY = 3
} |
| |
| enum | GPIO_PINCFG82_FNCSEL82_Enum {
GPIO_PINCFG82_FNCSEL82_MSPI2_8 = 0
, GPIO_PINCFG82_FNCSEL82_32KHzXT = 1
, GPIO_PINCFG82_FNCSEL82_SDIF_DAT7 = 2
, GPIO_PINCFG82_FNCSEL82_GPIO = 3
,
GPIO_PINCFG82_FNCSEL82_SWTRACE2 = 4
, GPIO_PINCFG82_FNCSEL82_DISP_PCLK = 5
, GPIO_PINCFG82_FNCSEL82_CT82 = 6
, GPIO_PINCFG82_FNCSEL82_NCE82 = 7
,
GPIO_PINCFG82_FNCSEL82_OBSBUS2 = 8
, GPIO_PINCFG82_FNCSEL82_RESERVED9 = 9
, GPIO_PINCFG82_FNCSEL82_RESERVED10 = 10
, GPIO_PINCFG82_FNCSEL82_FPIO = 11
,
GPIO_PINCFG82_FNCSEL82_RESERVED12 = 12
, GPIO_PINCFG82_FNCSEL82_RESERVED13 = 13
, GPIO_PINCFG82_FNCSEL82_RESERVED14 = 14
, GPIO_PINCFG82_FNCSEL82_RESERVED15 = 15
} |
| |
| enum | GPIO_PINCFG83_NCEPOL83_Enum { GPIO_PINCFG83_NCEPOL83_LOW = 0
, GPIO_PINCFG83_NCEPOL83_HIGH = 1
} |
| |
| enum | GPIO_PINCFG83_NCESRC83_Enum {
GPIO_PINCFG83_NCESRC83_IOM0CE0 = 0
, GPIO_PINCFG83_NCESRC83_IOM0CE1 = 1
, GPIO_PINCFG83_NCESRC83_IOM0CE2 = 2
, GPIO_PINCFG83_NCESRC83_IOM0CE3 = 3
,
GPIO_PINCFG83_NCESRC83_IOM1CE0 = 4
, GPIO_PINCFG83_NCESRC83_IOM1CE1 = 5
, GPIO_PINCFG83_NCESRC83_IOM1CE2 = 6
, GPIO_PINCFG83_NCESRC83_IOM1CE3 = 7
,
GPIO_PINCFG83_NCESRC83_IOM2CE0 = 8
, GPIO_PINCFG83_NCESRC83_IOM2CE1 = 9
, GPIO_PINCFG83_NCESRC83_IOM2CE2 = 10
, GPIO_PINCFG83_NCESRC83_IOM2CE3 = 11
,
GPIO_PINCFG83_NCESRC83_IOM3CE0 = 12
, GPIO_PINCFG83_NCESRC83_IOM3CE1 = 13
, GPIO_PINCFG83_NCESRC83_IOM3CE2 = 14
, GPIO_PINCFG83_NCESRC83_IOM3CE3 = 15
,
GPIO_PINCFG83_NCESRC83_IOM4CE0 = 16
, GPIO_PINCFG83_NCESRC83_IOM4CE1 = 17
, GPIO_PINCFG83_NCESRC83_IOM4CE2 = 18
, GPIO_PINCFG83_NCESRC83_IOM4CE3 = 19
,
GPIO_PINCFG83_NCESRC83_IOM5CE0 = 20
, GPIO_PINCFG83_NCESRC83_IOM5CE1 = 21
, GPIO_PINCFG83_NCESRC83_IOM5CE2 = 22
, GPIO_PINCFG83_NCESRC83_IOM5CE3 = 23
,
GPIO_PINCFG83_NCESRC83_IOM6CE0 = 24
, GPIO_PINCFG83_NCESRC83_IOM6CE1 = 25
, GPIO_PINCFG83_NCESRC83_IOM6CE2 = 26
, GPIO_PINCFG83_NCESRC83_IOM6CE3 = 27
,
GPIO_PINCFG83_NCESRC83_IOM7CE0 = 28
, GPIO_PINCFG83_NCESRC83_IOM7CE1 = 29
, GPIO_PINCFG83_NCESRC83_IOM7CE2 = 30
, GPIO_PINCFG83_NCESRC83_IOM7CE3 = 31
,
GPIO_PINCFG83_NCESRC83_MSPI0CEN0 = 32
, GPIO_PINCFG83_NCESRC83_MSPI0CEN1 = 33
, GPIO_PINCFG83_NCESRC83_MSPI1CEN0 = 34
, GPIO_PINCFG83_NCESRC83_MSPI1CEN1 = 35
,
GPIO_PINCFG83_NCESRC83_MSPI2CEN0 = 36
, GPIO_PINCFG83_NCESRC83_MSPI2CEN1 = 37
, GPIO_PINCFG83_NCESRC83_DC_DPI_DE = 38
, GPIO_PINCFG83_NCESRC83_DISP_CONT_CSX = 39
,
GPIO_PINCFG83_NCESRC83_DC_SPI_CS_N = 40
, GPIO_PINCFG83_NCESRC83_DC_QSPI_CS_N = 41
, GPIO_PINCFG83_NCESRC83_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG83_PULLCFG83_Enum {
GPIO_PINCFG83_PULLCFG83_DIS = 0
, GPIO_PINCFG83_PULLCFG83_PD50K = 1
, GPIO_PINCFG83_PULLCFG83_PU15K = 2
, GPIO_PINCFG83_PULLCFG83_PU6K = 3
,
GPIO_PINCFG83_PULLCFG83_PU12K = 4
, GPIO_PINCFG83_PULLCFG83_PU24K = 5
, GPIO_PINCFG83_PULLCFG83_PU50K = 6
, GPIO_PINCFG83_PULLCFG83_PU100K = 7
} |
| |
| enum | GPIO_PINCFG83_DS83_Enum { GPIO_PINCFG83_DS83_0P1X = 0
, GPIO_PINCFG83_DS83_0P5X = 1
, GPIO_PINCFG83_DS83_0P75X = 2
, GPIO_PINCFG83_DS83_1P0X = 3
} |
| |
| enum | GPIO_PINCFG83_OUTCFG83_Enum { GPIO_PINCFG83_OUTCFG83_DIS = 0
, GPIO_PINCFG83_OUTCFG83_PUSHPULL = 1
, GPIO_PINCFG83_OUTCFG83_OD = 2
, GPIO_PINCFG83_OUTCFG83_TS = 3
} |
| |
| enum | GPIO_PINCFG83_IRPTEN83_Enum { GPIO_PINCFG83_IRPTEN83_DIS = 0
, GPIO_PINCFG83_IRPTEN83_INTFALL = 1
, GPIO_PINCFG83_IRPTEN83_INTRISE = 2
, GPIO_PINCFG83_IRPTEN83_INTANY = 3
} |
| |
| enum | GPIO_PINCFG83_FNCSEL83_Enum {
GPIO_PINCFG83_FNCSEL83_MSPI2_9 = 0
, GPIO_PINCFG83_FNCSEL83_32KHzXT = 1
, GPIO_PINCFG83_FNCSEL83_SDIF_CMD = 2
, GPIO_PINCFG83_FNCSEL83_GPIO = 3
,
GPIO_PINCFG83_FNCSEL83_SWTRACE3 = 4
, GPIO_PINCFG83_FNCSEL83_DISP_SD = 5
, GPIO_PINCFG83_FNCSEL83_CT83 = 6
, GPIO_PINCFG83_FNCSEL83_NCE83 = 7
,
GPIO_PINCFG83_FNCSEL83_OBSBUS3 = 8
, GPIO_PINCFG83_FNCSEL83_RESERVED9 = 9
, GPIO_PINCFG83_FNCSEL83_RESERVED10 = 10
, GPIO_PINCFG83_FNCSEL83_FPIO = 11
,
GPIO_PINCFG83_FNCSEL83_RESERVED12 = 12
, GPIO_PINCFG83_FNCSEL83_RESERVED13 = 13
, GPIO_PINCFG83_FNCSEL83_RESERVED14 = 14
, GPIO_PINCFG83_FNCSEL83_RESERVED15 = 15
} |
| |
| enum | GPIO_PINCFG84_NCEPOL84_Enum { GPIO_PINCFG84_NCEPOL84_LOW = 0
, GPIO_PINCFG84_NCEPOL84_HIGH = 1
} |
| |
| enum | GPIO_PINCFG84_NCESRC84_Enum {
GPIO_PINCFG84_NCESRC84_IOM0CE0 = 0
, GPIO_PINCFG84_NCESRC84_IOM0CE1 = 1
, GPIO_PINCFG84_NCESRC84_IOM0CE2 = 2
, GPIO_PINCFG84_NCESRC84_IOM0CE3 = 3
,
GPIO_PINCFG84_NCESRC84_IOM1CE0 = 4
, GPIO_PINCFG84_NCESRC84_IOM1CE1 = 5
, GPIO_PINCFG84_NCESRC84_IOM1CE2 = 6
, GPIO_PINCFG84_NCESRC84_IOM1CE3 = 7
,
GPIO_PINCFG84_NCESRC84_IOM2CE0 = 8
, GPIO_PINCFG84_NCESRC84_IOM2CE1 = 9
, GPIO_PINCFG84_NCESRC84_IOM2CE2 = 10
, GPIO_PINCFG84_NCESRC84_IOM2CE3 = 11
,
GPIO_PINCFG84_NCESRC84_IOM3CE0 = 12
, GPIO_PINCFG84_NCESRC84_IOM3CE1 = 13
, GPIO_PINCFG84_NCESRC84_IOM3CE2 = 14
, GPIO_PINCFG84_NCESRC84_IOM3CE3 = 15
,
GPIO_PINCFG84_NCESRC84_IOM4CE0 = 16
, GPIO_PINCFG84_NCESRC84_IOM4CE1 = 17
, GPIO_PINCFG84_NCESRC84_IOM4CE2 = 18
, GPIO_PINCFG84_NCESRC84_IOM4CE3 = 19
,
GPIO_PINCFG84_NCESRC84_IOM5CE0 = 20
, GPIO_PINCFG84_NCESRC84_IOM5CE1 = 21
, GPIO_PINCFG84_NCESRC84_IOM5CE2 = 22
, GPIO_PINCFG84_NCESRC84_IOM5CE3 = 23
,
GPIO_PINCFG84_NCESRC84_IOM6CE0 = 24
, GPIO_PINCFG84_NCESRC84_IOM6CE1 = 25
, GPIO_PINCFG84_NCESRC84_IOM6CE2 = 26
, GPIO_PINCFG84_NCESRC84_IOM6CE3 = 27
,
GPIO_PINCFG84_NCESRC84_IOM7CE0 = 28
, GPIO_PINCFG84_NCESRC84_IOM7CE1 = 29
, GPIO_PINCFG84_NCESRC84_IOM7CE2 = 30
, GPIO_PINCFG84_NCESRC84_IOM7CE3 = 31
,
GPIO_PINCFG84_NCESRC84_MSPI0CEN0 = 32
, GPIO_PINCFG84_NCESRC84_MSPI0CEN1 = 33
, GPIO_PINCFG84_NCESRC84_MSPI1CEN0 = 34
, GPIO_PINCFG84_NCESRC84_MSPI1CEN1 = 35
,
GPIO_PINCFG84_NCESRC84_MSPI2CEN0 = 36
, GPIO_PINCFG84_NCESRC84_MSPI2CEN1 = 37
, GPIO_PINCFG84_NCESRC84_DC_DPI_DE = 38
, GPIO_PINCFG84_NCESRC84_DISP_CONT_CSX = 39
,
GPIO_PINCFG84_NCESRC84_DC_SPI_CS_N = 40
, GPIO_PINCFG84_NCESRC84_DC_QSPI_CS_N = 41
, GPIO_PINCFG84_NCESRC84_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG84_PULLCFG84_Enum {
GPIO_PINCFG84_PULLCFG84_DIS = 0
, GPIO_PINCFG84_PULLCFG84_PD50K = 1
, GPIO_PINCFG84_PULLCFG84_PU15K = 2
, GPIO_PINCFG84_PULLCFG84_PU6K = 3
,
GPIO_PINCFG84_PULLCFG84_PU12K = 4
, GPIO_PINCFG84_PULLCFG84_PU24K = 5
, GPIO_PINCFG84_PULLCFG84_PU50K = 6
, GPIO_PINCFG84_PULLCFG84_PU100K = 7
} |
| |
| enum | GPIO_PINCFG84_DS84_Enum { GPIO_PINCFG84_DS84_0P1X = 0
, GPIO_PINCFG84_DS84_0P5X = 1
, GPIO_PINCFG84_DS84_0P75X = 2
, GPIO_PINCFG84_DS84_1P0X = 3
} |
| |
| enum | GPIO_PINCFG84_OUTCFG84_Enum { GPIO_PINCFG84_OUTCFG84_DIS = 0
, GPIO_PINCFG84_OUTCFG84_PUSHPULL = 1
, GPIO_PINCFG84_OUTCFG84_OD = 2
, GPIO_PINCFG84_OUTCFG84_TS = 3
} |
| |
| enum | GPIO_PINCFG84_IRPTEN84_Enum { GPIO_PINCFG84_IRPTEN84_DIS = 0
, GPIO_PINCFG84_IRPTEN84_INTFALL = 1
, GPIO_PINCFG84_IRPTEN84_INTRISE = 2
, GPIO_PINCFG84_IRPTEN84_INTANY = 3
} |
| |
| enum | GPIO_PINCFG84_FNCSEL84_Enum {
GPIO_PINCFG84_FNCSEL84_RESERVED0 = 0
, GPIO_PINCFG84_FNCSEL84_RESERVED1 = 1
, GPIO_PINCFG84_FNCSEL84_SDIF_DAT0 = 2
, GPIO_PINCFG84_FNCSEL84_GPIO = 3
,
GPIO_PINCFG84_FNCSEL84_RESERVED4 = 4
, GPIO_PINCFG84_FNCSEL84_RESERVED5 = 5
, GPIO_PINCFG84_FNCSEL84_CT84 = 6
, GPIO_PINCFG84_FNCSEL84_NCE84 = 7
,
GPIO_PINCFG84_FNCSEL84_OBSBUS4 = 8
, GPIO_PINCFG84_FNCSEL84_RESERVED9 = 9
, GPIO_PINCFG84_FNCSEL84_RESERVED10 = 10
, GPIO_PINCFG84_FNCSEL84_FPIO = 11
,
GPIO_PINCFG84_FNCSEL84_RESERVED12 = 12
, GPIO_PINCFG84_FNCSEL84_RESERVED13 = 13
, GPIO_PINCFG84_FNCSEL84_RESERVED14 = 14
, GPIO_PINCFG84_FNCSEL84_RESERVED15 = 15
} |
| |
| enum | GPIO_PINCFG85_NCEPOL85_Enum { GPIO_PINCFG85_NCEPOL85_LOW = 0
, GPIO_PINCFG85_NCEPOL85_HIGH = 1
} |
| |
| enum | GPIO_PINCFG85_NCESRC85_Enum {
GPIO_PINCFG85_NCESRC85_IOM0CE0 = 0
, GPIO_PINCFG85_NCESRC85_IOM0CE1 = 1
, GPIO_PINCFG85_NCESRC85_IOM0CE2 = 2
, GPIO_PINCFG85_NCESRC85_IOM0CE3 = 3
,
GPIO_PINCFG85_NCESRC85_IOM1CE0 = 4
, GPIO_PINCFG85_NCESRC85_IOM1CE1 = 5
, GPIO_PINCFG85_NCESRC85_IOM1CE2 = 6
, GPIO_PINCFG85_NCESRC85_IOM1CE3 = 7
,
GPIO_PINCFG85_NCESRC85_IOM2CE0 = 8
, GPIO_PINCFG85_NCESRC85_IOM2CE1 = 9
, GPIO_PINCFG85_NCESRC85_IOM2CE2 = 10
, GPIO_PINCFG85_NCESRC85_IOM2CE3 = 11
,
GPIO_PINCFG85_NCESRC85_IOM3CE0 = 12
, GPIO_PINCFG85_NCESRC85_IOM3CE1 = 13
, GPIO_PINCFG85_NCESRC85_IOM3CE2 = 14
, GPIO_PINCFG85_NCESRC85_IOM3CE3 = 15
,
GPIO_PINCFG85_NCESRC85_IOM4CE0 = 16
, GPIO_PINCFG85_NCESRC85_IOM4CE1 = 17
, GPIO_PINCFG85_NCESRC85_IOM4CE2 = 18
, GPIO_PINCFG85_NCESRC85_IOM4CE3 = 19
,
GPIO_PINCFG85_NCESRC85_IOM5CE0 = 20
, GPIO_PINCFG85_NCESRC85_IOM5CE1 = 21
, GPIO_PINCFG85_NCESRC85_IOM5CE2 = 22
, GPIO_PINCFG85_NCESRC85_IOM5CE3 = 23
,
GPIO_PINCFG85_NCESRC85_IOM6CE0 = 24
, GPIO_PINCFG85_NCESRC85_IOM6CE1 = 25
, GPIO_PINCFG85_NCESRC85_IOM6CE2 = 26
, GPIO_PINCFG85_NCESRC85_IOM6CE3 = 27
,
GPIO_PINCFG85_NCESRC85_IOM7CE0 = 28
, GPIO_PINCFG85_NCESRC85_IOM7CE1 = 29
, GPIO_PINCFG85_NCESRC85_IOM7CE2 = 30
, GPIO_PINCFG85_NCESRC85_IOM7CE3 = 31
,
GPIO_PINCFG85_NCESRC85_MSPI0CEN0 = 32
, GPIO_PINCFG85_NCESRC85_MSPI0CEN1 = 33
, GPIO_PINCFG85_NCESRC85_MSPI1CEN0 = 34
, GPIO_PINCFG85_NCESRC85_MSPI1CEN1 = 35
,
GPIO_PINCFG85_NCESRC85_MSPI2CEN0 = 36
, GPIO_PINCFG85_NCESRC85_MSPI2CEN1 = 37
, GPIO_PINCFG85_NCESRC85_DC_DPI_DE = 38
, GPIO_PINCFG85_NCESRC85_DISP_CONT_CSX = 39
,
GPIO_PINCFG85_NCESRC85_DC_SPI_CS_N = 40
, GPIO_PINCFG85_NCESRC85_DC_QSPI_CS_N = 41
, GPIO_PINCFG85_NCESRC85_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG85_PULLCFG85_Enum {
GPIO_PINCFG85_PULLCFG85_DIS = 0
, GPIO_PINCFG85_PULLCFG85_PD50K = 1
, GPIO_PINCFG85_PULLCFG85_PU15K = 2
, GPIO_PINCFG85_PULLCFG85_PU6K = 3
,
GPIO_PINCFG85_PULLCFG85_PU12K = 4
, GPIO_PINCFG85_PULLCFG85_PU24K = 5
, GPIO_PINCFG85_PULLCFG85_PU50K = 6
, GPIO_PINCFG85_PULLCFG85_PU100K = 7
} |
| |
| enum | GPIO_PINCFG85_DS85_Enum { GPIO_PINCFG85_DS85_0P1X = 0
, GPIO_PINCFG85_DS85_0P5X = 1
, GPIO_PINCFG85_DS85_0P75X = 2
, GPIO_PINCFG85_DS85_1P0X = 3
} |
| |
| enum | GPIO_PINCFG85_OUTCFG85_Enum { GPIO_PINCFG85_OUTCFG85_DIS = 0
, GPIO_PINCFG85_OUTCFG85_PUSHPULL = 1
, GPIO_PINCFG85_OUTCFG85_OD = 2
, GPIO_PINCFG85_OUTCFG85_TS = 3
} |
| |
| enum | GPIO_PINCFG85_IRPTEN85_Enum { GPIO_PINCFG85_IRPTEN85_DIS = 0
, GPIO_PINCFG85_IRPTEN85_INTFALL = 1
, GPIO_PINCFG85_IRPTEN85_INTRISE = 2
, GPIO_PINCFG85_IRPTEN85_INTANY = 3
} |
| |
| enum | GPIO_PINCFG85_FNCSEL85_Enum {
GPIO_PINCFG85_FNCSEL85_RESERVED0 = 0
, GPIO_PINCFG85_FNCSEL85_RESERVED1 = 1
, GPIO_PINCFG85_FNCSEL85_SDIF_DAT1 = 2
, GPIO_PINCFG85_FNCSEL85_GPIO = 3
,
GPIO_PINCFG85_FNCSEL85_RESERVED4 = 4
, GPIO_PINCFG85_FNCSEL85_RESERVED5 = 5
, GPIO_PINCFG85_FNCSEL85_CT85 = 6
, GPIO_PINCFG85_FNCSEL85_NCE85 = 7
,
GPIO_PINCFG85_FNCSEL85_OBSBUS5 = 8
, GPIO_PINCFG85_FNCSEL85_RESERVED9 = 9
, GPIO_PINCFG85_FNCSEL85_RESERVED10 = 10
, GPIO_PINCFG85_FNCSEL85_FPIO = 11
,
GPIO_PINCFG85_FNCSEL85_RESERVED12 = 12
, GPIO_PINCFG85_FNCSEL85_RESERVED13 = 13
, GPIO_PINCFG85_FNCSEL85_RESERVED14 = 14
, GPIO_PINCFG85_FNCSEL85_RESERVED15 = 15
} |
| |
| enum | GPIO_PINCFG86_NCEPOL86_Enum { GPIO_PINCFG86_NCEPOL86_LOW = 0
, GPIO_PINCFG86_NCEPOL86_HIGH = 1
} |
| |
| enum | GPIO_PINCFG86_NCESRC86_Enum {
GPIO_PINCFG86_NCESRC86_IOM0CE0 = 0
, GPIO_PINCFG86_NCESRC86_IOM0CE1 = 1
, GPIO_PINCFG86_NCESRC86_IOM0CE2 = 2
, GPIO_PINCFG86_NCESRC86_IOM0CE3 = 3
,
GPIO_PINCFG86_NCESRC86_IOM1CE0 = 4
, GPIO_PINCFG86_NCESRC86_IOM1CE1 = 5
, GPIO_PINCFG86_NCESRC86_IOM1CE2 = 6
, GPIO_PINCFG86_NCESRC86_IOM1CE3 = 7
,
GPIO_PINCFG86_NCESRC86_IOM2CE0 = 8
, GPIO_PINCFG86_NCESRC86_IOM2CE1 = 9
, GPIO_PINCFG86_NCESRC86_IOM2CE2 = 10
, GPIO_PINCFG86_NCESRC86_IOM2CE3 = 11
,
GPIO_PINCFG86_NCESRC86_IOM3CE0 = 12
, GPIO_PINCFG86_NCESRC86_IOM3CE1 = 13
, GPIO_PINCFG86_NCESRC86_IOM3CE2 = 14
, GPIO_PINCFG86_NCESRC86_IOM3CE3 = 15
,
GPIO_PINCFG86_NCESRC86_IOM4CE0 = 16
, GPIO_PINCFG86_NCESRC86_IOM4CE1 = 17
, GPIO_PINCFG86_NCESRC86_IOM4CE2 = 18
, GPIO_PINCFG86_NCESRC86_IOM4CE3 = 19
,
GPIO_PINCFG86_NCESRC86_IOM5CE0 = 20
, GPIO_PINCFG86_NCESRC86_IOM5CE1 = 21
, GPIO_PINCFG86_NCESRC86_IOM5CE2 = 22
, GPIO_PINCFG86_NCESRC86_IOM5CE3 = 23
,
GPIO_PINCFG86_NCESRC86_IOM6CE0 = 24
, GPIO_PINCFG86_NCESRC86_IOM6CE1 = 25
, GPIO_PINCFG86_NCESRC86_IOM6CE2 = 26
, GPIO_PINCFG86_NCESRC86_IOM6CE3 = 27
,
GPIO_PINCFG86_NCESRC86_IOM7CE0 = 28
, GPIO_PINCFG86_NCESRC86_IOM7CE1 = 29
, GPIO_PINCFG86_NCESRC86_IOM7CE2 = 30
, GPIO_PINCFG86_NCESRC86_IOM7CE3 = 31
,
GPIO_PINCFG86_NCESRC86_MSPI0CEN0 = 32
, GPIO_PINCFG86_NCESRC86_MSPI0CEN1 = 33
, GPIO_PINCFG86_NCESRC86_MSPI1CEN0 = 34
, GPIO_PINCFG86_NCESRC86_MSPI1CEN1 = 35
,
GPIO_PINCFG86_NCESRC86_MSPI2CEN0 = 36
, GPIO_PINCFG86_NCESRC86_MSPI2CEN1 = 37
, GPIO_PINCFG86_NCESRC86_DC_DPI_DE = 38
, GPIO_PINCFG86_NCESRC86_DISP_CONT_CSX = 39
,
GPIO_PINCFG86_NCESRC86_DC_SPI_CS_N = 40
, GPIO_PINCFG86_NCESRC86_DC_QSPI_CS_N = 41
, GPIO_PINCFG86_NCESRC86_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG86_PULLCFG86_Enum {
GPIO_PINCFG86_PULLCFG86_DIS = 0
, GPIO_PINCFG86_PULLCFG86_PD50K = 1
, GPIO_PINCFG86_PULLCFG86_PU15K = 2
, GPIO_PINCFG86_PULLCFG86_PU6K = 3
,
GPIO_PINCFG86_PULLCFG86_PU12K = 4
, GPIO_PINCFG86_PULLCFG86_PU24K = 5
, GPIO_PINCFG86_PULLCFG86_PU50K = 6
, GPIO_PINCFG86_PULLCFG86_PU100K = 7
} |
| |
| enum | GPIO_PINCFG86_DS86_Enum { GPIO_PINCFG86_DS86_0P1X = 0
, GPIO_PINCFG86_DS86_0P5X = 1
, GPIO_PINCFG86_DS86_0P75X = 2
, GPIO_PINCFG86_DS86_1P0X = 3
} |
| |
| enum | GPIO_PINCFG86_OUTCFG86_Enum { GPIO_PINCFG86_OUTCFG86_DIS = 0
, GPIO_PINCFG86_OUTCFG86_PUSHPULL = 1
, GPIO_PINCFG86_OUTCFG86_OD = 2
, GPIO_PINCFG86_OUTCFG86_TS = 3
} |
| |
| enum | GPIO_PINCFG86_IRPTEN86_Enum { GPIO_PINCFG86_IRPTEN86_DIS = 0
, GPIO_PINCFG86_IRPTEN86_INTFALL = 1
, GPIO_PINCFG86_IRPTEN86_INTRISE = 2
, GPIO_PINCFG86_IRPTEN86_INTANY = 3
} |
| |
| enum | GPIO_PINCFG86_FNCSEL86_Enum {
GPIO_PINCFG86_FNCSEL86_RESERVED0 = 0
, GPIO_PINCFG86_FNCSEL86_RESERVED1 = 1
, GPIO_PINCFG86_FNCSEL86_SDIF_DAT2 = 2
, GPIO_PINCFG86_FNCSEL86_GPIO = 3
,
GPIO_PINCFG86_FNCSEL86_RESERVED4 = 4
, GPIO_PINCFG86_FNCSEL86_RESERVED5 = 5
, GPIO_PINCFG86_FNCSEL86_CT86 = 6
, GPIO_PINCFG86_FNCSEL86_NCE86 = 7
,
GPIO_PINCFG86_FNCSEL86_OBSBUS6 = 8
, GPIO_PINCFG86_FNCSEL86_RESERVED9 = 9
, GPIO_PINCFG86_FNCSEL86_RESERVED10 = 10
, GPIO_PINCFG86_FNCSEL86_FPIO = 11
,
GPIO_PINCFG86_FNCSEL86_RESERVED12 = 12
, GPIO_PINCFG86_FNCSEL86_RESERVED13 = 13
, GPIO_PINCFG86_FNCSEL86_RESERVED14 = 14
, GPIO_PINCFG86_FNCSEL86_RESERVED15 = 15
} |
| |
| enum | GPIO_PINCFG87_NCEPOL87_Enum { GPIO_PINCFG87_NCEPOL87_LOW = 0
, GPIO_PINCFG87_NCEPOL87_HIGH = 1
} |
| |
| enum | GPIO_PINCFG87_NCESRC87_Enum {
GPIO_PINCFG87_NCESRC87_IOM0CE0 = 0
, GPIO_PINCFG87_NCESRC87_IOM0CE1 = 1
, GPIO_PINCFG87_NCESRC87_IOM0CE2 = 2
, GPIO_PINCFG87_NCESRC87_IOM0CE3 = 3
,
GPIO_PINCFG87_NCESRC87_IOM1CE0 = 4
, GPIO_PINCFG87_NCESRC87_IOM1CE1 = 5
, GPIO_PINCFG87_NCESRC87_IOM1CE2 = 6
, GPIO_PINCFG87_NCESRC87_IOM1CE3 = 7
,
GPIO_PINCFG87_NCESRC87_IOM2CE0 = 8
, GPIO_PINCFG87_NCESRC87_IOM2CE1 = 9
, GPIO_PINCFG87_NCESRC87_IOM2CE2 = 10
, GPIO_PINCFG87_NCESRC87_IOM2CE3 = 11
,
GPIO_PINCFG87_NCESRC87_IOM3CE0 = 12
, GPIO_PINCFG87_NCESRC87_IOM3CE1 = 13
, GPIO_PINCFG87_NCESRC87_IOM3CE2 = 14
, GPIO_PINCFG87_NCESRC87_IOM3CE3 = 15
,
GPIO_PINCFG87_NCESRC87_IOM4CE0 = 16
, GPIO_PINCFG87_NCESRC87_IOM4CE1 = 17
, GPIO_PINCFG87_NCESRC87_IOM4CE2 = 18
, GPIO_PINCFG87_NCESRC87_IOM4CE3 = 19
,
GPIO_PINCFG87_NCESRC87_IOM5CE0 = 20
, GPIO_PINCFG87_NCESRC87_IOM5CE1 = 21
, GPIO_PINCFG87_NCESRC87_IOM5CE2 = 22
, GPIO_PINCFG87_NCESRC87_IOM5CE3 = 23
,
GPIO_PINCFG87_NCESRC87_IOM6CE0 = 24
, GPIO_PINCFG87_NCESRC87_IOM6CE1 = 25
, GPIO_PINCFG87_NCESRC87_IOM6CE2 = 26
, GPIO_PINCFG87_NCESRC87_IOM6CE3 = 27
,
GPIO_PINCFG87_NCESRC87_IOM7CE0 = 28
, GPIO_PINCFG87_NCESRC87_IOM7CE1 = 29
, GPIO_PINCFG87_NCESRC87_IOM7CE2 = 30
, GPIO_PINCFG87_NCESRC87_IOM7CE3 = 31
,
GPIO_PINCFG87_NCESRC87_MSPI0CEN0 = 32
, GPIO_PINCFG87_NCESRC87_MSPI0CEN1 = 33
, GPIO_PINCFG87_NCESRC87_MSPI1CEN0 = 34
, GPIO_PINCFG87_NCESRC87_MSPI1CEN1 = 35
,
GPIO_PINCFG87_NCESRC87_MSPI2CEN0 = 36
, GPIO_PINCFG87_NCESRC87_MSPI2CEN1 = 37
, GPIO_PINCFG87_NCESRC87_DC_DPI_DE = 38
, GPIO_PINCFG87_NCESRC87_DISP_CONT_CSX = 39
,
GPIO_PINCFG87_NCESRC87_DC_SPI_CS_N = 40
, GPIO_PINCFG87_NCESRC87_DC_QSPI_CS_N = 41
, GPIO_PINCFG87_NCESRC87_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG87_PULLCFG87_Enum {
GPIO_PINCFG87_PULLCFG87_DIS = 0
, GPIO_PINCFG87_PULLCFG87_PD50K = 1
, GPIO_PINCFG87_PULLCFG87_PU15K = 2
, GPIO_PINCFG87_PULLCFG87_PU6K = 3
,
GPIO_PINCFG87_PULLCFG87_PU12K = 4
, GPIO_PINCFG87_PULLCFG87_PU24K = 5
, GPIO_PINCFG87_PULLCFG87_PU50K = 6
, GPIO_PINCFG87_PULLCFG87_PU100K = 7
} |
| |
| enum | GPIO_PINCFG87_DS87_Enum { GPIO_PINCFG87_DS87_0P1X = 0
, GPIO_PINCFG87_DS87_0P5X = 1
, GPIO_PINCFG87_DS87_0P75X = 2
, GPIO_PINCFG87_DS87_1P0X = 3
} |
| |
| enum | GPIO_PINCFG87_OUTCFG87_Enum { GPIO_PINCFG87_OUTCFG87_DIS = 0
, GPIO_PINCFG87_OUTCFG87_PUSHPULL = 1
, GPIO_PINCFG87_OUTCFG87_OD = 2
, GPIO_PINCFG87_OUTCFG87_TS = 3
} |
| |
| enum | GPIO_PINCFG87_IRPTEN87_Enum { GPIO_PINCFG87_IRPTEN87_DIS = 0
, GPIO_PINCFG87_IRPTEN87_INTFALL = 1
, GPIO_PINCFG87_IRPTEN87_INTRISE = 2
, GPIO_PINCFG87_IRPTEN87_INTANY = 3
} |
| |
| enum | GPIO_PINCFG87_FNCSEL87_Enum {
GPIO_PINCFG87_FNCSEL87_RESERVED0 = 0
, GPIO_PINCFG87_FNCSEL87_RESERVED1 = 1
, GPIO_PINCFG87_FNCSEL87_SDIF_DAT3 = 2
, GPIO_PINCFG87_FNCSEL87_GPIO = 3
,
GPIO_PINCFG87_FNCSEL87_RESERVED4 = 4
, GPIO_PINCFG87_FNCSEL87_RESERVED5 = 5
, GPIO_PINCFG87_FNCSEL87_CT87 = 6
, GPIO_PINCFG87_FNCSEL87_NCE87 = 7
,
GPIO_PINCFG87_FNCSEL87_OBSBUS7 = 8
, GPIO_PINCFG87_FNCSEL87_DISP_TE = 9
, GPIO_PINCFG87_FNCSEL87_RESERVED10 = 10
, GPIO_PINCFG87_FNCSEL87_FPIO = 11
,
GPIO_PINCFG87_FNCSEL87_RESERVED12 = 12
, GPIO_PINCFG87_FNCSEL87_RESERVED13 = 13
, GPIO_PINCFG87_FNCSEL87_RESERVED14 = 14
, GPIO_PINCFG87_FNCSEL87_RESERVED15 = 15
} |
| |
| enum | GPIO_PINCFG88_NCEPOL88_Enum { GPIO_PINCFG88_NCEPOL88_LOW = 0
, GPIO_PINCFG88_NCEPOL88_HIGH = 1
} |
| |
| enum | GPIO_PINCFG88_NCESRC88_Enum {
GPIO_PINCFG88_NCESRC88_IOM0CE0 = 0
, GPIO_PINCFG88_NCESRC88_IOM0CE1 = 1
, GPIO_PINCFG88_NCESRC88_IOM0CE2 = 2
, GPIO_PINCFG88_NCESRC88_IOM0CE3 = 3
,
GPIO_PINCFG88_NCESRC88_IOM1CE0 = 4
, GPIO_PINCFG88_NCESRC88_IOM1CE1 = 5
, GPIO_PINCFG88_NCESRC88_IOM1CE2 = 6
, GPIO_PINCFG88_NCESRC88_IOM1CE3 = 7
,
GPIO_PINCFG88_NCESRC88_IOM2CE0 = 8
, GPIO_PINCFG88_NCESRC88_IOM2CE1 = 9
, GPIO_PINCFG88_NCESRC88_IOM2CE2 = 10
, GPIO_PINCFG88_NCESRC88_IOM2CE3 = 11
,
GPIO_PINCFG88_NCESRC88_IOM3CE0 = 12
, GPIO_PINCFG88_NCESRC88_IOM3CE1 = 13
, GPIO_PINCFG88_NCESRC88_IOM3CE2 = 14
, GPIO_PINCFG88_NCESRC88_IOM3CE3 = 15
,
GPIO_PINCFG88_NCESRC88_IOM4CE0 = 16
, GPIO_PINCFG88_NCESRC88_IOM4CE1 = 17
, GPIO_PINCFG88_NCESRC88_IOM4CE2 = 18
, GPIO_PINCFG88_NCESRC88_IOM4CE3 = 19
,
GPIO_PINCFG88_NCESRC88_IOM5CE0 = 20
, GPIO_PINCFG88_NCESRC88_IOM5CE1 = 21
, GPIO_PINCFG88_NCESRC88_IOM5CE2 = 22
, GPIO_PINCFG88_NCESRC88_IOM5CE3 = 23
,
GPIO_PINCFG88_NCESRC88_IOM6CE0 = 24
, GPIO_PINCFG88_NCESRC88_IOM6CE1 = 25
, GPIO_PINCFG88_NCESRC88_IOM6CE2 = 26
, GPIO_PINCFG88_NCESRC88_IOM6CE3 = 27
,
GPIO_PINCFG88_NCESRC88_IOM7CE0 = 28
, GPIO_PINCFG88_NCESRC88_IOM7CE1 = 29
, GPIO_PINCFG88_NCESRC88_IOM7CE2 = 30
, GPIO_PINCFG88_NCESRC88_IOM7CE3 = 31
,
GPIO_PINCFG88_NCESRC88_MSPI0CEN0 = 32
, GPIO_PINCFG88_NCESRC88_MSPI0CEN1 = 33
, GPIO_PINCFG88_NCESRC88_MSPI1CEN0 = 34
, GPIO_PINCFG88_NCESRC88_MSPI1CEN1 = 35
,
GPIO_PINCFG88_NCESRC88_MSPI2CEN0 = 36
, GPIO_PINCFG88_NCESRC88_MSPI2CEN1 = 37
, GPIO_PINCFG88_NCESRC88_DC_DPI_DE = 38
, GPIO_PINCFG88_NCESRC88_DISP_CONT_CSX = 39
,
GPIO_PINCFG88_NCESRC88_DC_SPI_CS_N = 40
, GPIO_PINCFG88_NCESRC88_DC_QSPI_CS_N = 41
, GPIO_PINCFG88_NCESRC88_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG88_PULLCFG88_Enum {
GPIO_PINCFG88_PULLCFG88_DIS = 0
, GPIO_PINCFG88_PULLCFG88_PD50K = 1
, GPIO_PINCFG88_PULLCFG88_PU15K = 2
, GPIO_PINCFG88_PULLCFG88_PU6K = 3
,
GPIO_PINCFG88_PULLCFG88_PU12K = 4
, GPIO_PINCFG88_PULLCFG88_PU24K = 5
, GPIO_PINCFG88_PULLCFG88_PU50K = 6
, GPIO_PINCFG88_PULLCFG88_PU100K = 7
} |
| |
| enum | GPIO_PINCFG88_DS88_Enum { GPIO_PINCFG88_DS88_0P1X = 0
, GPIO_PINCFG88_DS88_0P5X = 1
, GPIO_PINCFG88_DS88_0P75X = 2
, GPIO_PINCFG88_DS88_1P0X = 3
} |
| |
| enum | GPIO_PINCFG88_OUTCFG88_Enum { GPIO_PINCFG88_OUTCFG88_DIS = 0
, GPIO_PINCFG88_OUTCFG88_PUSHPULL = 1
, GPIO_PINCFG88_OUTCFG88_OD = 2
, GPIO_PINCFG88_OUTCFG88_TS = 3
} |
| |
| enum | GPIO_PINCFG88_IRPTEN88_Enum { GPIO_PINCFG88_IRPTEN88_DIS = 0
, GPIO_PINCFG88_IRPTEN88_INTFALL = 1
, GPIO_PINCFG88_IRPTEN88_INTRISE = 2
, GPIO_PINCFG88_IRPTEN88_INTANY = 3
} |
| |
| enum | GPIO_PINCFG88_FNCSEL88_Enum {
GPIO_PINCFG88_FNCSEL88_RESERVED0 = 0
, GPIO_PINCFG88_FNCSEL88_RESERVED1 = 1
, GPIO_PINCFG88_FNCSEL88_SDIF_CLKOUT = 2
, GPIO_PINCFG88_FNCSEL88_GPIO = 3
,
GPIO_PINCFG88_FNCSEL88_RESERVED4 = 4
, GPIO_PINCFG88_FNCSEL88_RESERVED5 = 5
, GPIO_PINCFG88_FNCSEL88_CT88 = 6
, GPIO_PINCFG88_FNCSEL88_NCE88 = 7
,
GPIO_PINCFG88_FNCSEL88_OBSBUS8 = 8
, GPIO_PINCFG88_FNCSEL88_RESERVED9 = 9
, GPIO_PINCFG88_FNCSEL88_RESERVED10 = 10
, GPIO_PINCFG88_FNCSEL88_FPIO = 11
,
GPIO_PINCFG88_FNCSEL88_RESERVED12 = 12
, GPIO_PINCFG88_FNCSEL88_RESERVED13 = 13
, GPIO_PINCFG88_FNCSEL88_RESERVED14 = 14
, GPIO_PINCFG88_FNCSEL88_RESERVED15 = 15
} |
| |
| enum | GPIO_PINCFG89_NCEPOL89_Enum { GPIO_PINCFG89_NCEPOL89_LOW = 0
, GPIO_PINCFG89_NCEPOL89_HIGH = 1
} |
| |
| enum | GPIO_PINCFG89_NCESRC89_Enum {
GPIO_PINCFG89_NCESRC89_IOM0CE0 = 0
, GPIO_PINCFG89_NCESRC89_IOM0CE1 = 1
, GPIO_PINCFG89_NCESRC89_IOM0CE2 = 2
, GPIO_PINCFG89_NCESRC89_IOM0CE3 = 3
,
GPIO_PINCFG89_NCESRC89_IOM1CE0 = 4
, GPIO_PINCFG89_NCESRC89_IOM1CE1 = 5
, GPIO_PINCFG89_NCESRC89_IOM1CE2 = 6
, GPIO_PINCFG89_NCESRC89_IOM1CE3 = 7
,
GPIO_PINCFG89_NCESRC89_IOM2CE0 = 8
, GPIO_PINCFG89_NCESRC89_IOM2CE1 = 9
, GPIO_PINCFG89_NCESRC89_IOM2CE2 = 10
, GPIO_PINCFG89_NCESRC89_IOM2CE3 = 11
,
GPIO_PINCFG89_NCESRC89_IOM3CE0 = 12
, GPIO_PINCFG89_NCESRC89_IOM3CE1 = 13
, GPIO_PINCFG89_NCESRC89_IOM3CE2 = 14
, GPIO_PINCFG89_NCESRC89_IOM3CE3 = 15
,
GPIO_PINCFG89_NCESRC89_IOM4CE0 = 16
, GPIO_PINCFG89_NCESRC89_IOM4CE1 = 17
, GPIO_PINCFG89_NCESRC89_IOM4CE2 = 18
, GPIO_PINCFG89_NCESRC89_IOM4CE3 = 19
,
GPIO_PINCFG89_NCESRC89_IOM5CE0 = 20
, GPIO_PINCFG89_NCESRC89_IOM5CE1 = 21
, GPIO_PINCFG89_NCESRC89_IOM5CE2 = 22
, GPIO_PINCFG89_NCESRC89_IOM5CE3 = 23
,
GPIO_PINCFG89_NCESRC89_IOM6CE0 = 24
, GPIO_PINCFG89_NCESRC89_IOM6CE1 = 25
, GPIO_PINCFG89_NCESRC89_IOM6CE2 = 26
, GPIO_PINCFG89_NCESRC89_IOM6CE3 = 27
,
GPIO_PINCFG89_NCESRC89_IOM7CE0 = 28
, GPIO_PINCFG89_NCESRC89_IOM7CE1 = 29
, GPIO_PINCFG89_NCESRC89_IOM7CE2 = 30
, GPIO_PINCFG89_NCESRC89_IOM7CE3 = 31
,
GPIO_PINCFG89_NCESRC89_MSPI0CEN0 = 32
, GPIO_PINCFG89_NCESRC89_MSPI0CEN1 = 33
, GPIO_PINCFG89_NCESRC89_MSPI1CEN0 = 34
, GPIO_PINCFG89_NCESRC89_MSPI1CEN1 = 35
,
GPIO_PINCFG89_NCESRC89_MSPI2CEN0 = 36
, GPIO_PINCFG89_NCESRC89_MSPI2CEN1 = 37
, GPIO_PINCFG89_NCESRC89_DC_DPI_DE = 38
, GPIO_PINCFG89_NCESRC89_DISP_CONT_CSX = 39
,
GPIO_PINCFG89_NCESRC89_DC_SPI_CS_N = 40
, GPIO_PINCFG89_NCESRC89_DC_QSPI_CS_N = 41
, GPIO_PINCFG89_NCESRC89_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG89_PULLCFG89_Enum {
GPIO_PINCFG89_PULLCFG89_DIS = 0
, GPIO_PINCFG89_PULLCFG89_PD50K = 1
, GPIO_PINCFG89_PULLCFG89_PU15K = 2
, GPIO_PINCFG89_PULLCFG89_PU6K = 3
,
GPIO_PINCFG89_PULLCFG89_PU12K = 4
, GPIO_PINCFG89_PULLCFG89_PU24K = 5
, GPIO_PINCFG89_PULLCFG89_PU50K = 6
, GPIO_PINCFG89_PULLCFG89_PU100K = 7
} |
| |
| enum | GPIO_PINCFG89_DS89_Enum { GPIO_PINCFG89_DS89_0P1X = 0
, GPIO_PINCFG89_DS89_0P5X = 1
} |
| |
| enum | GPIO_PINCFG89_OUTCFG89_Enum { GPIO_PINCFG89_OUTCFG89_DIS = 0
, GPIO_PINCFG89_OUTCFG89_PUSHPULL = 1
, GPIO_PINCFG89_OUTCFG89_OD = 2
, GPIO_PINCFG89_OUTCFG89_TS = 3
} |
| |
| enum | GPIO_PINCFG89_IRPTEN89_Enum { GPIO_PINCFG89_IRPTEN89_DIS = 0
, GPIO_PINCFG89_IRPTEN89_INTFALL = 1
, GPIO_PINCFG89_IRPTEN89_INTRISE = 2
, GPIO_PINCFG89_IRPTEN89_INTANY = 3
} |
| |
| enum | GPIO_PINCFG89_FNCSEL89_Enum {
GPIO_PINCFG89_FNCSEL89_RESERVED0 = 0
, GPIO_PINCFG89_FNCSEL89_RESERVED1 = 1
, GPIO_PINCFG89_FNCSEL89_RESERVED2 = 2
, GPIO_PINCFG89_FNCSEL89_GPIO = 3
,
GPIO_PINCFG89_FNCSEL89_RESERVED4 = 4
, GPIO_PINCFG89_FNCSEL89_DISP_CM = 5
, GPIO_PINCFG89_FNCSEL89_CT89 = 6
, GPIO_PINCFG89_FNCSEL89_NCE89 = 7
,
GPIO_PINCFG89_FNCSEL89_OBSBUS9 = 8
, GPIO_PINCFG89_FNCSEL89_RESERVED9 = 9
, GPIO_PINCFG89_FNCSEL89_RESERVED10 = 10
, GPIO_PINCFG89_FNCSEL89_FPIO = 11
,
GPIO_PINCFG89_FNCSEL89_RESERVED12 = 12
, GPIO_PINCFG89_FNCSEL89_RESERVED13 = 13
, GPIO_PINCFG89_FNCSEL89_RESERVED14 = 14
, GPIO_PINCFG89_FNCSEL89_RESERVED15 = 15
} |
| |
| enum | GPIO_PINCFG90_NCEPOL90_Enum { GPIO_PINCFG90_NCEPOL90_LOW = 0
, GPIO_PINCFG90_NCEPOL90_HIGH = 1
} |
| |
| enum | GPIO_PINCFG90_NCESRC90_Enum {
GPIO_PINCFG90_NCESRC90_IOM0CE0 = 0
, GPIO_PINCFG90_NCESRC90_IOM0CE1 = 1
, GPIO_PINCFG90_NCESRC90_IOM0CE2 = 2
, GPIO_PINCFG90_NCESRC90_IOM0CE3 = 3
,
GPIO_PINCFG90_NCESRC90_IOM1CE0 = 4
, GPIO_PINCFG90_NCESRC90_IOM1CE1 = 5
, GPIO_PINCFG90_NCESRC90_IOM1CE2 = 6
, GPIO_PINCFG90_NCESRC90_IOM1CE3 = 7
,
GPIO_PINCFG90_NCESRC90_IOM2CE0 = 8
, GPIO_PINCFG90_NCESRC90_IOM2CE1 = 9
, GPIO_PINCFG90_NCESRC90_IOM2CE2 = 10
, GPIO_PINCFG90_NCESRC90_IOM2CE3 = 11
,
GPIO_PINCFG90_NCESRC90_IOM3CE0 = 12
, GPIO_PINCFG90_NCESRC90_IOM3CE1 = 13
, GPIO_PINCFG90_NCESRC90_IOM3CE2 = 14
, GPIO_PINCFG90_NCESRC90_IOM3CE3 = 15
,
GPIO_PINCFG90_NCESRC90_IOM4CE0 = 16
, GPIO_PINCFG90_NCESRC90_IOM4CE1 = 17
, GPIO_PINCFG90_NCESRC90_IOM4CE2 = 18
, GPIO_PINCFG90_NCESRC90_IOM4CE3 = 19
,
GPIO_PINCFG90_NCESRC90_IOM5CE0 = 20
, GPIO_PINCFG90_NCESRC90_IOM5CE1 = 21
, GPIO_PINCFG90_NCESRC90_IOM5CE2 = 22
, GPIO_PINCFG90_NCESRC90_IOM5CE3 = 23
,
GPIO_PINCFG90_NCESRC90_IOM6CE0 = 24
, GPIO_PINCFG90_NCESRC90_IOM6CE1 = 25
, GPIO_PINCFG90_NCESRC90_IOM6CE2 = 26
, GPIO_PINCFG90_NCESRC90_IOM6CE3 = 27
,
GPIO_PINCFG90_NCESRC90_IOM7CE0 = 28
, GPIO_PINCFG90_NCESRC90_IOM7CE1 = 29
, GPIO_PINCFG90_NCESRC90_IOM7CE2 = 30
, GPIO_PINCFG90_NCESRC90_IOM7CE3 = 31
,
GPIO_PINCFG90_NCESRC90_MSPI0CEN0 = 32
, GPIO_PINCFG90_NCESRC90_MSPI0CEN1 = 33
, GPIO_PINCFG90_NCESRC90_MSPI1CEN0 = 34
, GPIO_PINCFG90_NCESRC90_MSPI1CEN1 = 35
,
GPIO_PINCFG90_NCESRC90_MSPI2CEN0 = 36
, GPIO_PINCFG90_NCESRC90_MSPI2CEN1 = 37
, GPIO_PINCFG90_NCESRC90_DC_DPI_DE = 38
, GPIO_PINCFG90_NCESRC90_DISP_CONT_CSX = 39
,
GPIO_PINCFG90_NCESRC90_DC_SPI_CS_N = 40
, GPIO_PINCFG90_NCESRC90_DC_QSPI_CS_N = 41
, GPIO_PINCFG90_NCESRC90_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG90_PULLCFG90_Enum {
GPIO_PINCFG90_PULLCFG90_DIS = 0
, GPIO_PINCFG90_PULLCFG90_PD50K = 1
, GPIO_PINCFG90_PULLCFG90_PU15K = 2
, GPIO_PINCFG90_PULLCFG90_PU6K = 3
,
GPIO_PINCFG90_PULLCFG90_PU12K = 4
, GPIO_PINCFG90_PULLCFG90_PU24K = 5
, GPIO_PINCFG90_PULLCFG90_PU50K = 6
, GPIO_PINCFG90_PULLCFG90_PU100K = 7
} |
| |
| enum | GPIO_PINCFG90_DS90_Enum { GPIO_PINCFG90_DS90_0P1X = 0
, GPIO_PINCFG90_DS90_0P5X = 1
} |
| |
| enum | GPIO_PINCFG90_OUTCFG90_Enum { GPIO_PINCFG90_OUTCFG90_DIS = 0
, GPIO_PINCFG90_OUTCFG90_PUSHPULL = 1
, GPIO_PINCFG90_OUTCFG90_OD = 2
, GPIO_PINCFG90_OUTCFG90_TS = 3
} |
| |
| enum | GPIO_PINCFG90_IRPTEN90_Enum { GPIO_PINCFG90_IRPTEN90_DIS = 0
, GPIO_PINCFG90_IRPTEN90_INTFALL = 1
, GPIO_PINCFG90_IRPTEN90_INTRISE = 2
, GPIO_PINCFG90_IRPTEN90_INTANY = 3
} |
| |
| enum | GPIO_PINCFG90_FNCSEL90_Enum {
GPIO_PINCFG90_FNCSEL90_RESERVED0 = 0
, GPIO_PINCFG90_FNCSEL90_RESERVED1 = 1
, GPIO_PINCFG90_FNCSEL90_RESERVED2 = 2
, GPIO_PINCFG90_FNCSEL90_GPIO = 3
,
GPIO_PINCFG90_FNCSEL90_RESERVED4 = 4
, GPIO_PINCFG90_FNCSEL90_RESERVED5 = 5
, GPIO_PINCFG90_FNCSEL90_CT90 = 6
, GPIO_PINCFG90_FNCSEL90_NCE90 = 7
,
GPIO_PINCFG90_FNCSEL90_OBSBUS10 = 8
, GPIO_PINCFG90_FNCSEL90_VCMPO = 9
, GPIO_PINCFG90_FNCSEL90_RESERVED10 = 10
, GPIO_PINCFG90_FNCSEL90_FPIO = 11
,
GPIO_PINCFG90_FNCSEL90_RESERVED12 = 12
, GPIO_PINCFG90_FNCSEL90_RESERVED13 = 13
, GPIO_PINCFG90_FNCSEL90_RESERVED14 = 14
, GPIO_PINCFG90_FNCSEL90_RESERVED15 = 15
} |
| |
| enum | GPIO_PINCFG91_NCEPOL91_Enum { GPIO_PINCFG91_NCEPOL91_LOW = 0
, GPIO_PINCFG91_NCEPOL91_HIGH = 1
} |
| |
| enum | GPIO_PINCFG91_NCESRC91_Enum {
GPIO_PINCFG91_NCESRC91_IOM0CE0 = 0
, GPIO_PINCFG91_NCESRC91_IOM0CE1 = 1
, GPIO_PINCFG91_NCESRC91_IOM0CE2 = 2
, GPIO_PINCFG91_NCESRC91_IOM0CE3 = 3
,
GPIO_PINCFG91_NCESRC91_IOM1CE0 = 4
, GPIO_PINCFG91_NCESRC91_IOM1CE1 = 5
, GPIO_PINCFG91_NCESRC91_IOM1CE2 = 6
, GPIO_PINCFG91_NCESRC91_IOM1CE3 = 7
,
GPIO_PINCFG91_NCESRC91_IOM2CE0 = 8
, GPIO_PINCFG91_NCESRC91_IOM2CE1 = 9
, GPIO_PINCFG91_NCESRC91_IOM2CE2 = 10
, GPIO_PINCFG91_NCESRC91_IOM2CE3 = 11
,
GPIO_PINCFG91_NCESRC91_IOM3CE0 = 12
, GPIO_PINCFG91_NCESRC91_IOM3CE1 = 13
, GPIO_PINCFG91_NCESRC91_IOM3CE2 = 14
, GPIO_PINCFG91_NCESRC91_IOM3CE3 = 15
,
GPIO_PINCFG91_NCESRC91_IOM4CE0 = 16
, GPIO_PINCFG91_NCESRC91_IOM4CE1 = 17
, GPIO_PINCFG91_NCESRC91_IOM4CE2 = 18
, GPIO_PINCFG91_NCESRC91_IOM4CE3 = 19
,
GPIO_PINCFG91_NCESRC91_IOM5CE0 = 20
, GPIO_PINCFG91_NCESRC91_IOM5CE1 = 21
, GPIO_PINCFG91_NCESRC91_IOM5CE2 = 22
, GPIO_PINCFG91_NCESRC91_IOM5CE3 = 23
,
GPIO_PINCFG91_NCESRC91_IOM6CE0 = 24
, GPIO_PINCFG91_NCESRC91_IOM6CE1 = 25
, GPIO_PINCFG91_NCESRC91_IOM6CE2 = 26
, GPIO_PINCFG91_NCESRC91_IOM6CE3 = 27
,
GPIO_PINCFG91_NCESRC91_IOM7CE0 = 28
, GPIO_PINCFG91_NCESRC91_IOM7CE1 = 29
, GPIO_PINCFG91_NCESRC91_IOM7CE2 = 30
, GPIO_PINCFG91_NCESRC91_IOM7CE3 = 31
,
GPIO_PINCFG91_NCESRC91_MSPI0CEN0 = 32
, GPIO_PINCFG91_NCESRC91_MSPI0CEN1 = 33
, GPIO_PINCFG91_NCESRC91_MSPI1CEN0 = 34
, GPIO_PINCFG91_NCESRC91_MSPI1CEN1 = 35
,
GPIO_PINCFG91_NCESRC91_MSPI2CEN0 = 36
, GPIO_PINCFG91_NCESRC91_MSPI2CEN1 = 37
, GPIO_PINCFG91_NCESRC91_DC_DPI_DE = 38
, GPIO_PINCFG91_NCESRC91_DISP_CONT_CSX = 39
,
GPIO_PINCFG91_NCESRC91_DC_SPI_CS_N = 40
, GPIO_PINCFG91_NCESRC91_DC_QSPI_CS_N = 41
, GPIO_PINCFG91_NCESRC91_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG91_PULLCFG91_Enum {
GPIO_PINCFG91_PULLCFG91_DIS = 0
, GPIO_PINCFG91_PULLCFG91_PD50K = 1
, GPIO_PINCFG91_PULLCFG91_PU15K = 2
, GPIO_PINCFG91_PULLCFG91_PU6K = 3
,
GPIO_PINCFG91_PULLCFG91_PU12K = 4
, GPIO_PINCFG91_PULLCFG91_PU24K = 5
, GPIO_PINCFG91_PULLCFG91_PU50K = 6
, GPIO_PINCFG91_PULLCFG91_PU100K = 7
} |
| |
| enum | GPIO_PINCFG91_DS91_Enum { GPIO_PINCFG91_DS91_0P1X = 0
, GPIO_PINCFG91_DS91_0P5X = 1
} |
| |
| enum | GPIO_PINCFG91_OUTCFG91_Enum { GPIO_PINCFG91_OUTCFG91_DIS = 0
, GPIO_PINCFG91_OUTCFG91_PUSHPULL = 1
, GPIO_PINCFG91_OUTCFG91_OD = 2
, GPIO_PINCFG91_OUTCFG91_TS = 3
} |
| |
| enum | GPIO_PINCFG91_IRPTEN91_Enum { GPIO_PINCFG91_IRPTEN91_DIS = 0
, GPIO_PINCFG91_IRPTEN91_INTFALL = 1
, GPIO_PINCFG91_IRPTEN91_INTRISE = 2
, GPIO_PINCFG91_IRPTEN91_INTANY = 3
} |
| |
| enum | GPIO_PINCFG91_FNCSEL91_Enum {
GPIO_PINCFG91_FNCSEL91_RESERVED0 = 0
, GPIO_PINCFG91_FNCSEL91_RESERVED1 = 1
, GPIO_PINCFG91_FNCSEL91_RESERVED2 = 2
, GPIO_PINCFG91_FNCSEL91_GPIO = 3
,
GPIO_PINCFG91_FNCSEL91_RESERVED4 = 4
, GPIO_PINCFG91_FNCSEL91_RESERVED5 = 5
, GPIO_PINCFG91_FNCSEL91_CT91 = 6
, GPIO_PINCFG91_FNCSEL91_NCE91 = 7
,
GPIO_PINCFG91_FNCSEL91_OBSBUS11 = 8
, GPIO_PINCFG91_FNCSEL91_VCMPO = 9
, GPIO_PINCFG91_FNCSEL91_RESERVED10 = 10
, GPIO_PINCFG91_FNCSEL91_FPIO = 11
,
GPIO_PINCFG91_FNCSEL91_RESERVED12 = 12
, GPIO_PINCFG91_FNCSEL91_RESERVED13 = 13
, GPIO_PINCFG91_FNCSEL91_RESERVED14 = 14
, GPIO_PINCFG91_FNCSEL91_RESERVED15 = 15
} |
| |
| enum | GPIO_PINCFG92_NCEPOL92_Enum { GPIO_PINCFG92_NCEPOL92_LOW = 0
, GPIO_PINCFG92_NCEPOL92_HIGH = 1
} |
| |
| enum | GPIO_PINCFG92_NCESRC92_Enum {
GPIO_PINCFG92_NCESRC92_IOM0CE0 = 0
, GPIO_PINCFG92_NCESRC92_IOM0CE1 = 1
, GPIO_PINCFG92_NCESRC92_IOM0CE2 = 2
, GPIO_PINCFG92_NCESRC92_IOM0CE3 = 3
,
GPIO_PINCFG92_NCESRC92_IOM1CE0 = 4
, GPIO_PINCFG92_NCESRC92_IOM1CE1 = 5
, GPIO_PINCFG92_NCESRC92_IOM1CE2 = 6
, GPIO_PINCFG92_NCESRC92_IOM1CE3 = 7
,
GPIO_PINCFG92_NCESRC92_IOM2CE0 = 8
, GPIO_PINCFG92_NCESRC92_IOM2CE1 = 9
, GPIO_PINCFG92_NCESRC92_IOM2CE2 = 10
, GPIO_PINCFG92_NCESRC92_IOM2CE3 = 11
,
GPIO_PINCFG92_NCESRC92_IOM3CE0 = 12
, GPIO_PINCFG92_NCESRC92_IOM3CE1 = 13
, GPIO_PINCFG92_NCESRC92_IOM3CE2 = 14
, GPIO_PINCFG92_NCESRC92_IOM3CE3 = 15
,
GPIO_PINCFG92_NCESRC92_IOM4CE0 = 16
, GPIO_PINCFG92_NCESRC92_IOM4CE1 = 17
, GPIO_PINCFG92_NCESRC92_IOM4CE2 = 18
, GPIO_PINCFG92_NCESRC92_IOM4CE3 = 19
,
GPIO_PINCFG92_NCESRC92_IOM5CE0 = 20
, GPIO_PINCFG92_NCESRC92_IOM5CE1 = 21
, GPIO_PINCFG92_NCESRC92_IOM5CE2 = 22
, GPIO_PINCFG92_NCESRC92_IOM5CE3 = 23
,
GPIO_PINCFG92_NCESRC92_IOM6CE0 = 24
, GPIO_PINCFG92_NCESRC92_IOM6CE1 = 25
, GPIO_PINCFG92_NCESRC92_IOM6CE2 = 26
, GPIO_PINCFG92_NCESRC92_IOM6CE3 = 27
,
GPIO_PINCFG92_NCESRC92_IOM7CE0 = 28
, GPIO_PINCFG92_NCESRC92_IOM7CE1 = 29
, GPIO_PINCFG92_NCESRC92_IOM7CE2 = 30
, GPIO_PINCFG92_NCESRC92_IOM7CE3 = 31
,
GPIO_PINCFG92_NCESRC92_MSPI0CEN0 = 32
, GPIO_PINCFG92_NCESRC92_MSPI0CEN1 = 33
, GPIO_PINCFG92_NCESRC92_MSPI1CEN0 = 34
, GPIO_PINCFG92_NCESRC92_MSPI1CEN1 = 35
,
GPIO_PINCFG92_NCESRC92_MSPI2CEN0 = 36
, GPIO_PINCFG92_NCESRC92_MSPI2CEN1 = 37
, GPIO_PINCFG92_NCESRC92_DC_DPI_DE = 38
, GPIO_PINCFG92_NCESRC92_DISP_CONT_CSX = 39
,
GPIO_PINCFG92_NCESRC92_DC_SPI_CS_N = 40
, GPIO_PINCFG92_NCESRC92_DC_QSPI_CS_N = 41
, GPIO_PINCFG92_NCESRC92_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG92_PULLCFG92_Enum {
GPIO_PINCFG92_PULLCFG92_DIS = 0
, GPIO_PINCFG92_PULLCFG92_PD50K = 1
, GPIO_PINCFG92_PULLCFG92_PU15K = 2
, GPIO_PINCFG92_PULLCFG92_PU6K = 3
,
GPIO_PINCFG92_PULLCFG92_PU12K = 4
, GPIO_PINCFG92_PULLCFG92_PU24K = 5
, GPIO_PINCFG92_PULLCFG92_PU50K = 6
, GPIO_PINCFG92_PULLCFG92_PU100K = 7
} |
| |
| enum | GPIO_PINCFG92_DS92_Enum { GPIO_PINCFG92_DS92_0P1X = 0
, GPIO_PINCFG92_DS92_0P5X = 1
} |
| |
| enum | GPIO_PINCFG92_OUTCFG92_Enum { GPIO_PINCFG92_OUTCFG92_DIS = 0
, GPIO_PINCFG92_OUTCFG92_PUSHPULL = 1
, GPIO_PINCFG92_OUTCFG92_OD = 2
, GPIO_PINCFG92_OUTCFG92_TS = 3
} |
| |
| enum | GPIO_PINCFG92_IRPTEN92_Enum { GPIO_PINCFG92_IRPTEN92_DIS = 0
, GPIO_PINCFG92_IRPTEN92_INTFALL = 1
, GPIO_PINCFG92_IRPTEN92_INTRISE = 2
, GPIO_PINCFG92_IRPTEN92_INTANY = 3
} |
| |
| enum | GPIO_PINCFG92_FNCSEL92_Enum {
GPIO_PINCFG92_FNCSEL92_RESERVED0 = 0
, GPIO_PINCFG92_FNCSEL92_RESERVED1 = 1
, GPIO_PINCFG92_FNCSEL92_RESERVED2 = 2
, GPIO_PINCFG92_FNCSEL92_GPIO = 3
,
GPIO_PINCFG92_FNCSEL92_RESERVED4 = 4
, GPIO_PINCFG92_FNCSEL92_RESERVED5 = 5
, GPIO_PINCFG92_FNCSEL92_CT92 = 6
, GPIO_PINCFG92_FNCSEL92_NCE92 = 7
,
GPIO_PINCFG92_FNCSEL92_OBSBUS12 = 8
, GPIO_PINCFG92_FNCSEL92_VCMPO = 9
, GPIO_PINCFG92_FNCSEL92_RESERVED10 = 10
, GPIO_PINCFG92_FNCSEL92_FPIO = 11
,
GPIO_PINCFG92_FNCSEL92_RESERVED12 = 12
, GPIO_PINCFG92_FNCSEL92_RESERVED13 = 13
, GPIO_PINCFG92_FNCSEL92_RESERVED14 = 14
, GPIO_PINCFG92_FNCSEL92_RESERVED15 = 15
} |
| |
| enum | GPIO_PINCFG93_NCEPOL93_Enum { GPIO_PINCFG93_NCEPOL93_LOW = 0
, GPIO_PINCFG93_NCEPOL93_HIGH = 1
} |
| |
| enum | GPIO_PINCFG93_NCESRC93_Enum {
GPIO_PINCFG93_NCESRC93_IOM0CE0 = 0
, GPIO_PINCFG93_NCESRC93_IOM0CE1 = 1
, GPIO_PINCFG93_NCESRC93_IOM0CE2 = 2
, GPIO_PINCFG93_NCESRC93_IOM0CE3 = 3
,
GPIO_PINCFG93_NCESRC93_IOM1CE0 = 4
, GPIO_PINCFG93_NCESRC93_IOM1CE1 = 5
, GPIO_PINCFG93_NCESRC93_IOM1CE2 = 6
, GPIO_PINCFG93_NCESRC93_IOM1CE3 = 7
,
GPIO_PINCFG93_NCESRC93_IOM2CE0 = 8
, GPIO_PINCFG93_NCESRC93_IOM2CE1 = 9
, GPIO_PINCFG93_NCESRC93_IOM2CE2 = 10
, GPIO_PINCFG93_NCESRC93_IOM2CE3 = 11
,
GPIO_PINCFG93_NCESRC93_IOM3CE0 = 12
, GPIO_PINCFG93_NCESRC93_IOM3CE1 = 13
, GPIO_PINCFG93_NCESRC93_IOM3CE2 = 14
, GPIO_PINCFG93_NCESRC93_IOM3CE3 = 15
,
GPIO_PINCFG93_NCESRC93_IOM4CE0 = 16
, GPIO_PINCFG93_NCESRC93_IOM4CE1 = 17
, GPIO_PINCFG93_NCESRC93_IOM4CE2 = 18
, GPIO_PINCFG93_NCESRC93_IOM4CE3 = 19
,
GPIO_PINCFG93_NCESRC93_IOM5CE0 = 20
, GPIO_PINCFG93_NCESRC93_IOM5CE1 = 21
, GPIO_PINCFG93_NCESRC93_IOM5CE2 = 22
, GPIO_PINCFG93_NCESRC93_IOM5CE3 = 23
,
GPIO_PINCFG93_NCESRC93_IOM6CE0 = 24
, GPIO_PINCFG93_NCESRC93_IOM6CE1 = 25
, GPIO_PINCFG93_NCESRC93_IOM6CE2 = 26
, GPIO_PINCFG93_NCESRC93_IOM6CE3 = 27
,
GPIO_PINCFG93_NCESRC93_IOM7CE0 = 28
, GPIO_PINCFG93_NCESRC93_IOM7CE1 = 29
, GPIO_PINCFG93_NCESRC93_IOM7CE2 = 30
, GPIO_PINCFG93_NCESRC93_IOM7CE3 = 31
,
GPIO_PINCFG93_NCESRC93_MSPI0CEN0 = 32
, GPIO_PINCFG93_NCESRC93_MSPI0CEN1 = 33
, GPIO_PINCFG93_NCESRC93_MSPI1CEN0 = 34
, GPIO_PINCFG93_NCESRC93_MSPI1CEN1 = 35
,
GPIO_PINCFG93_NCESRC93_MSPI2CEN0 = 36
, GPIO_PINCFG93_NCESRC93_MSPI2CEN1 = 37
, GPIO_PINCFG93_NCESRC93_DC_DPI_DE = 38
, GPIO_PINCFG93_NCESRC93_DISP_CONT_CSX = 39
,
GPIO_PINCFG93_NCESRC93_DC_SPI_CS_N = 40
, GPIO_PINCFG93_NCESRC93_DC_QSPI_CS_N = 41
, GPIO_PINCFG93_NCESRC93_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG93_PULLCFG93_Enum {
GPIO_PINCFG93_PULLCFG93_DIS = 0
, GPIO_PINCFG93_PULLCFG93_PD50K = 1
, GPIO_PINCFG93_PULLCFG93_PU15K = 2
, GPIO_PINCFG93_PULLCFG93_PU6K = 3
,
GPIO_PINCFG93_PULLCFG93_PU12K = 4
, GPIO_PINCFG93_PULLCFG93_PU24K = 5
, GPIO_PINCFG93_PULLCFG93_PU50K = 6
, GPIO_PINCFG93_PULLCFG93_PU100K = 7
} |
| |
| enum | GPIO_PINCFG93_DS93_Enum { GPIO_PINCFG93_DS93_0P1X = 0
, GPIO_PINCFG93_DS93_0P5X = 1
} |
| |
| enum | GPIO_PINCFG93_OUTCFG93_Enum { GPIO_PINCFG93_OUTCFG93_DIS = 0
, GPIO_PINCFG93_OUTCFG93_PUSHPULL = 1
, GPIO_PINCFG93_OUTCFG93_OD = 2
, GPIO_PINCFG93_OUTCFG93_TS = 3
} |
| |
| enum | GPIO_PINCFG93_IRPTEN93_Enum { GPIO_PINCFG93_IRPTEN93_DIS = 0
, GPIO_PINCFG93_IRPTEN93_INTFALL = 1
, GPIO_PINCFG93_IRPTEN93_INTRISE = 2
, GPIO_PINCFG93_IRPTEN93_INTANY = 3
} |
| |
| enum | GPIO_PINCFG93_FNCSEL93_Enum {
GPIO_PINCFG93_FNCSEL93_MSPI2_9 = 0
, GPIO_PINCFG93_FNCSEL93_RESERVED1 = 1
, GPIO_PINCFG93_FNCSEL93_RESERVED2 = 2
, GPIO_PINCFG93_FNCSEL93_GPIO = 3
,
GPIO_PINCFG93_FNCSEL93_RESERVED4 = 4
, GPIO_PINCFG93_FNCSEL93_RESERVED5 = 5
, GPIO_PINCFG93_FNCSEL93_CT93 = 6
, GPIO_PINCFG93_FNCSEL93_NCE93 = 7
,
GPIO_PINCFG93_FNCSEL93_OBSBUS13 = 8
, GPIO_PINCFG93_FNCSEL93_VCMPO = 9
, GPIO_PINCFG93_FNCSEL93_RESERVED10 = 10
, GPIO_PINCFG93_FNCSEL93_FPIO = 11
,
GPIO_PINCFG93_FNCSEL93_RESERVED12 = 12
, GPIO_PINCFG93_FNCSEL93_RESERVED13 = 13
, GPIO_PINCFG93_FNCSEL93_RESERVED14 = 14
, GPIO_PINCFG93_FNCSEL93_RESERVED15 = 15
} |
| |
| enum | GPIO_PINCFG94_NCEPOL94_Enum { GPIO_PINCFG94_NCEPOL94_LOW = 0
, GPIO_PINCFG94_NCEPOL94_HIGH = 1
} |
| |
| enum | GPIO_PINCFG94_NCESRC94_Enum {
GPIO_PINCFG94_NCESRC94_IOM0CE0 = 0
, GPIO_PINCFG94_NCESRC94_IOM0CE1 = 1
, GPIO_PINCFG94_NCESRC94_IOM0CE2 = 2
, GPIO_PINCFG94_NCESRC94_IOM0CE3 = 3
,
GPIO_PINCFG94_NCESRC94_IOM1CE0 = 4
, GPIO_PINCFG94_NCESRC94_IOM1CE1 = 5
, GPIO_PINCFG94_NCESRC94_IOM1CE2 = 6
, GPIO_PINCFG94_NCESRC94_IOM1CE3 = 7
,
GPIO_PINCFG94_NCESRC94_IOM2CE0 = 8
, GPIO_PINCFG94_NCESRC94_IOM2CE1 = 9
, GPIO_PINCFG94_NCESRC94_IOM2CE2 = 10
, GPIO_PINCFG94_NCESRC94_IOM2CE3 = 11
,
GPIO_PINCFG94_NCESRC94_IOM3CE0 = 12
, GPIO_PINCFG94_NCESRC94_IOM3CE1 = 13
, GPIO_PINCFG94_NCESRC94_IOM3CE2 = 14
, GPIO_PINCFG94_NCESRC94_IOM3CE3 = 15
,
GPIO_PINCFG94_NCESRC94_IOM4CE0 = 16
, GPIO_PINCFG94_NCESRC94_IOM4CE1 = 17
, GPIO_PINCFG94_NCESRC94_IOM4CE2 = 18
, GPIO_PINCFG94_NCESRC94_IOM4CE3 = 19
,
GPIO_PINCFG94_NCESRC94_IOM5CE0 = 20
, GPIO_PINCFG94_NCESRC94_IOM5CE1 = 21
, GPIO_PINCFG94_NCESRC94_IOM5CE2 = 22
, GPIO_PINCFG94_NCESRC94_IOM5CE3 = 23
,
GPIO_PINCFG94_NCESRC94_IOM6CE0 = 24
, GPIO_PINCFG94_NCESRC94_IOM6CE1 = 25
, GPIO_PINCFG94_NCESRC94_IOM6CE2 = 26
, GPIO_PINCFG94_NCESRC94_IOM6CE3 = 27
,
GPIO_PINCFG94_NCESRC94_IOM7CE0 = 28
, GPIO_PINCFG94_NCESRC94_IOM7CE1 = 29
, GPIO_PINCFG94_NCESRC94_IOM7CE2 = 30
, GPIO_PINCFG94_NCESRC94_IOM7CE3 = 31
,
GPIO_PINCFG94_NCESRC94_MSPI0CEN0 = 32
, GPIO_PINCFG94_NCESRC94_MSPI0CEN1 = 33
, GPIO_PINCFG94_NCESRC94_MSPI1CEN0 = 34
, GPIO_PINCFG94_NCESRC94_MSPI1CEN1 = 35
,
GPIO_PINCFG94_NCESRC94_MSPI2CEN0 = 36
, GPIO_PINCFG94_NCESRC94_MSPI2CEN1 = 37
, GPIO_PINCFG94_NCESRC94_DC_DPI_DE = 38
, GPIO_PINCFG94_NCESRC94_DISP_CONT_CSX = 39
,
GPIO_PINCFG94_NCESRC94_DC_SPI_CS_N = 40
, GPIO_PINCFG94_NCESRC94_DC_QSPI_CS_N = 41
, GPIO_PINCFG94_NCESRC94_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG94_PULLCFG94_Enum {
GPIO_PINCFG94_PULLCFG94_DIS = 0
, GPIO_PINCFG94_PULLCFG94_PD50K = 1
, GPIO_PINCFG94_PULLCFG94_PU15K = 2
, GPIO_PINCFG94_PULLCFG94_PU6K = 3
,
GPIO_PINCFG94_PULLCFG94_PU12K = 4
, GPIO_PINCFG94_PULLCFG94_PU24K = 5
, GPIO_PINCFG94_PULLCFG94_PU50K = 6
, GPIO_PINCFG94_PULLCFG94_PU100K = 7
} |
| |
| enum | GPIO_PINCFG94_DS94_Enum { GPIO_PINCFG94_DS94_0P1X = 0
, GPIO_PINCFG94_DS94_0P5X = 1
} |
| |
| enum | GPIO_PINCFG94_OUTCFG94_Enum { GPIO_PINCFG94_OUTCFG94_DIS = 0
, GPIO_PINCFG94_OUTCFG94_PUSHPULL = 1
, GPIO_PINCFG94_OUTCFG94_OD = 2
, GPIO_PINCFG94_OUTCFG94_TS = 3
} |
| |
| enum | GPIO_PINCFG94_IRPTEN94_Enum { GPIO_PINCFG94_IRPTEN94_DIS = 0
, GPIO_PINCFG94_IRPTEN94_INTFALL = 1
, GPIO_PINCFG94_IRPTEN94_INTRISE = 2
, GPIO_PINCFG94_IRPTEN94_INTANY = 3
} |
| |
| enum | GPIO_PINCFG94_FNCSEL94_Enum {
GPIO_PINCFG94_FNCSEL94_RESERVED0 = 0
, GPIO_PINCFG94_FNCSEL94_RESERVED1 = 1
, GPIO_PINCFG94_FNCSEL94_RESERVED2 = 2
, GPIO_PINCFG94_FNCSEL94_GPIO = 3
,
GPIO_PINCFG94_FNCSEL94_RESERVED4 = 4
, GPIO_PINCFG94_FNCSEL94_RESERVED5 = 5
, GPIO_PINCFG94_FNCSEL94_CT94 = 6
, GPIO_PINCFG94_FNCSEL94_NCE94 = 7
,
GPIO_PINCFG94_FNCSEL94_OBSBUS14 = 8
, GPIO_PINCFG94_FNCSEL94_VCMPO = 9
, GPIO_PINCFG94_FNCSEL94_RESERVED10 = 10
, GPIO_PINCFG94_FNCSEL94_FPIO = 11
,
GPIO_PINCFG94_FNCSEL94_RESERVED12 = 12
, GPIO_PINCFG94_FNCSEL94_RESERVED13 = 13
, GPIO_PINCFG94_FNCSEL94_RESERVED14 = 14
, GPIO_PINCFG94_FNCSEL94_RESERVED15 = 15
} |
| |
| enum | GPIO_PINCFG95_NCEPOL95_Enum { GPIO_PINCFG95_NCEPOL95_LOW = 0
, GPIO_PINCFG95_NCEPOL95_HIGH = 1
} |
| |
| enum | GPIO_PINCFG95_NCESRC95_Enum {
GPIO_PINCFG95_NCESRC95_IOM0CE0 = 0
, GPIO_PINCFG95_NCESRC95_IOM0CE1 = 1
, GPIO_PINCFG95_NCESRC95_IOM0CE2 = 2
, GPIO_PINCFG95_NCESRC95_IOM0CE3 = 3
,
GPIO_PINCFG95_NCESRC95_IOM1CE0 = 4
, GPIO_PINCFG95_NCESRC95_IOM1CE1 = 5
, GPIO_PINCFG95_NCESRC95_IOM1CE2 = 6
, GPIO_PINCFG95_NCESRC95_IOM1CE3 = 7
,
GPIO_PINCFG95_NCESRC95_IOM2CE0 = 8
, GPIO_PINCFG95_NCESRC95_IOM2CE1 = 9
, GPIO_PINCFG95_NCESRC95_IOM2CE2 = 10
, GPIO_PINCFG95_NCESRC95_IOM2CE3 = 11
,
GPIO_PINCFG95_NCESRC95_IOM3CE0 = 12
, GPIO_PINCFG95_NCESRC95_IOM3CE1 = 13
, GPIO_PINCFG95_NCESRC95_IOM3CE2 = 14
, GPIO_PINCFG95_NCESRC95_IOM3CE3 = 15
,
GPIO_PINCFG95_NCESRC95_IOM4CE0 = 16
, GPIO_PINCFG95_NCESRC95_IOM4CE1 = 17
, GPIO_PINCFG95_NCESRC95_IOM4CE2 = 18
, GPIO_PINCFG95_NCESRC95_IOM4CE3 = 19
,
GPIO_PINCFG95_NCESRC95_IOM5CE0 = 20
, GPIO_PINCFG95_NCESRC95_IOM5CE1 = 21
, GPIO_PINCFG95_NCESRC95_IOM5CE2 = 22
, GPIO_PINCFG95_NCESRC95_IOM5CE3 = 23
,
GPIO_PINCFG95_NCESRC95_IOM6CE0 = 24
, GPIO_PINCFG95_NCESRC95_IOM6CE1 = 25
, GPIO_PINCFG95_NCESRC95_IOM6CE2 = 26
, GPIO_PINCFG95_NCESRC95_IOM6CE3 = 27
,
GPIO_PINCFG95_NCESRC95_IOM7CE0 = 28
, GPIO_PINCFG95_NCESRC95_IOM7CE1 = 29
, GPIO_PINCFG95_NCESRC95_IOM7CE2 = 30
, GPIO_PINCFG95_NCESRC95_IOM7CE3 = 31
,
GPIO_PINCFG95_NCESRC95_MSPI0CEN0 = 32
, GPIO_PINCFG95_NCESRC95_MSPI0CEN1 = 33
, GPIO_PINCFG95_NCESRC95_MSPI1CEN0 = 34
, GPIO_PINCFG95_NCESRC95_MSPI1CEN1 = 35
,
GPIO_PINCFG95_NCESRC95_MSPI2CEN0 = 36
, GPIO_PINCFG95_NCESRC95_MSPI2CEN1 = 37
, GPIO_PINCFG95_NCESRC95_DC_DPI_DE = 38
, GPIO_PINCFG95_NCESRC95_DISP_CONT_CSX = 39
,
GPIO_PINCFG95_NCESRC95_DC_SPI_CS_N = 40
, GPIO_PINCFG95_NCESRC95_DC_QSPI_CS_N = 41
, GPIO_PINCFG95_NCESRC95_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG95_PULLCFG95_Enum {
GPIO_PINCFG95_PULLCFG95_DIS = 0
, GPIO_PINCFG95_PULLCFG95_PD50K = 1
, GPIO_PINCFG95_PULLCFG95_PU15K = 2
, GPIO_PINCFG95_PULLCFG95_PU6K = 3
,
GPIO_PINCFG95_PULLCFG95_PU12K = 4
, GPIO_PINCFG95_PULLCFG95_PU24K = 5
, GPIO_PINCFG95_PULLCFG95_PU50K = 6
, GPIO_PINCFG95_PULLCFG95_PU100K = 7
} |
| |
| enum | GPIO_PINCFG95_DS95_Enum { GPIO_PINCFG95_DS95_0P1X = 0
, GPIO_PINCFG95_DS95_0P5X = 1
} |
| |
| enum | GPIO_PINCFG95_OUTCFG95_Enum { GPIO_PINCFG95_OUTCFG95_DIS = 0
, GPIO_PINCFG95_OUTCFG95_PUSHPULL = 1
, GPIO_PINCFG95_OUTCFG95_OD = 2
, GPIO_PINCFG95_OUTCFG95_TS = 3
} |
| |
| enum | GPIO_PINCFG95_IRPTEN95_Enum { GPIO_PINCFG95_IRPTEN95_DIS = 0
, GPIO_PINCFG95_IRPTEN95_INTFALL = 1
, GPIO_PINCFG95_IRPTEN95_INTRISE = 2
, GPIO_PINCFG95_IRPTEN95_INTANY = 3
} |
| |
| enum | GPIO_PINCFG95_FNCSEL95_Enum {
GPIO_PINCFG95_FNCSEL95_MSPI1_0 = 0
, GPIO_PINCFG95_FNCSEL95_RESERVED1 = 1
, GPIO_PINCFG95_FNCSEL95_RESERVED2 = 2
, GPIO_PINCFG95_FNCSEL95_GPIO = 3
,
GPIO_PINCFG95_FNCSEL95_RESERVED4 = 4
, GPIO_PINCFG95_FNCSEL95_RESERVED5 = 5
, GPIO_PINCFG95_FNCSEL95_CT95 = 6
, GPIO_PINCFG95_FNCSEL95_NCE95 = 7
,
GPIO_PINCFG95_FNCSEL95_OBSBUS15 = 8
, GPIO_PINCFG95_FNCSEL95_RESERVED9 = 9
, GPIO_PINCFG95_FNCSEL95_RESERVED10 = 10
, GPIO_PINCFG95_FNCSEL95_FPIO = 11
,
GPIO_PINCFG95_FNCSEL95_RESERVED12 = 12
, GPIO_PINCFG95_FNCSEL95_RESERVED13 = 13
, GPIO_PINCFG95_FNCSEL95_RESERVED14 = 14
, GPIO_PINCFG95_FNCSEL95_RESERVED15 = 15
} |
| |
| enum | GPIO_PINCFG96_NCEPOL96_Enum { GPIO_PINCFG96_NCEPOL96_LOW = 0
, GPIO_PINCFG96_NCEPOL96_HIGH = 1
} |
| |
| enum | GPIO_PINCFG96_NCESRC96_Enum {
GPIO_PINCFG96_NCESRC96_IOM0CE0 = 0
, GPIO_PINCFG96_NCESRC96_IOM0CE1 = 1
, GPIO_PINCFG96_NCESRC96_IOM0CE2 = 2
, GPIO_PINCFG96_NCESRC96_IOM0CE3 = 3
,
GPIO_PINCFG96_NCESRC96_IOM1CE0 = 4
, GPIO_PINCFG96_NCESRC96_IOM1CE1 = 5
, GPIO_PINCFG96_NCESRC96_IOM1CE2 = 6
, GPIO_PINCFG96_NCESRC96_IOM1CE3 = 7
,
GPIO_PINCFG96_NCESRC96_IOM2CE0 = 8
, GPIO_PINCFG96_NCESRC96_IOM2CE1 = 9
, GPIO_PINCFG96_NCESRC96_IOM2CE2 = 10
, GPIO_PINCFG96_NCESRC96_IOM2CE3 = 11
,
GPIO_PINCFG96_NCESRC96_IOM3CE0 = 12
, GPIO_PINCFG96_NCESRC96_IOM3CE1 = 13
, GPIO_PINCFG96_NCESRC96_IOM3CE2 = 14
, GPIO_PINCFG96_NCESRC96_IOM3CE3 = 15
,
GPIO_PINCFG96_NCESRC96_IOM4CE0 = 16
, GPIO_PINCFG96_NCESRC96_IOM4CE1 = 17
, GPIO_PINCFG96_NCESRC96_IOM4CE2 = 18
, GPIO_PINCFG96_NCESRC96_IOM4CE3 = 19
,
GPIO_PINCFG96_NCESRC96_IOM5CE0 = 20
, GPIO_PINCFG96_NCESRC96_IOM5CE1 = 21
, GPIO_PINCFG96_NCESRC96_IOM5CE2 = 22
, GPIO_PINCFG96_NCESRC96_IOM5CE3 = 23
,
GPIO_PINCFG96_NCESRC96_IOM6CE0 = 24
, GPIO_PINCFG96_NCESRC96_IOM6CE1 = 25
, GPIO_PINCFG96_NCESRC96_IOM6CE2 = 26
, GPIO_PINCFG96_NCESRC96_IOM6CE3 = 27
,
GPIO_PINCFG96_NCESRC96_IOM7CE0 = 28
, GPIO_PINCFG96_NCESRC96_IOM7CE1 = 29
, GPIO_PINCFG96_NCESRC96_IOM7CE2 = 30
, GPIO_PINCFG96_NCESRC96_IOM7CE3 = 31
,
GPIO_PINCFG96_NCESRC96_MSPI0CEN0 = 32
, GPIO_PINCFG96_NCESRC96_MSPI0CEN1 = 33
, GPIO_PINCFG96_NCESRC96_MSPI1CEN0 = 34
, GPIO_PINCFG96_NCESRC96_MSPI1CEN1 = 35
,
GPIO_PINCFG96_NCESRC96_MSPI2CEN0 = 36
, GPIO_PINCFG96_NCESRC96_MSPI2CEN1 = 37
, GPIO_PINCFG96_NCESRC96_DC_DPI_DE = 38
, GPIO_PINCFG96_NCESRC96_DISP_CONT_CSX = 39
,
GPIO_PINCFG96_NCESRC96_DC_SPI_CS_N = 40
, GPIO_PINCFG96_NCESRC96_DC_QSPI_CS_N = 41
, GPIO_PINCFG96_NCESRC96_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG96_PULLCFG96_Enum {
GPIO_PINCFG96_PULLCFG96_DIS = 0
, GPIO_PINCFG96_PULLCFG96_PD50K = 1
, GPIO_PINCFG96_PULLCFG96_PU15K = 2
, GPIO_PINCFG96_PULLCFG96_PU6K = 3
,
GPIO_PINCFG96_PULLCFG96_PU12K = 4
, GPIO_PINCFG96_PULLCFG96_PU24K = 5
, GPIO_PINCFG96_PULLCFG96_PU50K = 6
, GPIO_PINCFG96_PULLCFG96_PU100K = 7
} |
| |
| enum | GPIO_PINCFG96_DS96_Enum { GPIO_PINCFG96_DS96_0P1X = 0
, GPIO_PINCFG96_DS96_0P5X = 1
} |
| |
| enum | GPIO_PINCFG96_OUTCFG96_Enum { GPIO_PINCFG96_OUTCFG96_DIS = 0
, GPIO_PINCFG96_OUTCFG96_PUSHPULL = 1
, GPIO_PINCFG96_OUTCFG96_OD = 2
, GPIO_PINCFG96_OUTCFG96_TS = 3
} |
| |
| enum | GPIO_PINCFG96_IRPTEN96_Enum { GPIO_PINCFG96_IRPTEN96_DIS = 0
, GPIO_PINCFG96_IRPTEN96_INTFALL = 1
, GPIO_PINCFG96_IRPTEN96_INTRISE = 2
, GPIO_PINCFG96_IRPTEN96_INTANY = 3
} |
| |
| enum | GPIO_PINCFG96_FNCSEL96_Enum {
GPIO_PINCFG96_FNCSEL96_MSPI1_1 = 0
, GPIO_PINCFG96_FNCSEL96_RESERVED1 = 1
, GPIO_PINCFG96_FNCSEL96_RESERVED2 = 2
, GPIO_PINCFG96_FNCSEL96_GPIO = 3
,
GPIO_PINCFG96_FNCSEL96_RESERVED4 = 4
, GPIO_PINCFG96_FNCSEL96_RESERVED5 = 5
, GPIO_PINCFG96_FNCSEL96_CT96 = 6
, GPIO_PINCFG96_FNCSEL96_NCE96 = 7
,
GPIO_PINCFG96_FNCSEL96_OBSBUS0 = 8
, GPIO_PINCFG96_FNCSEL96_RESERVED9 = 9
, GPIO_PINCFG96_FNCSEL96_RESERVED10 = 10
, GPIO_PINCFG96_FNCSEL96_FPIO = 11
,
GPIO_PINCFG96_FNCSEL96_RESERVED12 = 12
, GPIO_PINCFG96_FNCSEL96_RESERVED13 = 13
, GPIO_PINCFG96_FNCSEL96_RESERVED14 = 14
, GPIO_PINCFG96_FNCSEL96_RESERVED15 = 15
} |
| |
| enum | GPIO_PINCFG97_NCEPOL97_Enum { GPIO_PINCFG97_NCEPOL97_LOW = 0
, GPIO_PINCFG97_NCEPOL97_HIGH = 1
} |
| |
| enum | GPIO_PINCFG97_NCESRC97_Enum {
GPIO_PINCFG97_NCESRC97_IOM0CE0 = 0
, GPIO_PINCFG97_NCESRC97_IOM0CE1 = 1
, GPIO_PINCFG97_NCESRC97_IOM0CE2 = 2
, GPIO_PINCFG97_NCESRC97_IOM0CE3 = 3
,
GPIO_PINCFG97_NCESRC97_IOM1CE0 = 4
, GPIO_PINCFG97_NCESRC97_IOM1CE1 = 5
, GPIO_PINCFG97_NCESRC97_IOM1CE2 = 6
, GPIO_PINCFG97_NCESRC97_IOM1CE3 = 7
,
GPIO_PINCFG97_NCESRC97_IOM2CE0 = 8
, GPIO_PINCFG97_NCESRC97_IOM2CE1 = 9
, GPIO_PINCFG97_NCESRC97_IOM2CE2 = 10
, GPIO_PINCFG97_NCESRC97_IOM2CE3 = 11
,
GPIO_PINCFG97_NCESRC97_IOM3CE0 = 12
, GPIO_PINCFG97_NCESRC97_IOM3CE1 = 13
, GPIO_PINCFG97_NCESRC97_IOM3CE2 = 14
, GPIO_PINCFG97_NCESRC97_IOM3CE3 = 15
,
GPIO_PINCFG97_NCESRC97_IOM4CE0 = 16
, GPIO_PINCFG97_NCESRC97_IOM4CE1 = 17
, GPIO_PINCFG97_NCESRC97_IOM4CE2 = 18
, GPIO_PINCFG97_NCESRC97_IOM4CE3 = 19
,
GPIO_PINCFG97_NCESRC97_IOM5CE0 = 20
, GPIO_PINCFG97_NCESRC97_IOM5CE1 = 21
, GPIO_PINCFG97_NCESRC97_IOM5CE2 = 22
, GPIO_PINCFG97_NCESRC97_IOM5CE3 = 23
,
GPIO_PINCFG97_NCESRC97_IOM6CE0 = 24
, GPIO_PINCFG97_NCESRC97_IOM6CE1 = 25
, GPIO_PINCFG97_NCESRC97_IOM6CE2 = 26
, GPIO_PINCFG97_NCESRC97_IOM6CE3 = 27
,
GPIO_PINCFG97_NCESRC97_IOM7CE0 = 28
, GPIO_PINCFG97_NCESRC97_IOM7CE1 = 29
, GPIO_PINCFG97_NCESRC97_IOM7CE2 = 30
, GPIO_PINCFG97_NCESRC97_IOM7CE3 = 31
,
GPIO_PINCFG97_NCESRC97_MSPI0CEN0 = 32
, GPIO_PINCFG97_NCESRC97_MSPI0CEN1 = 33
, GPIO_PINCFG97_NCESRC97_MSPI1CEN0 = 34
, GPIO_PINCFG97_NCESRC97_MSPI1CEN1 = 35
,
GPIO_PINCFG97_NCESRC97_MSPI2CEN0 = 36
, GPIO_PINCFG97_NCESRC97_MSPI2CEN1 = 37
, GPIO_PINCFG97_NCESRC97_DC_DPI_DE = 38
, GPIO_PINCFG97_NCESRC97_DISP_CONT_CSX = 39
,
GPIO_PINCFG97_NCESRC97_DC_SPI_CS_N = 40
, GPIO_PINCFG97_NCESRC97_DC_QSPI_CS_N = 41
, GPIO_PINCFG97_NCESRC97_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG97_PULLCFG97_Enum {
GPIO_PINCFG97_PULLCFG97_DIS = 0
, GPIO_PINCFG97_PULLCFG97_PD50K = 1
, GPIO_PINCFG97_PULLCFG97_PU15K = 2
, GPIO_PINCFG97_PULLCFG97_PU6K = 3
,
GPIO_PINCFG97_PULLCFG97_PU12K = 4
, GPIO_PINCFG97_PULLCFG97_PU24K = 5
, GPIO_PINCFG97_PULLCFG97_PU50K = 6
, GPIO_PINCFG97_PULLCFG97_PU100K = 7
} |
| |
| enum | GPIO_PINCFG97_DS97_Enum { GPIO_PINCFG97_DS97_0P1X = 0
, GPIO_PINCFG97_DS97_0P5X = 1
} |
| |
| enum | GPIO_PINCFG97_OUTCFG97_Enum { GPIO_PINCFG97_OUTCFG97_DIS = 0
, GPIO_PINCFG97_OUTCFG97_PUSHPULL = 1
, GPIO_PINCFG97_OUTCFG97_OD = 2
, GPIO_PINCFG97_OUTCFG97_TS = 3
} |
| |
| enum | GPIO_PINCFG97_IRPTEN97_Enum { GPIO_PINCFG97_IRPTEN97_DIS = 0
, GPIO_PINCFG97_IRPTEN97_INTFALL = 1
, GPIO_PINCFG97_IRPTEN97_INTRISE = 2
, GPIO_PINCFG97_IRPTEN97_INTANY = 3
} |
| |
| enum | GPIO_PINCFG97_FNCSEL97_Enum {
GPIO_PINCFG97_FNCSEL97_MSPI1_2 = 0
, GPIO_PINCFG97_FNCSEL97_RESERVED1 = 1
, GPIO_PINCFG97_FNCSEL97_RESERVED2 = 2
, GPIO_PINCFG97_FNCSEL97_GPIO = 3
,
GPIO_PINCFG97_FNCSEL97_RESERVED4 = 4
, GPIO_PINCFG97_FNCSEL97_RESERVED5 = 5
, GPIO_PINCFG97_FNCSEL97_CT97 = 6
, GPIO_PINCFG97_FNCSEL97_NCE97 = 7
,
GPIO_PINCFG97_FNCSEL97_OBSBUS1 = 8
, GPIO_PINCFG97_FNCSEL97_RESERVED9 = 9
, GPIO_PINCFG97_FNCSEL97_RESERVED10 = 10
, GPIO_PINCFG97_FNCSEL97_FPIO = 11
,
GPIO_PINCFG97_FNCSEL97_RESERVED12 = 12
, GPIO_PINCFG97_FNCSEL97_RESERVED13 = 13
, GPIO_PINCFG97_FNCSEL97_RESERVED14 = 14
, GPIO_PINCFG97_FNCSEL97_RESERVED15 = 15
} |
| |
| enum | GPIO_PINCFG98_NCEPOL98_Enum { GPIO_PINCFG98_NCEPOL98_LOW = 0
, GPIO_PINCFG98_NCEPOL98_HIGH = 1
} |
| |
| enum | GPIO_PINCFG98_NCESRC98_Enum {
GPIO_PINCFG98_NCESRC98_IOM0CE0 = 0
, GPIO_PINCFG98_NCESRC98_IOM0CE1 = 1
, GPIO_PINCFG98_NCESRC98_IOM0CE2 = 2
, GPIO_PINCFG98_NCESRC98_IOM0CE3 = 3
,
GPIO_PINCFG98_NCESRC98_IOM1CE0 = 4
, GPIO_PINCFG98_NCESRC98_IOM1CE1 = 5
, GPIO_PINCFG98_NCESRC98_IOM1CE2 = 6
, GPIO_PINCFG98_NCESRC98_IOM1CE3 = 7
,
GPIO_PINCFG98_NCESRC98_IOM2CE0 = 8
, GPIO_PINCFG98_NCESRC98_IOM2CE1 = 9
, GPIO_PINCFG98_NCESRC98_IOM2CE2 = 10
, GPIO_PINCFG98_NCESRC98_IOM2CE3 = 11
,
GPIO_PINCFG98_NCESRC98_IOM3CE0 = 12
, GPIO_PINCFG98_NCESRC98_IOM3CE1 = 13
, GPIO_PINCFG98_NCESRC98_IOM3CE2 = 14
, GPIO_PINCFG98_NCESRC98_IOM3CE3 = 15
,
GPIO_PINCFG98_NCESRC98_IOM4CE0 = 16
, GPIO_PINCFG98_NCESRC98_IOM4CE1 = 17
, GPIO_PINCFG98_NCESRC98_IOM4CE2 = 18
, GPIO_PINCFG98_NCESRC98_IOM4CE3 = 19
,
GPIO_PINCFG98_NCESRC98_IOM5CE0 = 20
, GPIO_PINCFG98_NCESRC98_IOM5CE1 = 21
, GPIO_PINCFG98_NCESRC98_IOM5CE2 = 22
, GPIO_PINCFG98_NCESRC98_IOM5CE3 = 23
,
GPIO_PINCFG98_NCESRC98_IOM6CE0 = 24
, GPIO_PINCFG98_NCESRC98_IOM6CE1 = 25
, GPIO_PINCFG98_NCESRC98_IOM6CE2 = 26
, GPIO_PINCFG98_NCESRC98_IOM6CE3 = 27
,
GPIO_PINCFG98_NCESRC98_IOM7CE0 = 28
, GPIO_PINCFG98_NCESRC98_IOM7CE1 = 29
, GPIO_PINCFG98_NCESRC98_IOM7CE2 = 30
, GPIO_PINCFG98_NCESRC98_IOM7CE3 = 31
,
GPIO_PINCFG98_NCESRC98_MSPI0CEN0 = 32
, GPIO_PINCFG98_NCESRC98_MSPI0CEN1 = 33
, GPIO_PINCFG98_NCESRC98_MSPI1CEN0 = 34
, GPIO_PINCFG98_NCESRC98_MSPI1CEN1 = 35
,
GPIO_PINCFG98_NCESRC98_MSPI2CEN0 = 36
, GPIO_PINCFG98_NCESRC98_MSPI2CEN1 = 37
, GPIO_PINCFG98_NCESRC98_DC_DPI_DE = 38
, GPIO_PINCFG98_NCESRC98_DISP_CONT_CSX = 39
,
GPIO_PINCFG98_NCESRC98_DC_SPI_CS_N = 40
, GPIO_PINCFG98_NCESRC98_DC_QSPI_CS_N = 41
, GPIO_PINCFG98_NCESRC98_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG98_PULLCFG98_Enum {
GPIO_PINCFG98_PULLCFG98_DIS = 0
, GPIO_PINCFG98_PULLCFG98_PD50K = 1
, GPIO_PINCFG98_PULLCFG98_PU15K = 2
, GPIO_PINCFG98_PULLCFG98_PU6K = 3
,
GPIO_PINCFG98_PULLCFG98_PU12K = 4
, GPIO_PINCFG98_PULLCFG98_PU24K = 5
, GPIO_PINCFG98_PULLCFG98_PU50K = 6
, GPIO_PINCFG98_PULLCFG98_PU100K = 7
} |
| |
| enum | GPIO_PINCFG98_DS98_Enum { GPIO_PINCFG98_DS98_0P1X = 0
, GPIO_PINCFG98_DS98_0P5X = 1
} |
| |
| enum | GPIO_PINCFG98_OUTCFG98_Enum { GPIO_PINCFG98_OUTCFG98_DIS = 0
, GPIO_PINCFG98_OUTCFG98_PUSHPULL = 1
, GPIO_PINCFG98_OUTCFG98_OD = 2
, GPIO_PINCFG98_OUTCFG98_TS = 3
} |
| |
| enum | GPIO_PINCFG98_IRPTEN98_Enum { GPIO_PINCFG98_IRPTEN98_DIS = 0
, GPIO_PINCFG98_IRPTEN98_INTFALL = 1
, GPIO_PINCFG98_IRPTEN98_INTRISE = 2
, GPIO_PINCFG98_IRPTEN98_INTANY = 3
} |
| |
| enum | GPIO_PINCFG98_FNCSEL98_Enum {
GPIO_PINCFG98_FNCSEL98_MSPI1_3 = 0
, GPIO_PINCFG98_FNCSEL98_RESERVED1 = 1
, GPIO_PINCFG98_FNCSEL98_RESERVED2 = 2
, GPIO_PINCFG98_FNCSEL98_GPIO = 3
,
GPIO_PINCFG98_FNCSEL98_RESERVED4 = 4
, GPIO_PINCFG98_FNCSEL98_RESERVED5 = 5
, GPIO_PINCFG98_FNCSEL98_CT98 = 6
, GPIO_PINCFG98_FNCSEL98_NCE98 = 7
,
GPIO_PINCFG98_FNCSEL98_OBSBUS2 = 8
, GPIO_PINCFG98_FNCSEL98_RESERVED9 = 9
, GPIO_PINCFG98_FNCSEL98_RESERVED10 = 10
, GPIO_PINCFG98_FNCSEL98_FPIO = 11
,
GPIO_PINCFG98_FNCSEL98_RESERVED12 = 12
, GPIO_PINCFG98_FNCSEL98_RESERVED13 = 13
, GPIO_PINCFG98_FNCSEL98_RESERVED14 = 14
, GPIO_PINCFG98_FNCSEL98_RESERVED15 = 15
} |
| |
| enum | GPIO_PINCFG99_NCEPOL99_Enum { GPIO_PINCFG99_NCEPOL99_LOW = 0
, GPIO_PINCFG99_NCEPOL99_HIGH = 1
} |
| |
| enum | GPIO_PINCFG99_NCESRC99_Enum {
GPIO_PINCFG99_NCESRC99_IOM0CE0 = 0
, GPIO_PINCFG99_NCESRC99_IOM0CE1 = 1
, GPIO_PINCFG99_NCESRC99_IOM0CE2 = 2
, GPIO_PINCFG99_NCESRC99_IOM0CE3 = 3
,
GPIO_PINCFG99_NCESRC99_IOM1CE0 = 4
, GPIO_PINCFG99_NCESRC99_IOM1CE1 = 5
, GPIO_PINCFG99_NCESRC99_IOM1CE2 = 6
, GPIO_PINCFG99_NCESRC99_IOM1CE3 = 7
,
GPIO_PINCFG99_NCESRC99_IOM2CE0 = 8
, GPIO_PINCFG99_NCESRC99_IOM2CE1 = 9
, GPIO_PINCFG99_NCESRC99_IOM2CE2 = 10
, GPIO_PINCFG99_NCESRC99_IOM2CE3 = 11
,
GPIO_PINCFG99_NCESRC99_IOM3CE0 = 12
, GPIO_PINCFG99_NCESRC99_IOM3CE1 = 13
, GPIO_PINCFG99_NCESRC99_IOM3CE2 = 14
, GPIO_PINCFG99_NCESRC99_IOM3CE3 = 15
,
GPIO_PINCFG99_NCESRC99_IOM4CE0 = 16
, GPIO_PINCFG99_NCESRC99_IOM4CE1 = 17
, GPIO_PINCFG99_NCESRC99_IOM4CE2 = 18
, GPIO_PINCFG99_NCESRC99_IOM4CE3 = 19
,
GPIO_PINCFG99_NCESRC99_IOM5CE0 = 20
, GPIO_PINCFG99_NCESRC99_IOM5CE1 = 21
, GPIO_PINCFG99_NCESRC99_IOM5CE2 = 22
, GPIO_PINCFG99_NCESRC99_IOM5CE3 = 23
,
GPIO_PINCFG99_NCESRC99_IOM6CE0 = 24
, GPIO_PINCFG99_NCESRC99_IOM6CE1 = 25
, GPIO_PINCFG99_NCESRC99_IOM6CE2 = 26
, GPIO_PINCFG99_NCESRC99_IOM6CE3 = 27
,
GPIO_PINCFG99_NCESRC99_IOM7CE0 = 28
, GPIO_PINCFG99_NCESRC99_IOM7CE1 = 29
, GPIO_PINCFG99_NCESRC99_IOM7CE2 = 30
, GPIO_PINCFG99_NCESRC99_IOM7CE3 = 31
,
GPIO_PINCFG99_NCESRC99_MSPI0CEN0 = 32
, GPIO_PINCFG99_NCESRC99_MSPI0CEN1 = 33
, GPIO_PINCFG99_NCESRC99_MSPI1CEN0 = 34
, GPIO_PINCFG99_NCESRC99_MSPI1CEN1 = 35
,
GPIO_PINCFG99_NCESRC99_MSPI2CEN0 = 36
, GPIO_PINCFG99_NCESRC99_MSPI2CEN1 = 37
, GPIO_PINCFG99_NCESRC99_DC_DPI_DE = 38
, GPIO_PINCFG99_NCESRC99_DISP_CONT_CSX = 39
,
GPIO_PINCFG99_NCESRC99_DC_SPI_CS_N = 40
, GPIO_PINCFG99_NCESRC99_DC_QSPI_CS_N = 41
, GPIO_PINCFG99_NCESRC99_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG99_PULLCFG99_Enum {
GPIO_PINCFG99_PULLCFG99_DIS = 0
, GPIO_PINCFG99_PULLCFG99_PD50K = 1
, GPIO_PINCFG99_PULLCFG99_PU15K = 2
, GPIO_PINCFG99_PULLCFG99_PU6K = 3
,
GPIO_PINCFG99_PULLCFG99_PU12K = 4
, GPIO_PINCFG99_PULLCFG99_PU24K = 5
, GPIO_PINCFG99_PULLCFG99_PU50K = 6
, GPIO_PINCFG99_PULLCFG99_PU100K = 7
} |
| |
| enum | GPIO_PINCFG99_DS99_Enum { GPIO_PINCFG99_DS99_0P1X = 0
, GPIO_PINCFG99_DS99_0P5X = 1
} |
| |
| enum | GPIO_PINCFG99_OUTCFG99_Enum { GPIO_PINCFG99_OUTCFG99_DIS = 0
, GPIO_PINCFG99_OUTCFG99_PUSHPULL = 1
, GPIO_PINCFG99_OUTCFG99_OD = 2
, GPIO_PINCFG99_OUTCFG99_TS = 3
} |
| |
| enum | GPIO_PINCFG99_IRPTEN99_Enum { GPIO_PINCFG99_IRPTEN99_DIS = 0
, GPIO_PINCFG99_IRPTEN99_INTFALL = 1
, GPIO_PINCFG99_IRPTEN99_INTRISE = 2
, GPIO_PINCFG99_IRPTEN99_INTANY = 3
} |
| |
| enum | GPIO_PINCFG99_FNCSEL99_Enum {
GPIO_PINCFG99_FNCSEL99_MSPI1_4 = 0
, GPIO_PINCFG99_FNCSEL99_RESERVED1 = 1
, GPIO_PINCFG99_FNCSEL99_RESERVED2 = 2
, GPIO_PINCFG99_FNCSEL99_GPIO = 3
,
GPIO_PINCFG99_FNCSEL99_RESERVED4 = 4
, GPIO_PINCFG99_FNCSEL99_RESERVED5 = 5
, GPIO_PINCFG99_FNCSEL99_CT99 = 6
, GPIO_PINCFG99_FNCSEL99_NCE99 = 7
,
GPIO_PINCFG99_FNCSEL99_OBSBUS3 = 8
, GPIO_PINCFG99_FNCSEL99_RESERVED9 = 9
, GPIO_PINCFG99_FNCSEL99_RESERVED10 = 10
, GPIO_PINCFG99_FNCSEL99_FPIO = 11
,
GPIO_PINCFG99_FNCSEL99_RESERVED12 = 12
, GPIO_PINCFG99_FNCSEL99_RESERVED13 = 13
, GPIO_PINCFG99_FNCSEL99_RESERVED14 = 14
, GPIO_PINCFG99_FNCSEL99_RESERVED15 = 15
} |
| |
| enum | GPIO_PINCFG100_NCEPOL100_Enum { GPIO_PINCFG100_NCEPOL100_LOW = 0
, GPIO_PINCFG100_NCEPOL100_HIGH = 1
} |
| |
| enum | GPIO_PINCFG100_NCESRC100_Enum {
GPIO_PINCFG100_NCESRC100_IOM0CE0 = 0
, GPIO_PINCFG100_NCESRC100_IOM0CE1 = 1
, GPIO_PINCFG100_NCESRC100_IOM0CE2 = 2
, GPIO_PINCFG100_NCESRC100_IOM0CE3 = 3
,
GPIO_PINCFG100_NCESRC100_IOM1CE0 = 4
, GPIO_PINCFG100_NCESRC100_IOM1CE1 = 5
, GPIO_PINCFG100_NCESRC100_IOM1CE2 = 6
, GPIO_PINCFG100_NCESRC100_IOM1CE3 = 7
,
GPIO_PINCFG100_NCESRC100_IOM2CE0 = 8
, GPIO_PINCFG100_NCESRC100_IOM2CE1 = 9
, GPIO_PINCFG100_NCESRC100_IOM2CE2 = 10
, GPIO_PINCFG100_NCESRC100_IOM2CE3 = 11
,
GPIO_PINCFG100_NCESRC100_IOM3CE0 = 12
, GPIO_PINCFG100_NCESRC100_IOM3CE1 = 13
, GPIO_PINCFG100_NCESRC100_IOM3CE2 = 14
, GPIO_PINCFG100_NCESRC100_IOM3CE3 = 15
,
GPIO_PINCFG100_NCESRC100_IOM4CE0 = 16
, GPIO_PINCFG100_NCESRC100_IOM4CE1 = 17
, GPIO_PINCFG100_NCESRC100_IOM4CE2 = 18
, GPIO_PINCFG100_NCESRC100_IOM4CE3 = 19
,
GPIO_PINCFG100_NCESRC100_IOM5CE0 = 20
, GPIO_PINCFG100_NCESRC100_IOM5CE1 = 21
, GPIO_PINCFG100_NCESRC100_IOM5CE2 = 22
, GPIO_PINCFG100_NCESRC100_IOM5CE3 = 23
,
GPIO_PINCFG100_NCESRC100_IOM6CE0 = 24
, GPIO_PINCFG100_NCESRC100_IOM6CE1 = 25
, GPIO_PINCFG100_NCESRC100_IOM6CE2 = 26
, GPIO_PINCFG100_NCESRC100_IOM6CE3 = 27
,
GPIO_PINCFG100_NCESRC100_IOM7CE0 = 28
, GPIO_PINCFG100_NCESRC100_IOM7CE1 = 29
, GPIO_PINCFG100_NCESRC100_IOM7CE2 = 30
, GPIO_PINCFG100_NCESRC100_IOM7CE3 = 31
,
GPIO_PINCFG100_NCESRC100_MSPI0CEN0 = 32
, GPIO_PINCFG100_NCESRC100_MSPI0CEN1 = 33
, GPIO_PINCFG100_NCESRC100_MSPI1CEN0 = 34
, GPIO_PINCFG100_NCESRC100_MSPI1CEN1 = 35
,
GPIO_PINCFG100_NCESRC100_MSPI2CEN0 = 36
, GPIO_PINCFG100_NCESRC100_MSPI2CEN1 = 37
, GPIO_PINCFG100_NCESRC100_DC_DPI_DE = 38
, GPIO_PINCFG100_NCESRC100_DISP_CONT_CSX = 39
,
GPIO_PINCFG100_NCESRC100_DC_SPI_CS_N = 40
, GPIO_PINCFG100_NCESRC100_DC_QSPI_CS_N = 41
, GPIO_PINCFG100_NCESRC100_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG100_PULLCFG100_Enum {
GPIO_PINCFG100_PULLCFG100_DIS = 0
, GPIO_PINCFG100_PULLCFG100_PD50K = 1
, GPIO_PINCFG100_PULLCFG100_PU15K = 2
, GPIO_PINCFG100_PULLCFG100_PU6K = 3
,
GPIO_PINCFG100_PULLCFG100_PU12K = 4
, GPIO_PINCFG100_PULLCFG100_PU24K = 5
, GPIO_PINCFG100_PULLCFG100_PU50K = 6
, GPIO_PINCFG100_PULLCFG100_PU100K = 7
} |
| |
| enum | GPIO_PINCFG100_DS100_Enum { GPIO_PINCFG100_DS100_0P1X = 0
, GPIO_PINCFG100_DS100_0P5X = 1
} |
| |
| enum | GPIO_PINCFG100_OUTCFG100_Enum { GPIO_PINCFG100_OUTCFG100_DIS = 0
, GPIO_PINCFG100_OUTCFG100_PUSHPULL = 1
, GPIO_PINCFG100_OUTCFG100_OD = 2
, GPIO_PINCFG100_OUTCFG100_TS = 3
} |
| |
| enum | GPIO_PINCFG100_IRPTEN100_Enum { GPIO_PINCFG100_IRPTEN100_DIS = 0
, GPIO_PINCFG100_IRPTEN100_INTFALL = 1
, GPIO_PINCFG100_IRPTEN100_INTRISE = 2
, GPIO_PINCFG100_IRPTEN100_INTANY = 3
} |
| |
| enum | GPIO_PINCFG100_FNCSEL100_Enum {
GPIO_PINCFG100_FNCSEL100_MSPI1_5 = 0
, GPIO_PINCFG100_FNCSEL100_RESERVED1 = 1
, GPIO_PINCFG100_FNCSEL100_RESERVED2 = 2
, GPIO_PINCFG100_FNCSEL100_GPIO = 3
,
GPIO_PINCFG100_FNCSEL100_RESERVED4 = 4
, GPIO_PINCFG100_FNCSEL100_RESERVED5 = 5
, GPIO_PINCFG100_FNCSEL100_CT100 = 6
, GPIO_PINCFG100_FNCSEL100_NCE100 = 7
,
GPIO_PINCFG100_FNCSEL100_OBSBUS4 = 8
, GPIO_PINCFG100_FNCSEL100_RESERVED9 = 9
, GPIO_PINCFG100_FNCSEL100_RESERVED10 = 10
, GPIO_PINCFG100_FNCSEL100_FPIO = 11
,
GPIO_PINCFG100_FNCSEL100_RESERVED12 = 12
, GPIO_PINCFG100_FNCSEL100_RESERVED13 = 13
, GPIO_PINCFG100_FNCSEL100_RESERVED14 = 14
, GPIO_PINCFG100_FNCSEL100_RESERVED15 = 15
} |
| |
| enum | GPIO_PINCFG101_NCEPOL101_Enum { GPIO_PINCFG101_NCEPOL101_LOW = 0
, GPIO_PINCFG101_NCEPOL101_HIGH = 1
} |
| |
| enum | GPIO_PINCFG101_NCESRC101_Enum {
GPIO_PINCFG101_NCESRC101_IOM0CE0 = 0
, GPIO_PINCFG101_NCESRC101_IOM0CE1 = 1
, GPIO_PINCFG101_NCESRC101_IOM0CE2 = 2
, GPIO_PINCFG101_NCESRC101_IOM0CE3 = 3
,
GPIO_PINCFG101_NCESRC101_IOM1CE0 = 4
, GPIO_PINCFG101_NCESRC101_IOM1CE1 = 5
, GPIO_PINCFG101_NCESRC101_IOM1CE2 = 6
, GPIO_PINCFG101_NCESRC101_IOM1CE3 = 7
,
GPIO_PINCFG101_NCESRC101_IOM2CE0 = 8
, GPIO_PINCFG101_NCESRC101_IOM2CE1 = 9
, GPIO_PINCFG101_NCESRC101_IOM2CE2 = 10
, GPIO_PINCFG101_NCESRC101_IOM2CE3 = 11
,
GPIO_PINCFG101_NCESRC101_IOM3CE0 = 12
, GPIO_PINCFG101_NCESRC101_IOM3CE1 = 13
, GPIO_PINCFG101_NCESRC101_IOM3CE2 = 14
, GPIO_PINCFG101_NCESRC101_IOM3CE3 = 15
,
GPIO_PINCFG101_NCESRC101_IOM4CE0 = 16
, GPIO_PINCFG101_NCESRC101_IOM4CE1 = 17
, GPIO_PINCFG101_NCESRC101_IOM4CE2 = 18
, GPIO_PINCFG101_NCESRC101_IOM4CE3 = 19
,
GPIO_PINCFG101_NCESRC101_IOM5CE0 = 20
, GPIO_PINCFG101_NCESRC101_IOM5CE1 = 21
, GPIO_PINCFG101_NCESRC101_IOM5CE2 = 22
, GPIO_PINCFG101_NCESRC101_IOM5CE3 = 23
,
GPIO_PINCFG101_NCESRC101_IOM6CE0 = 24
, GPIO_PINCFG101_NCESRC101_IOM6CE1 = 25
, GPIO_PINCFG101_NCESRC101_IOM6CE2 = 26
, GPIO_PINCFG101_NCESRC101_IOM6CE3 = 27
,
GPIO_PINCFG101_NCESRC101_IOM7CE0 = 28
, GPIO_PINCFG101_NCESRC101_IOM7CE1 = 29
, GPIO_PINCFG101_NCESRC101_IOM7CE2 = 30
, GPIO_PINCFG101_NCESRC101_IOM7CE3 = 31
,
GPIO_PINCFG101_NCESRC101_MSPI0CEN0 = 32
, GPIO_PINCFG101_NCESRC101_MSPI0CEN1 = 33
, GPIO_PINCFG101_NCESRC101_MSPI1CEN0 = 34
, GPIO_PINCFG101_NCESRC101_MSPI1CEN1 = 35
,
GPIO_PINCFG101_NCESRC101_MSPI2CEN0 = 36
, GPIO_PINCFG101_NCESRC101_MSPI2CEN1 = 37
, GPIO_PINCFG101_NCESRC101_DC_DPI_DE = 38
, GPIO_PINCFG101_NCESRC101_DISP_CONT_CSX = 39
,
GPIO_PINCFG101_NCESRC101_DC_SPI_CS_N = 40
, GPIO_PINCFG101_NCESRC101_DC_QSPI_CS_N = 41
, GPIO_PINCFG101_NCESRC101_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG101_PULLCFG101_Enum {
GPIO_PINCFG101_PULLCFG101_DIS = 0
, GPIO_PINCFG101_PULLCFG101_PD50K = 1
, GPIO_PINCFG101_PULLCFG101_PU15K = 2
, GPIO_PINCFG101_PULLCFG101_PU6K = 3
,
GPIO_PINCFG101_PULLCFG101_PU12K = 4
, GPIO_PINCFG101_PULLCFG101_PU24K = 5
, GPIO_PINCFG101_PULLCFG101_PU50K = 6
, GPIO_PINCFG101_PULLCFG101_PU100K = 7
} |
| |
| enum | GPIO_PINCFG101_DS101_Enum { GPIO_PINCFG101_DS101_0P1X = 0
, GPIO_PINCFG101_DS101_0P5X = 1
} |
| |
| enum | GPIO_PINCFG101_OUTCFG101_Enum { GPIO_PINCFG101_OUTCFG101_DIS = 0
, GPIO_PINCFG101_OUTCFG101_PUSHPULL = 1
, GPIO_PINCFG101_OUTCFG101_OD = 2
, GPIO_PINCFG101_OUTCFG101_TS = 3
} |
| |
| enum | GPIO_PINCFG101_IRPTEN101_Enum { GPIO_PINCFG101_IRPTEN101_DIS = 0
, GPIO_PINCFG101_IRPTEN101_INTFALL = 1
, GPIO_PINCFG101_IRPTEN101_INTRISE = 2
, GPIO_PINCFG101_IRPTEN101_INTANY = 3
} |
| |
| enum | GPIO_PINCFG101_FNCSEL101_Enum {
GPIO_PINCFG101_FNCSEL101_MSPI1_6 = 0
, GPIO_PINCFG101_FNCSEL101_RESERVED1 = 1
, GPIO_PINCFG101_FNCSEL101_RESERVED2 = 2
, GPIO_PINCFG101_FNCSEL101_GPIO = 3
,
GPIO_PINCFG101_FNCSEL101_RESERVED4 = 4
, GPIO_PINCFG101_FNCSEL101_RESERVED5 = 5
, GPIO_PINCFG101_FNCSEL101_CT101 = 6
, GPIO_PINCFG101_FNCSEL101_NCE101 = 7
,
GPIO_PINCFG101_FNCSEL101_OBSBUS5 = 8
, GPIO_PINCFG101_FNCSEL101_RESERVED9 = 9
, GPIO_PINCFG101_FNCSEL101_RESERVED10 = 10
, GPIO_PINCFG101_FNCSEL101_FPIO = 11
,
GPIO_PINCFG101_FNCSEL101_RESERVED12 = 12
, GPIO_PINCFG101_FNCSEL101_RESERVED13 = 13
, GPIO_PINCFG101_FNCSEL101_RESERVED14 = 14
, GPIO_PINCFG101_FNCSEL101_RESERVED15 = 15
} |
| |
| enum | GPIO_PINCFG102_NCEPOL102_Enum { GPIO_PINCFG102_NCEPOL102_LOW = 0
, GPIO_PINCFG102_NCEPOL102_HIGH = 1
} |
| |
| enum | GPIO_PINCFG102_NCESRC102_Enum {
GPIO_PINCFG102_NCESRC102_IOM0CE0 = 0
, GPIO_PINCFG102_NCESRC102_IOM0CE1 = 1
, GPIO_PINCFG102_NCESRC102_IOM0CE2 = 2
, GPIO_PINCFG102_NCESRC102_IOM0CE3 = 3
,
GPIO_PINCFG102_NCESRC102_IOM1CE0 = 4
, GPIO_PINCFG102_NCESRC102_IOM1CE1 = 5
, GPIO_PINCFG102_NCESRC102_IOM1CE2 = 6
, GPIO_PINCFG102_NCESRC102_IOM1CE3 = 7
,
GPIO_PINCFG102_NCESRC102_IOM2CE0 = 8
, GPIO_PINCFG102_NCESRC102_IOM2CE1 = 9
, GPIO_PINCFG102_NCESRC102_IOM2CE2 = 10
, GPIO_PINCFG102_NCESRC102_IOM2CE3 = 11
,
GPIO_PINCFG102_NCESRC102_IOM3CE0 = 12
, GPIO_PINCFG102_NCESRC102_IOM3CE1 = 13
, GPIO_PINCFG102_NCESRC102_IOM3CE2 = 14
, GPIO_PINCFG102_NCESRC102_IOM3CE3 = 15
,
GPIO_PINCFG102_NCESRC102_IOM4CE0 = 16
, GPIO_PINCFG102_NCESRC102_IOM4CE1 = 17
, GPIO_PINCFG102_NCESRC102_IOM4CE2 = 18
, GPIO_PINCFG102_NCESRC102_IOM4CE3 = 19
,
GPIO_PINCFG102_NCESRC102_IOM5CE0 = 20
, GPIO_PINCFG102_NCESRC102_IOM5CE1 = 21
, GPIO_PINCFG102_NCESRC102_IOM5CE2 = 22
, GPIO_PINCFG102_NCESRC102_IOM5CE3 = 23
,
GPIO_PINCFG102_NCESRC102_IOM6CE0 = 24
, GPIO_PINCFG102_NCESRC102_IOM6CE1 = 25
, GPIO_PINCFG102_NCESRC102_IOM6CE2 = 26
, GPIO_PINCFG102_NCESRC102_IOM6CE3 = 27
,
GPIO_PINCFG102_NCESRC102_IOM7CE0 = 28
, GPIO_PINCFG102_NCESRC102_IOM7CE1 = 29
, GPIO_PINCFG102_NCESRC102_IOM7CE2 = 30
, GPIO_PINCFG102_NCESRC102_IOM7CE3 = 31
,
GPIO_PINCFG102_NCESRC102_MSPI0CEN0 = 32
, GPIO_PINCFG102_NCESRC102_MSPI0CEN1 = 33
, GPIO_PINCFG102_NCESRC102_MSPI1CEN0 = 34
, GPIO_PINCFG102_NCESRC102_MSPI1CEN1 = 35
,
GPIO_PINCFG102_NCESRC102_MSPI2CEN0 = 36
, GPIO_PINCFG102_NCESRC102_MSPI2CEN1 = 37
, GPIO_PINCFG102_NCESRC102_DC_DPI_DE = 38
, GPIO_PINCFG102_NCESRC102_DISP_CONT_CSX = 39
,
GPIO_PINCFG102_NCESRC102_DC_SPI_CS_N = 40
, GPIO_PINCFG102_NCESRC102_DC_QSPI_CS_N = 41
, GPIO_PINCFG102_NCESRC102_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG102_PULLCFG102_Enum {
GPIO_PINCFG102_PULLCFG102_DIS = 0
, GPIO_PINCFG102_PULLCFG102_PD50K = 1
, GPIO_PINCFG102_PULLCFG102_PU15K = 2
, GPIO_PINCFG102_PULLCFG102_PU6K = 3
,
GPIO_PINCFG102_PULLCFG102_PU12K = 4
, GPIO_PINCFG102_PULLCFG102_PU24K = 5
, GPIO_PINCFG102_PULLCFG102_PU50K = 6
, GPIO_PINCFG102_PULLCFG102_PU100K = 7
} |
| |
| enum | GPIO_PINCFG102_DS102_Enum { GPIO_PINCFG102_DS102_0P1X = 0
, GPIO_PINCFG102_DS102_0P5X = 1
} |
| |
| enum | GPIO_PINCFG102_OUTCFG102_Enum { GPIO_PINCFG102_OUTCFG102_DIS = 0
, GPIO_PINCFG102_OUTCFG102_PUSHPULL = 1
, GPIO_PINCFG102_OUTCFG102_OD = 2
, GPIO_PINCFG102_OUTCFG102_TS = 3
} |
| |
| enum | GPIO_PINCFG102_IRPTEN102_Enum { GPIO_PINCFG102_IRPTEN102_DIS = 0
, GPIO_PINCFG102_IRPTEN102_INTFALL = 1
, GPIO_PINCFG102_IRPTEN102_INTRISE = 2
, GPIO_PINCFG102_IRPTEN102_INTANY = 3
} |
| |
| enum | GPIO_PINCFG102_FNCSEL102_Enum {
GPIO_PINCFG102_FNCSEL102_MSPI1_7 = 0
, GPIO_PINCFG102_FNCSEL102_RESERVED1 = 1
, GPIO_PINCFG102_FNCSEL102_RESERVED2 = 2
, GPIO_PINCFG102_FNCSEL102_GPIO = 3
,
GPIO_PINCFG102_FNCSEL102_RESERVED4 = 4
, GPIO_PINCFG102_FNCSEL102_RESERVED5 = 5
, GPIO_PINCFG102_FNCSEL102_CT102 = 6
, GPIO_PINCFG102_FNCSEL102_NCE102 = 7
,
GPIO_PINCFG102_FNCSEL102_OBSBUS6 = 8
, GPIO_PINCFG102_FNCSEL102_RESERVED9 = 9
, GPIO_PINCFG102_FNCSEL102_RESERVED10 = 10
, GPIO_PINCFG102_FNCSEL102_FPIO = 11
,
GPIO_PINCFG102_FNCSEL102_RESERVED12 = 12
, GPIO_PINCFG102_FNCSEL102_RESERVED13 = 13
, GPIO_PINCFG102_FNCSEL102_RESERVED14 = 14
, GPIO_PINCFG102_FNCSEL102_RESERVED15 = 15
} |
| |
| enum | GPIO_PINCFG103_NCEPOL103_Enum { GPIO_PINCFG103_NCEPOL103_LOW = 0
, GPIO_PINCFG103_NCEPOL103_HIGH = 1
} |
| |
| enum | GPIO_PINCFG103_NCESRC103_Enum {
GPIO_PINCFG103_NCESRC103_IOM0CE0 = 0
, GPIO_PINCFG103_NCESRC103_IOM0CE1 = 1
, GPIO_PINCFG103_NCESRC103_IOM0CE2 = 2
, GPIO_PINCFG103_NCESRC103_IOM0CE3 = 3
,
GPIO_PINCFG103_NCESRC103_IOM1CE0 = 4
, GPIO_PINCFG103_NCESRC103_IOM1CE1 = 5
, GPIO_PINCFG103_NCESRC103_IOM1CE2 = 6
, GPIO_PINCFG103_NCESRC103_IOM1CE3 = 7
,
GPIO_PINCFG103_NCESRC103_IOM2CE0 = 8
, GPIO_PINCFG103_NCESRC103_IOM2CE1 = 9
, GPIO_PINCFG103_NCESRC103_IOM2CE2 = 10
, GPIO_PINCFG103_NCESRC103_IOM2CE3 = 11
,
GPIO_PINCFG103_NCESRC103_IOM3CE0 = 12
, GPIO_PINCFG103_NCESRC103_IOM3CE1 = 13
, GPIO_PINCFG103_NCESRC103_IOM3CE2 = 14
, GPIO_PINCFG103_NCESRC103_IOM3CE3 = 15
,
GPIO_PINCFG103_NCESRC103_IOM4CE0 = 16
, GPIO_PINCFG103_NCESRC103_IOM4CE1 = 17
, GPIO_PINCFG103_NCESRC103_IOM4CE2 = 18
, GPIO_PINCFG103_NCESRC103_IOM4CE3 = 19
,
GPIO_PINCFG103_NCESRC103_IOM5CE0 = 20
, GPIO_PINCFG103_NCESRC103_IOM5CE1 = 21
, GPIO_PINCFG103_NCESRC103_IOM5CE2 = 22
, GPIO_PINCFG103_NCESRC103_IOM5CE3 = 23
,
GPIO_PINCFG103_NCESRC103_IOM6CE0 = 24
, GPIO_PINCFG103_NCESRC103_IOM6CE1 = 25
, GPIO_PINCFG103_NCESRC103_IOM6CE2 = 26
, GPIO_PINCFG103_NCESRC103_IOM6CE3 = 27
,
GPIO_PINCFG103_NCESRC103_IOM7CE0 = 28
, GPIO_PINCFG103_NCESRC103_IOM7CE1 = 29
, GPIO_PINCFG103_NCESRC103_IOM7CE2 = 30
, GPIO_PINCFG103_NCESRC103_IOM7CE3 = 31
,
GPIO_PINCFG103_NCESRC103_MSPI0CEN0 = 32
, GPIO_PINCFG103_NCESRC103_MSPI0CEN1 = 33
, GPIO_PINCFG103_NCESRC103_MSPI1CEN0 = 34
, GPIO_PINCFG103_NCESRC103_MSPI1CEN1 = 35
,
GPIO_PINCFG103_NCESRC103_MSPI2CEN0 = 36
, GPIO_PINCFG103_NCESRC103_MSPI2CEN1 = 37
, GPIO_PINCFG103_NCESRC103_DC_DPI_DE = 38
, GPIO_PINCFG103_NCESRC103_DISP_CONT_CSX = 39
,
GPIO_PINCFG103_NCESRC103_DC_SPI_CS_N = 40
, GPIO_PINCFG103_NCESRC103_DC_QSPI_CS_N = 41
, GPIO_PINCFG103_NCESRC103_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG103_PULLCFG103_Enum {
GPIO_PINCFG103_PULLCFG103_DIS = 0
, GPIO_PINCFG103_PULLCFG103_PD50K = 1
, GPIO_PINCFG103_PULLCFG103_PU15K = 2
, GPIO_PINCFG103_PULLCFG103_PU6K = 3
,
GPIO_PINCFG103_PULLCFG103_PU12K = 4
, GPIO_PINCFG103_PULLCFG103_PU24K = 5
, GPIO_PINCFG103_PULLCFG103_PU50K = 6
, GPIO_PINCFG103_PULLCFG103_PU100K = 7
} |
| |
| enum | GPIO_PINCFG103_DS103_Enum { GPIO_PINCFG103_DS103_0P1X = 0
, GPIO_PINCFG103_DS103_0P5X = 1
} |
| |
| enum | GPIO_PINCFG103_OUTCFG103_Enum { GPIO_PINCFG103_OUTCFG103_DIS = 0
, GPIO_PINCFG103_OUTCFG103_PUSHPULL = 1
, GPIO_PINCFG103_OUTCFG103_OD = 2
, GPIO_PINCFG103_OUTCFG103_TS = 3
} |
| |
| enum | GPIO_PINCFG103_IRPTEN103_Enum { GPIO_PINCFG103_IRPTEN103_DIS = 0
, GPIO_PINCFG103_IRPTEN103_INTFALL = 1
, GPIO_PINCFG103_IRPTEN103_INTRISE = 2
, GPIO_PINCFG103_IRPTEN103_INTANY = 3
} |
| |
| enum | GPIO_PINCFG103_FNCSEL103_Enum {
GPIO_PINCFG103_FNCSEL103_MSPI1_8 = 0
, GPIO_PINCFG103_FNCSEL103_RESERVED1 = 1
, GPIO_PINCFG103_FNCSEL103_RESERVED2 = 2
, GPIO_PINCFG103_FNCSEL103_GPIO = 3
,
GPIO_PINCFG103_FNCSEL103_RESERVED4 = 4
, GPIO_PINCFG103_FNCSEL103_RESERVED5 = 5
, GPIO_PINCFG103_FNCSEL103_CT103 = 6
, GPIO_PINCFG103_FNCSEL103_NCE103 = 7
,
GPIO_PINCFG103_FNCSEL103_OBSBUS7 = 8
, GPIO_PINCFG103_FNCSEL103_RESERVED9 = 9
, GPIO_PINCFG103_FNCSEL103_RESERVED10 = 10
, GPIO_PINCFG103_FNCSEL103_FPIO = 11
,
GPIO_PINCFG103_FNCSEL103_RESERVED12 = 12
, GPIO_PINCFG103_FNCSEL103_RESERVED13 = 13
, GPIO_PINCFG103_FNCSEL103_RESERVED14 = 14
, GPIO_PINCFG103_FNCSEL103_RESERVED15 = 15
} |
| |
| enum | GPIO_PINCFG104_NCEPOL104_Enum { GPIO_PINCFG104_NCEPOL104_LOW = 0
, GPIO_PINCFG104_NCEPOL104_HIGH = 1
} |
| |
| enum | GPIO_PINCFG104_NCESRC104_Enum {
GPIO_PINCFG104_NCESRC104_IOM0CE0 = 0
, GPIO_PINCFG104_NCESRC104_IOM0CE1 = 1
, GPIO_PINCFG104_NCESRC104_IOM0CE2 = 2
, GPIO_PINCFG104_NCESRC104_IOM0CE3 = 3
,
GPIO_PINCFG104_NCESRC104_IOM1CE0 = 4
, GPIO_PINCFG104_NCESRC104_IOM1CE1 = 5
, GPIO_PINCFG104_NCESRC104_IOM1CE2 = 6
, GPIO_PINCFG104_NCESRC104_IOM1CE3 = 7
,
GPIO_PINCFG104_NCESRC104_IOM2CE0 = 8
, GPIO_PINCFG104_NCESRC104_IOM2CE1 = 9
, GPIO_PINCFG104_NCESRC104_IOM2CE2 = 10
, GPIO_PINCFG104_NCESRC104_IOM2CE3 = 11
,
GPIO_PINCFG104_NCESRC104_IOM3CE0 = 12
, GPIO_PINCFG104_NCESRC104_IOM3CE1 = 13
, GPIO_PINCFG104_NCESRC104_IOM3CE2 = 14
, GPIO_PINCFG104_NCESRC104_IOM3CE3 = 15
,
GPIO_PINCFG104_NCESRC104_IOM4CE0 = 16
, GPIO_PINCFG104_NCESRC104_IOM4CE1 = 17
, GPIO_PINCFG104_NCESRC104_IOM4CE2 = 18
, GPIO_PINCFG104_NCESRC104_IOM4CE3 = 19
,
GPIO_PINCFG104_NCESRC104_IOM5CE0 = 20
, GPIO_PINCFG104_NCESRC104_IOM5CE1 = 21
, GPIO_PINCFG104_NCESRC104_IOM5CE2 = 22
, GPIO_PINCFG104_NCESRC104_IOM5CE3 = 23
,
GPIO_PINCFG104_NCESRC104_IOM6CE0 = 24
, GPIO_PINCFG104_NCESRC104_IOM6CE1 = 25
, GPIO_PINCFG104_NCESRC104_IOM6CE2 = 26
, GPIO_PINCFG104_NCESRC104_IOM6CE3 = 27
,
GPIO_PINCFG104_NCESRC104_IOM7CE0 = 28
, GPIO_PINCFG104_NCESRC104_IOM7CE1 = 29
, GPIO_PINCFG104_NCESRC104_IOM7CE2 = 30
, GPIO_PINCFG104_NCESRC104_IOM7CE3 = 31
,
GPIO_PINCFG104_NCESRC104_MSPI0CEN0 = 32
, GPIO_PINCFG104_NCESRC104_MSPI0CEN1 = 33
, GPIO_PINCFG104_NCESRC104_MSPI1CEN0 = 34
, GPIO_PINCFG104_NCESRC104_MSPI1CEN1 = 35
,
GPIO_PINCFG104_NCESRC104_MSPI2CEN0 = 36
, GPIO_PINCFG104_NCESRC104_MSPI2CEN1 = 37
, GPIO_PINCFG104_NCESRC104_DC_DPI_DE = 38
, GPIO_PINCFG104_NCESRC104_DISP_CONT_CSX = 39
,
GPIO_PINCFG104_NCESRC104_DC_SPI_CS_N = 40
, GPIO_PINCFG104_NCESRC104_DC_QSPI_CS_N = 41
, GPIO_PINCFG104_NCESRC104_DC_RESX = 42
} |
| |
| enum | GPIO_PINCFG104_PULLCFG104_Enum {
GPIO_PINCFG104_PULLCFG104_DIS = 0
, GPIO_PINCFG104_PULLCFG104_PD50K = 1
, GPIO_PINCFG104_PULLCFG104_PU15K = 2
, GPIO_PINCFG104_PULLCFG104_PU6K = 3
,
GPIO_PINCFG104_PULLCFG104_PU12K = 4
, GPIO_PINCFG104_PULLCFG104_PU24K = 5
, GPIO_PINCFG104_PULLCFG104_PU50K = 6
, GPIO_PINCFG104_PULLCFG104_PU100K = 7
} |
| |
| enum | GPIO_PINCFG104_DS104_Enum { GPIO_PINCFG104_DS104_0P1X = 0
, GPIO_PINCFG104_DS104_0P5X = 1
} |
| |
| enum | GPIO_PINCFG104_OUTCFG104_Enum { GPIO_PINCFG104_OUTCFG104_DIS = 0
, GPIO_PINCFG104_OUTCFG104_PUSHPULL = 1
, GPIO_PINCFG104_OUTCFG104_OD = 2
, GPIO_PINCFG104_OUTCFG104_TS = 3
} |
| |
| enum | GPIO_PINCFG104_IRPTEN104_Enum { GPIO_PINCFG104_IRPTEN104_DIS = 0
, GPIO_PINCFG104_IRPTEN104_INTFALL = 1
, GPIO_PINCFG104_IRPTEN104_INTRISE = 2
, GPIO_PINCFG104_IRPTEN104_INTANY = 3
} |
| |
| enum | GPIO_PINCFG104_FNCSEL104_Enum {
GPIO_PINCFG104_FNCSEL104_MSPI1_9 = 0
, GPIO_PINCFG104_FNCSEL104_RESERVED1 = 1
, GPIO_PINCFG104_FNCSEL104_RESERVED2 = 2
, GPIO_PINCFG104_FNCSEL104_GPIO = 3
,
GPIO_PINCFG104_FNCSEL104_RESERVED4 = 4
, GPIO_PINCFG104_FNCSEL104_RESERVED5 = 5
, GPIO_PINCFG104_FNCSEL104_CT104 = 6
, GPIO_PINCFG104_FNCSEL104_NCE104 = 7
,
GPIO_PINCFG104_FNCSEL104_OBSBUS8 = 8
, GPIO_PINCFG104_FNCSEL104_RESERVED9 = 9
, GPIO_PINCFG104_FNCSEL104_RESERVED10 = 10
, GPIO_PINCFG104_FNCSEL104_FPIO = 11
,
GPIO_PINCFG104_FNCSEL104_RESERVED12 = 12
, GPIO_PINCFG104_FNCSEL104_RESERVED13 = 13
, GPIO_PINCFG104_FNCSEL104_RESERVED14 = 14
, GPIO_PINCFG104_FNCSEL104_RESERVED15 = 15
} |
| |
| enum | GPIO_PINCFG105_OUTCFG105_Enum { GPIO_PINCFG105_OUTCFG105_DIS = 0
, GPIO_PINCFG105_OUTCFG105_PUSHPULL = 1
, GPIO_PINCFG105_OUTCFG105_OD = 2
, GPIO_PINCFG105_OUTCFG105_TS = 3
} |
| |
| enum | GPIO_PINCFG105_IRPTEN105_Enum { GPIO_PINCFG105_IRPTEN105_DIS = 0
, GPIO_PINCFG105_IRPTEN105_INTFALL = 1
, GPIO_PINCFG105_IRPTEN105_INTRISE = 2
, GPIO_PINCFG105_IRPTEN105_INTANY = 3
} |
| |
| enum | GPIO_PINCFG105_FNCSEL105_Enum {
GPIO_PINCFG105_FNCSEL105_RESERVED0 = 0
, GPIO_PINCFG105_FNCSEL105_RESERVED1 = 1
, GPIO_PINCFG105_FNCSEL105_RESERVED2 = 2
, GPIO_PINCFG105_FNCSEL105_GPIO = 3
,
GPIO_PINCFG105_FNCSEL105_RESERVED4 = 4
, GPIO_PINCFG105_FNCSEL105_RESERVED5 = 5
, GPIO_PINCFG105_FNCSEL105_CT105 = 6
, GPIO_PINCFG105_FNCSEL105_RESERVED7 = 7
,
GPIO_PINCFG105_FNCSEL105_OBSBUS9 = 8
, GPIO_PINCFG105_FNCSEL105_RESERVED9 = 9
, GPIO_PINCFG105_FNCSEL105_RESERVED10 = 10
, GPIO_PINCFG105_FNCSEL105_RESERVED11 = 11
,
GPIO_PINCFG105_FNCSEL105_RESERVED12 = 12
, GPIO_PINCFG105_FNCSEL105_RESERVED13 = 13
, GPIO_PINCFG105_FNCSEL105_RESERVED14 = 14
, GPIO_PINCFG105_FNCSEL105_RESERVED15 = 15
} |
| |
| enum | GPIO_PINCFG106_OUTCFG106_Enum { GPIO_PINCFG106_OUTCFG106_DIS = 0
, GPIO_PINCFG106_OUTCFG106_PUSHPULL = 1
, GPIO_PINCFG106_OUTCFG106_OD = 2
, GPIO_PINCFG106_OUTCFG106_TS = 3
} |
| |
| enum | GPIO_PINCFG106_IRPTEN106_Enum { GPIO_PINCFG106_IRPTEN106_DIS = 0
, GPIO_PINCFG106_IRPTEN106_INTFALL = 1
, GPIO_PINCFG106_IRPTEN106_INTRISE = 2
, GPIO_PINCFG106_IRPTEN106_INTANY = 3
} |
| |
| enum | GPIO_PINCFG106_FNCSEL106_Enum {
GPIO_PINCFG106_FNCSEL106_RESERVED0 = 0
, GPIO_PINCFG106_FNCSEL106_RESERVED1 = 1
, GPIO_PINCFG106_FNCSEL106_RESERVED2 = 2
, GPIO_PINCFG106_FNCSEL106_GPIO = 3
,
GPIO_PINCFG106_FNCSEL106_RESERVED4 = 4
, GPIO_PINCFG106_FNCSEL106_RESERVED5 = 5
, GPIO_PINCFG106_FNCSEL106_CT106 = 6
, GPIO_PINCFG106_FNCSEL106_RESERVED7 = 7
,
GPIO_PINCFG106_FNCSEL106_OBSBUS10 = 8
, GPIO_PINCFG106_FNCSEL106_RESERVED9 = 9
, GPIO_PINCFG106_FNCSEL106_RESERVED10 = 10
, GPIO_PINCFG106_FNCSEL106_RESERVED11 = 11
,
GPIO_PINCFG106_FNCSEL106_RESERVED12 = 12
, GPIO_PINCFG106_FNCSEL106_RESERVED13 = 13
, GPIO_PINCFG106_FNCSEL106_RESERVED14 = 14
, GPIO_PINCFG106_FNCSEL106_RESERVED15 = 15
} |
| |
| enum | GPIO_PINCFG107_OUTCFG107_Enum { GPIO_PINCFG107_OUTCFG107_DIS = 0
, GPIO_PINCFG107_OUTCFG107_PUSHPULL = 1
, GPIO_PINCFG107_OUTCFG107_OD = 2
, GPIO_PINCFG107_OUTCFG107_TS = 3
} |
| |
| enum | GPIO_PINCFG107_IRPTEN107_Enum { GPIO_PINCFG107_IRPTEN107_DIS = 0
, GPIO_PINCFG107_IRPTEN107_INTFALL = 1
, GPIO_PINCFG107_IRPTEN107_INTRISE = 2
, GPIO_PINCFG107_IRPTEN107_INTANY = 3
} |
| |
| enum | GPIO_PINCFG107_FNCSEL107_Enum {
GPIO_PINCFG107_FNCSEL107_RESERVED0 = 0
, GPIO_PINCFG107_FNCSEL107_RESERVED1 = 1
, GPIO_PINCFG107_FNCSEL107_RESERVED2 = 2
, GPIO_PINCFG107_FNCSEL107_GPIO = 3
,
GPIO_PINCFG107_FNCSEL107_RESERVED4 = 4
, GPIO_PINCFG107_FNCSEL107_RESERVED5 = 5
, GPIO_PINCFG107_FNCSEL107_CT107 = 6
, GPIO_PINCFG107_FNCSEL107_RESERVED7 = 7
,
GPIO_PINCFG107_FNCSEL107_OBSBUS11 = 8
, GPIO_PINCFG107_FNCSEL107_RESERVED9 = 9
, GPIO_PINCFG107_FNCSEL107_RESERVED10 = 10
, GPIO_PINCFG107_FNCSEL107_RESERVED11 = 11
,
GPIO_PINCFG107_FNCSEL107_RESERVED12 = 12
, GPIO_PINCFG107_FNCSEL107_RESERVED13 = 13
, GPIO_PINCFG107_FNCSEL107_RESERVED14 = 14
, GPIO_PINCFG107_FNCSEL107_RESERVED15 = 15
} |
| |
| enum | GPIO_PINCFG108_OUTCFG108_Enum { GPIO_PINCFG108_OUTCFG108_DIS = 0
, GPIO_PINCFG108_OUTCFG108_PUSHPULL = 1
, GPIO_PINCFG108_OUTCFG108_OD = 2
, GPIO_PINCFG108_OUTCFG108_TS = 3
} |
| |
| enum | GPIO_PINCFG108_IRPTEN108_Enum { GPIO_PINCFG108_IRPTEN108_DIS = 0
, GPIO_PINCFG108_IRPTEN108_INTFALL = 1
, GPIO_PINCFG108_IRPTEN108_INTRISE = 2
, GPIO_PINCFG108_IRPTEN108_INTANY = 3
} |
| |
| enum | GPIO_PINCFG108_FNCSEL108_Enum {
GPIO_PINCFG108_FNCSEL108_RESERVED0 = 0
, GPIO_PINCFG108_FNCSEL108_RESERVED1 = 1
, GPIO_PINCFG108_FNCSEL108_RESERVED2 = 2
, GPIO_PINCFG108_FNCSEL108_GPIO = 3
,
GPIO_PINCFG108_FNCSEL108_RESERVED4 = 4
, GPIO_PINCFG108_FNCSEL108_RESERVED5 = 5
, GPIO_PINCFG108_FNCSEL108_CT108 = 6
, GPIO_PINCFG108_FNCSEL108_RESERVED7 = 7
,
GPIO_PINCFG108_FNCSEL108_OBSBUS12 = 8
, GPIO_PINCFG108_FNCSEL108_RESERVED9 = 9
, GPIO_PINCFG108_FNCSEL108_RESERVED10 = 10
, GPIO_PINCFG108_FNCSEL108_RESERVED11 = 11
,
GPIO_PINCFG108_FNCSEL108_RESERVED12 = 12
, GPIO_PINCFG108_FNCSEL108_RESERVED13 = 13
, GPIO_PINCFG108_FNCSEL108_RESERVED14 = 14
, GPIO_PINCFG108_FNCSEL108_RESERVED15 = 15
} |
| |
| enum | GPIO_PINCFG109_OUTCFG109_Enum { GPIO_PINCFG109_OUTCFG109_DIS = 0
, GPIO_PINCFG109_OUTCFG109_PUSHPULL = 1
, GPIO_PINCFG109_OUTCFG109_OD = 2
, GPIO_PINCFG109_OUTCFG109_TS = 3
} |
| |
| enum | GPIO_PINCFG109_IRPTEN109_Enum { GPIO_PINCFG109_IRPTEN109_DIS = 0
, GPIO_PINCFG109_IRPTEN109_INTFALL = 1
, GPIO_PINCFG109_IRPTEN109_INTRISE = 2
, GPIO_PINCFG109_IRPTEN109_INTANY = 3
} |
| |
| enum | GPIO_PINCFG109_FNCSEL109_Enum {
GPIO_PINCFG109_FNCSEL109_RESERVED0 = 0
, GPIO_PINCFG109_FNCSEL109_RESERVED1 = 1
, GPIO_PINCFG109_FNCSEL109_RESERVED2 = 2
, GPIO_PINCFG109_FNCSEL109_GPIO = 3
,
GPIO_PINCFG109_FNCSEL109_RESERVED4 = 4
, GPIO_PINCFG109_FNCSEL109_RESERVED5 = 5
, GPIO_PINCFG109_FNCSEL109_CT109 = 6
, GPIO_PINCFG109_FNCSEL109_RESERVED7 = 7
,
GPIO_PINCFG109_FNCSEL109_OBSBUS13 = 8
, GPIO_PINCFG109_FNCSEL109_RESERVED9 = 9
, GPIO_PINCFG109_FNCSEL109_RESERVED10 = 10
, GPIO_PINCFG109_FNCSEL109_RESERVED11 = 11
,
GPIO_PINCFG109_FNCSEL109_RESERVED12 = 12
, GPIO_PINCFG109_FNCSEL109_RESERVED13 = 13
, GPIO_PINCFG109_FNCSEL109_RESERVED14 = 14
, GPIO_PINCFG109_FNCSEL109_RESERVED15 = 15
} |
| |
| enum | GPIO_PINCFG110_OUTCFG110_Enum { GPIO_PINCFG110_OUTCFG110_DIS = 0
, GPIO_PINCFG110_OUTCFG110_PUSHPULL = 1
, GPIO_PINCFG110_OUTCFG110_OD = 2
, GPIO_PINCFG110_OUTCFG110_TS = 3
} |
| |
| enum | GPIO_PINCFG110_IRPTEN110_Enum { GPIO_PINCFG110_IRPTEN110_DIS = 0
, GPIO_PINCFG110_IRPTEN110_INTFALL = 1
, GPIO_PINCFG110_IRPTEN110_INTRISE = 2
, GPIO_PINCFG110_IRPTEN110_INTANY = 3
} |
| |
| enum | GPIO_PINCFG110_FNCSEL110_Enum {
GPIO_PINCFG110_FNCSEL110_RESERVED0 = 0
, GPIO_PINCFG110_FNCSEL110_RESERVED1 = 1
, GPIO_PINCFG110_FNCSEL110_RESERVED2 = 2
, GPIO_PINCFG110_FNCSEL110_GPIO = 3
,
GPIO_PINCFG110_FNCSEL110_RESERVED4 = 4
, GPIO_PINCFG110_FNCSEL110_RESERVED5 = 5
, GPIO_PINCFG110_FNCSEL110_CT110 = 6
, GPIO_PINCFG110_FNCSEL110_RESERVED7 = 7
,
GPIO_PINCFG110_FNCSEL110_OBSBUS14 = 8
, GPIO_PINCFG110_FNCSEL110_RESERVED9 = 9
, GPIO_PINCFG110_FNCSEL110_RESERVED10 = 10
, GPIO_PINCFG110_FNCSEL110_RESERVED11 = 11
,
GPIO_PINCFG110_FNCSEL110_RESERVED12 = 12
, GPIO_PINCFG110_FNCSEL110_RESERVED13 = 13
, GPIO_PINCFG110_FNCSEL110_RESERVED14 = 14
, GPIO_PINCFG110_FNCSEL110_RESERVED15 = 15
} |
| |
| enum | GPIO_PINCFG111_OUTCFG111_Enum { GPIO_PINCFG111_OUTCFG111_DIS = 0
, GPIO_PINCFG111_OUTCFG111_PUSHPULL = 1
, GPIO_PINCFG111_OUTCFG111_OD = 2
, GPIO_PINCFG111_OUTCFG111_TS = 3
} |
| |
| enum | GPIO_PINCFG111_IRPTEN111_Enum { GPIO_PINCFG111_IRPTEN111_DIS = 0
, GPIO_PINCFG111_IRPTEN111_INTFALL = 1
, GPIO_PINCFG111_IRPTEN111_INTRISE = 2
, GPIO_PINCFG111_IRPTEN111_INTANY = 3
} |
| |
| enum | GPIO_PINCFG111_FNCSEL111_Enum {
GPIO_PINCFG111_FNCSEL111_RESERVED0 = 0
, GPIO_PINCFG111_FNCSEL111_RESERVED1 = 1
, GPIO_PINCFG111_FNCSEL111_RESERVED2 = 2
, GPIO_PINCFG111_FNCSEL111_GPIO = 3
,
GPIO_PINCFG111_FNCSEL111_RESERVED4 = 4
, GPIO_PINCFG111_FNCSEL111_RESERVED5 = 5
, GPIO_PINCFG111_FNCSEL111_CT111 = 6
, GPIO_PINCFG111_FNCSEL111_RESERVED7 = 7
,
GPIO_PINCFG111_FNCSEL111_OBSBUS15 = 8
, GPIO_PINCFG111_FNCSEL111_RESERVED9 = 9
, GPIO_PINCFG111_FNCSEL111_RESERVED10 = 10
, GPIO_PINCFG111_FNCSEL111_RESERVED11 = 11
,
GPIO_PINCFG111_FNCSEL111_RESERVED12 = 12
, GPIO_PINCFG111_FNCSEL111_RESERVED13 = 13
, GPIO_PINCFG111_FNCSEL111_RESERVED14 = 14
, GPIO_PINCFG111_FNCSEL111_RESERVED15 = 15
} |
| |
| enum | GPIO_PINCFG112_OUTCFG112_Enum { GPIO_PINCFG112_OUTCFG112_DIS = 0
, GPIO_PINCFG112_OUTCFG112_PUSHPULL = 1
, GPIO_PINCFG112_OUTCFG112_OD = 2
, GPIO_PINCFG112_OUTCFG112_TS = 3
} |
| |
| enum | GPIO_PINCFG112_IRPTEN112_Enum { GPIO_PINCFG112_IRPTEN112_DIS = 0
, GPIO_PINCFG112_IRPTEN112_INTFALL = 1
, GPIO_PINCFG112_IRPTEN112_INTRISE = 2
, GPIO_PINCFG112_IRPTEN112_INTANY = 3
} |
| |
| enum | GPIO_PINCFG112_FNCSEL112_Enum {
GPIO_PINCFG112_FNCSEL112_RESERVED0 = 0
, GPIO_PINCFG112_FNCSEL112_RESERVED1 = 1
, GPIO_PINCFG112_FNCSEL112_RESERVED2 = 2
, GPIO_PINCFG112_FNCSEL112_GPIO = 3
,
GPIO_PINCFG112_FNCSEL112_RESERVED4 = 4
, GPIO_PINCFG112_FNCSEL112_RESERVED5 = 5
, GPIO_PINCFG112_FNCSEL112_CT112 = 6
, GPIO_PINCFG112_FNCSEL112_RESERVED7 = 7
,
GPIO_PINCFG112_FNCSEL112_OBSBUS0 = 8
, GPIO_PINCFG112_FNCSEL112_RESERVED9 = 9
, GPIO_PINCFG112_FNCSEL112_RESERVED10 = 10
, GPIO_PINCFG112_FNCSEL112_RESERVED11 = 11
,
GPIO_PINCFG112_FNCSEL112_RESERVED12 = 12
, GPIO_PINCFG112_FNCSEL112_RESERVED13 = 13
, GPIO_PINCFG112_FNCSEL112_RESERVED14 = 14
, GPIO_PINCFG112_FNCSEL112_RESERVED15 = 15
} |
| |
| enum | GPIO_PINCFG113_OUTCFG113_Enum { GPIO_PINCFG113_OUTCFG113_DIS = 0
, GPIO_PINCFG113_OUTCFG113_PUSHPULL = 1
, GPIO_PINCFG113_OUTCFG113_OD = 2
, GPIO_PINCFG113_OUTCFG113_TS = 3
} |
| |
| enum | GPIO_PINCFG113_IRPTEN113_Enum { GPIO_PINCFG113_IRPTEN113_DIS = 0
, GPIO_PINCFG113_IRPTEN113_INTFALL = 1
, GPIO_PINCFG113_IRPTEN113_INTRISE = 2
, GPIO_PINCFG113_IRPTEN113_INTANY = 3
} |
| |
| enum | GPIO_PINCFG113_FNCSEL113_Enum {
GPIO_PINCFG113_FNCSEL113_RESERVED0 = 0
, GPIO_PINCFG113_FNCSEL113_RESERVED1 = 1
, GPIO_PINCFG113_FNCSEL113_RESERVED2 = 2
, GPIO_PINCFG113_FNCSEL113_GPIO = 3
,
GPIO_PINCFG113_FNCSEL113_RESERVED4 = 4
, GPIO_PINCFG113_FNCSEL113_RESERVED5 = 5
, GPIO_PINCFG113_FNCSEL113_CT113 = 6
, GPIO_PINCFG113_FNCSEL113_RESERVED7 = 7
,
GPIO_PINCFG113_FNCSEL113_OBSBUS1 = 8
, GPIO_PINCFG113_FNCSEL113_RESERVED9 = 9
, GPIO_PINCFG113_FNCSEL113_RESERVED10 = 10
, GPIO_PINCFG113_FNCSEL113_RESERVED11 = 11
,
GPIO_PINCFG113_FNCSEL113_RESERVED12 = 12
, GPIO_PINCFG113_FNCSEL113_RESERVED13 = 13
, GPIO_PINCFG113_FNCSEL113_RESERVED14 = 14
, GPIO_PINCFG113_FNCSEL113_RESERVED15 = 15
} |
| |
| enum | GPIO_PINCFG114_OUTCFG114_Enum { GPIO_PINCFG114_OUTCFG114_DIS = 0
, GPIO_PINCFG114_OUTCFG114_PUSHPULL = 1
, GPIO_PINCFG114_OUTCFG114_OD = 2
, GPIO_PINCFG114_OUTCFG114_TS = 3
} |
| |
| enum | GPIO_PINCFG114_IRPTEN114_Enum { GPIO_PINCFG114_IRPTEN114_DIS = 0
, GPIO_PINCFG114_IRPTEN114_INTFALL = 1
, GPIO_PINCFG114_IRPTEN114_INTRISE = 2
, GPIO_PINCFG114_IRPTEN114_INTANY = 3
} |
| |
| enum | GPIO_PINCFG114_FNCSEL114_Enum {
GPIO_PINCFG114_FNCSEL114_RESERVED0 = 0
, GPIO_PINCFG114_FNCSEL114_RESERVED1 = 1
, GPIO_PINCFG114_FNCSEL114_RESERVED2 = 2
, GPIO_PINCFG114_FNCSEL114_GPIO = 3
,
GPIO_PINCFG114_FNCSEL114_RESERVED4 = 4
, GPIO_PINCFG114_FNCSEL114_RESERVED5 = 5
, GPIO_PINCFG114_FNCSEL114_CT114 = 6
, GPIO_PINCFG114_FNCSEL114_RESERVED7 = 7
,
GPIO_PINCFG114_FNCSEL114_OBSBUS2 = 8
, GPIO_PINCFG114_FNCSEL114_RESERVED9 = 9
, GPIO_PINCFG114_FNCSEL114_RESERVED10 = 10
, GPIO_PINCFG114_FNCSEL114_RESERVED11 = 11
,
GPIO_PINCFG114_FNCSEL114_RESERVED12 = 12
, GPIO_PINCFG114_FNCSEL114_RESERVED13 = 13
, GPIO_PINCFG114_FNCSEL114_RESERVED14 = 14
, GPIO_PINCFG114_FNCSEL114_RESERVED15 = 15
} |
| |
| enum | GPIO_PINCFG115_OUTCFG115_Enum { GPIO_PINCFG115_OUTCFG115_DIS = 0
, GPIO_PINCFG115_OUTCFG115_PUSHPULL = 1
, GPIO_PINCFG115_OUTCFG115_OD = 2
, GPIO_PINCFG115_OUTCFG115_TS = 3
} |
| |
| enum | GPIO_PINCFG115_IRPTEN115_Enum { GPIO_PINCFG115_IRPTEN115_DIS = 0
, GPIO_PINCFG115_IRPTEN115_INTFALL = 1
, GPIO_PINCFG115_IRPTEN115_INTRISE = 2
, GPIO_PINCFG115_IRPTEN115_INTANY = 3
} |
| |
| enum | GPIO_PINCFG115_FNCSEL115_Enum {
GPIO_PINCFG115_FNCSEL115_RESERVED0 = 0
, GPIO_PINCFG115_FNCSEL115_RESERVED1 = 1
, GPIO_PINCFG115_FNCSEL115_RESERVED2 = 2
, GPIO_PINCFG115_FNCSEL115_GPIO = 3
,
GPIO_PINCFG115_FNCSEL115_RESERVED4 = 4
, GPIO_PINCFG115_FNCSEL115_RESERVED5 = 5
, GPIO_PINCFG115_FNCSEL115_CT115 = 6
, GPIO_PINCFG115_FNCSEL115_RESERVED7 = 7
,
GPIO_PINCFG115_FNCSEL115_OBSBUS3 = 8
, GPIO_PINCFG115_FNCSEL115_RESERVED9 = 9
, GPIO_PINCFG115_FNCSEL115_RESERVED10 = 10
, GPIO_PINCFG115_FNCSEL115_RESERVED11 = 11
,
GPIO_PINCFG115_FNCSEL115_RESERVED12 = 12
, GPIO_PINCFG115_FNCSEL115_RESERVED13 = 13
, GPIO_PINCFG115_FNCSEL115_RESERVED14 = 14
, GPIO_PINCFG115_FNCSEL115_RESERVED15 = 15
} |
| |
| enum | GPIO_PINCFG116_OUTCFG116_Enum { GPIO_PINCFG116_OUTCFG116_DIS = 0
, GPIO_PINCFG116_OUTCFG116_PUSHPULL = 1
, GPIO_PINCFG116_OUTCFG116_OD = 2
, GPIO_PINCFG116_OUTCFG116_TS = 3
} |
| |
| enum | GPIO_PINCFG116_IRPTEN116_Enum { GPIO_PINCFG116_IRPTEN116_DIS = 0
, GPIO_PINCFG116_IRPTEN116_INTFALL = 1
, GPIO_PINCFG116_IRPTEN116_INTRISE = 2
, GPIO_PINCFG116_IRPTEN116_INTANY = 3
} |
| |
| enum | GPIO_PINCFG116_FNCSEL116_Enum {
GPIO_PINCFG116_FNCSEL116_RESERVED0 = 0
, GPIO_PINCFG116_FNCSEL116_RESERVED1 = 1
, GPIO_PINCFG116_FNCSEL116_RESERVED2 = 2
, GPIO_PINCFG116_FNCSEL116_GPIO = 3
,
GPIO_PINCFG116_FNCSEL116_RESERVED4 = 4
, GPIO_PINCFG116_FNCSEL116_RESERVED5 = 5
, GPIO_PINCFG116_FNCSEL116_CT116 = 6
, GPIO_PINCFG116_FNCSEL116_RESERVED7 = 7
,
GPIO_PINCFG116_FNCSEL116_OBSBUS4 = 8
, GPIO_PINCFG116_FNCSEL116_RESERVED9 = 9
, GPIO_PINCFG116_FNCSEL116_RESERVED10 = 10
, GPIO_PINCFG116_FNCSEL116_RESERVED11 = 11
,
GPIO_PINCFG116_FNCSEL116_RESERVED12 = 12
, GPIO_PINCFG116_FNCSEL116_RESERVED13 = 13
, GPIO_PINCFG116_FNCSEL116_RESERVED14 = 14
, GPIO_PINCFG116_FNCSEL116_RESERVED15 = 15
} |
| |
| enum | GPIO_PINCFG117_OUTCFG117_Enum { GPIO_PINCFG117_OUTCFG117_DIS = 0
, GPIO_PINCFG117_OUTCFG117_PUSHPULL = 1
, GPIO_PINCFG117_OUTCFG117_OD = 2
, GPIO_PINCFG117_OUTCFG117_TS = 3
} |
| |
| enum | GPIO_PINCFG117_IRPTEN117_Enum { GPIO_PINCFG117_IRPTEN117_DIS = 0
, GPIO_PINCFG117_IRPTEN117_INTFALL = 1
, GPIO_PINCFG117_IRPTEN117_INTRISE = 2
, GPIO_PINCFG117_IRPTEN117_INTANY = 3
} |
| |
| enum | GPIO_PINCFG117_FNCSEL117_Enum {
GPIO_PINCFG117_FNCSEL117_RESERVED0 = 0
, GPIO_PINCFG117_FNCSEL117_RESERVED1 = 1
, GPIO_PINCFG117_FNCSEL117_RESERVED2 = 2
, GPIO_PINCFG117_FNCSEL117_GPIO = 3
,
GPIO_PINCFG117_FNCSEL117_RESERVED4 = 4
, GPIO_PINCFG117_FNCSEL117_RESERVED5 = 5
, GPIO_PINCFG117_FNCSEL117_CT117 = 6
, GPIO_PINCFG117_FNCSEL117_RESERVED7 = 7
,
GPIO_PINCFG117_FNCSEL117_OBSBUS5 = 8
, GPIO_PINCFG117_FNCSEL117_RESERVED9 = 9
, GPIO_PINCFG117_FNCSEL117_RESERVED10 = 10
, GPIO_PINCFG117_FNCSEL117_RESERVED11 = 11
,
GPIO_PINCFG117_FNCSEL117_RESERVED12 = 12
, GPIO_PINCFG117_FNCSEL117_RESERVED13 = 13
, GPIO_PINCFG117_FNCSEL117_RESERVED14 = 14
, GPIO_PINCFG117_FNCSEL117_RESERVED15 = 15
} |
| |
| enum | GPIO_PINCFG118_OUTCFG118_Enum { GPIO_PINCFG118_OUTCFG118_DIS = 0
, GPIO_PINCFG118_OUTCFG118_PUSHPULL = 1
, GPIO_PINCFG118_OUTCFG118_OD = 2
, GPIO_PINCFG118_OUTCFG118_TS = 3
} |
| |
| enum | GPIO_PINCFG118_IRPTEN118_Enum { GPIO_PINCFG118_IRPTEN118_DIS = 0
, GPIO_PINCFG118_IRPTEN118_INTFALL = 1
, GPIO_PINCFG118_IRPTEN118_INTRISE = 2
, GPIO_PINCFG118_IRPTEN118_INTANY = 3
} |
| |
| enum | GPIO_PINCFG118_FNCSEL118_Enum {
GPIO_PINCFG118_FNCSEL118_RESERVED0 = 0
, GPIO_PINCFG118_FNCSEL118_RESERVED1 = 1
, GPIO_PINCFG118_FNCSEL118_RESERVED2 = 2
, GPIO_PINCFG118_FNCSEL118_GPIO = 3
,
GPIO_PINCFG118_FNCSEL118_RESERVED4 = 4
, GPIO_PINCFG118_FNCSEL118_RESERVED5 = 5
, GPIO_PINCFG118_FNCSEL118_CT118 = 6
, GPIO_PINCFG118_FNCSEL118_RESERVED7 = 7
,
GPIO_PINCFG118_FNCSEL118_OBSBUS6 = 8
, GPIO_PINCFG118_FNCSEL118_RESERVED9 = 9
, GPIO_PINCFG118_FNCSEL118_RESERVED10 = 10
, GPIO_PINCFG118_FNCSEL118_RESERVED11 = 11
,
GPIO_PINCFG118_FNCSEL118_RESERVED12 = 12
, GPIO_PINCFG118_FNCSEL118_RESERVED13 = 13
, GPIO_PINCFG118_FNCSEL118_RESERVED14 = 14
, GPIO_PINCFG118_FNCSEL118_RESERVED15 = 15
} |
| |
| enum | GPIO_PINCFG119_OUTCFG119_Enum { GPIO_PINCFG119_OUTCFG119_DIS = 0
, GPIO_PINCFG119_OUTCFG119_PUSHPULL = 1
, GPIO_PINCFG119_OUTCFG119_OD = 2
, GPIO_PINCFG119_OUTCFG119_TS = 3
} |
| |
| enum | GPIO_PINCFG119_IRPTEN119_Enum { GPIO_PINCFG119_IRPTEN119_DIS = 0
, GPIO_PINCFG119_IRPTEN119_INTFALL = 1
, GPIO_PINCFG119_IRPTEN119_INTRISE = 2
, GPIO_PINCFG119_IRPTEN119_INTANY = 3
} |
| |
| enum | GPIO_PINCFG119_FNCSEL119_Enum {
GPIO_PINCFG119_FNCSEL119_RESERVED0 = 0
, GPIO_PINCFG119_FNCSEL119_RESERVED1 = 1
, GPIO_PINCFG119_FNCSEL119_RESERVED2 = 2
, GPIO_PINCFG119_FNCSEL119_GPIO = 3
,
GPIO_PINCFG119_FNCSEL119_RESERVED4 = 4
, GPIO_PINCFG119_FNCSEL119_RESERVED5 = 5
, GPIO_PINCFG119_FNCSEL119_CT119 = 6
, GPIO_PINCFG119_FNCSEL119_RESERVED7 = 7
,
GPIO_PINCFG119_FNCSEL119_OBSBUS7 = 8
, GPIO_PINCFG119_FNCSEL119_RESERVED9 = 9
, GPIO_PINCFG119_FNCSEL119_RESERVED10 = 10
, GPIO_PINCFG119_FNCSEL119_RESERVED11 = 11
,
GPIO_PINCFG119_FNCSEL119_RESERVED12 = 12
, GPIO_PINCFG119_FNCSEL119_RESERVED13 = 13
, GPIO_PINCFG119_FNCSEL119_RESERVED14 = 14
, GPIO_PINCFG119_FNCSEL119_RESERVED15 = 15
} |
| |
| enum | GPIO_PINCFG120_OUTCFG120_Enum { GPIO_PINCFG120_OUTCFG120_DIS = 0
, GPIO_PINCFG120_OUTCFG120_PUSHPULL = 1
, GPIO_PINCFG120_OUTCFG120_OD = 2
, GPIO_PINCFG120_OUTCFG120_TS = 3
} |
| |
| enum | GPIO_PINCFG120_IRPTEN120_Enum { GPIO_PINCFG120_IRPTEN120_DIS = 0
, GPIO_PINCFG120_IRPTEN120_INTFALL = 1
, GPIO_PINCFG120_IRPTEN120_INTRISE = 2
, GPIO_PINCFG120_IRPTEN120_INTANY = 3
} |
| |
| enum | GPIO_PINCFG120_FNCSEL120_Enum {
GPIO_PINCFG120_FNCSEL120_RESERVED0 = 0
, GPIO_PINCFG120_FNCSEL120_RESERVED1 = 1
, GPIO_PINCFG120_FNCSEL120_RESERVED2 = 2
, GPIO_PINCFG120_FNCSEL120_GPIO = 3
,
GPIO_PINCFG120_FNCSEL120_RESERVED4 = 4
, GPIO_PINCFG120_FNCSEL120_RESERVED5 = 5
, GPIO_PINCFG120_FNCSEL120_CT120 = 6
, GPIO_PINCFG120_FNCSEL120_RESERVED7 = 7
,
GPIO_PINCFG120_FNCSEL120_OBSBUS8 = 8
, GPIO_PINCFG120_FNCSEL120_RESERVED9 = 9
, GPIO_PINCFG120_FNCSEL120_RESERVED10 = 10
, GPIO_PINCFG120_FNCSEL120_RESERVED11 = 11
,
GPIO_PINCFG120_FNCSEL120_RESERVED12 = 12
, GPIO_PINCFG120_FNCSEL120_RESERVED13 = 13
, GPIO_PINCFG120_FNCSEL120_RESERVED14 = 14
, GPIO_PINCFG120_FNCSEL120_RESERVED15 = 15
} |
| |
| enum | GPIO_PINCFG121_OUTCFG121_Enum { GPIO_PINCFG121_OUTCFG121_DIS = 0
, GPIO_PINCFG121_OUTCFG121_PUSHPULL = 1
, GPIO_PINCFG121_OUTCFG121_OD = 2
, GPIO_PINCFG121_OUTCFG121_TS = 3
} |
| |
| enum | GPIO_PINCFG121_IRPTEN121_Enum { GPIO_PINCFG121_IRPTEN121_DIS = 0
, GPIO_PINCFG121_IRPTEN121_INTFALL = 1
, GPIO_PINCFG121_IRPTEN121_INTRISE = 2
, GPIO_PINCFG121_IRPTEN121_INTANY = 3
} |
| |
| enum | GPIO_PINCFG121_FNCSEL121_Enum {
GPIO_PINCFG121_FNCSEL121_RESERVED0 = 0
, GPIO_PINCFG121_FNCSEL121_RESERVED1 = 1
, GPIO_PINCFG121_FNCSEL121_RESERVED2 = 2
, GPIO_PINCFG121_FNCSEL121_GPIO = 3
,
GPIO_PINCFG121_FNCSEL121_RESERVED4 = 4
, GPIO_PINCFG121_FNCSEL121_RESERVED5 = 5
, GPIO_PINCFG121_FNCSEL121_CT121 = 6
, GPIO_PINCFG121_FNCSEL121_RESERVED7 = 7
,
GPIO_PINCFG121_FNCSEL121_OBSBUS9 = 8
, GPIO_PINCFG121_FNCSEL121_RESERVED9 = 9
, GPIO_PINCFG121_FNCSEL121_RESERVED10 = 10
, GPIO_PINCFG121_FNCSEL121_RESERVED11 = 11
,
GPIO_PINCFG121_FNCSEL121_RESERVED12 = 12
, GPIO_PINCFG121_FNCSEL121_RESERVED13 = 13
, GPIO_PINCFG121_FNCSEL121_RESERVED14 = 14
, GPIO_PINCFG121_FNCSEL121_RESERVED15 = 15
} |
| |
| enum | GPIO_PINCFG122_OUTCFG122_Enum { GPIO_PINCFG122_OUTCFG122_DIS = 0
, GPIO_PINCFG122_OUTCFG122_PUSHPULL = 1
, GPIO_PINCFG122_OUTCFG122_OD = 2
, GPIO_PINCFG122_OUTCFG122_TS = 3
} |
| |
| enum | GPIO_PINCFG122_IRPTEN122_Enum { GPIO_PINCFG122_IRPTEN122_DIS = 0
, GPIO_PINCFG122_IRPTEN122_INTFALL = 1
, GPIO_PINCFG122_IRPTEN122_INTRISE = 2
, GPIO_PINCFG122_IRPTEN122_INTANY = 3
} |
| |
| enum | GPIO_PINCFG122_FNCSEL122_Enum {
GPIO_PINCFG122_FNCSEL122_RESERVED0 = 0
, GPIO_PINCFG122_FNCSEL122_RESERVED1 = 1
, GPIO_PINCFG122_FNCSEL122_RESERVED2 = 2
, GPIO_PINCFG122_FNCSEL122_GPIO = 3
,
GPIO_PINCFG122_FNCSEL122_RESERVED4 = 4
, GPIO_PINCFG122_FNCSEL122_RESERVED5 = 5
, GPIO_PINCFG122_FNCSEL122_CT122 = 6
, GPIO_PINCFG122_FNCSEL122_RESERVED7 = 7
,
GPIO_PINCFG122_FNCSEL122_OBSBUS10 = 8
, GPIO_PINCFG122_FNCSEL122_RESERVED9 = 9
, GPIO_PINCFG122_FNCSEL122_RESERVED10 = 10
, GPIO_PINCFG122_FNCSEL122_RESERVED11 = 11
,
GPIO_PINCFG122_FNCSEL122_RESERVED12 = 12
, GPIO_PINCFG122_FNCSEL122_RESERVED13 = 13
, GPIO_PINCFG122_FNCSEL122_RESERVED14 = 14
, GPIO_PINCFG122_FNCSEL122_RESERVED15 = 15
} |
| |
| enum | GPIO_PINCFG123_OUTCFG123_Enum { GPIO_PINCFG123_OUTCFG123_DIS = 0
, GPIO_PINCFG123_OUTCFG123_PUSHPULL = 1
, GPIO_PINCFG123_OUTCFG123_OD = 2
, GPIO_PINCFG123_OUTCFG123_TS = 3
} |
| |
| enum | GPIO_PINCFG123_IRPTEN123_Enum { GPIO_PINCFG123_IRPTEN123_DIS = 0
, GPIO_PINCFG123_IRPTEN123_INTFALL = 1
, GPIO_PINCFG123_IRPTEN123_INTRISE = 2
, GPIO_PINCFG123_IRPTEN123_INTANY = 3
} |
| |
| enum | GPIO_PINCFG123_FNCSEL123_Enum {
GPIO_PINCFG123_FNCSEL123_RESERVED0 = 0
, GPIO_PINCFG123_FNCSEL123_RESERVED1 = 1
, GPIO_PINCFG123_FNCSEL123_RESERVED2 = 2
, GPIO_PINCFG123_FNCSEL123_GPIO = 3
,
GPIO_PINCFG123_FNCSEL123_RESERVED4 = 4
, GPIO_PINCFG123_FNCSEL123_RESERVED5 = 5
, GPIO_PINCFG123_FNCSEL123_CT123 = 6
, GPIO_PINCFG123_FNCSEL123_RESERVED7 = 7
,
GPIO_PINCFG123_FNCSEL123_OBSBUS11 = 8
, GPIO_PINCFG123_FNCSEL123_RESERVED9 = 9
, GPIO_PINCFG123_FNCSEL123_RESERVED10 = 10
, GPIO_PINCFG123_FNCSEL123_RESERVED11 = 11
,
GPIO_PINCFG123_FNCSEL123_RESERVED12 = 12
, GPIO_PINCFG123_FNCSEL123_RESERVED13 = 13
, GPIO_PINCFG123_FNCSEL123_RESERVED14 = 14
, GPIO_PINCFG123_FNCSEL123_RESERVED15 = 15
} |
| |
| enum | GPIO_PINCFG124_OUTCFG124_Enum { GPIO_PINCFG124_OUTCFG124_DIS = 0
, GPIO_PINCFG124_OUTCFG124_PUSHPULL = 1
, GPIO_PINCFG124_OUTCFG124_OD = 2
, GPIO_PINCFG124_OUTCFG124_TS = 3
} |
| |
| enum | GPIO_PINCFG124_IRPTEN124_Enum { GPIO_PINCFG124_IRPTEN124_DIS = 0
, GPIO_PINCFG124_IRPTEN124_INTFALL = 1
, GPIO_PINCFG124_IRPTEN124_INTRISE = 2
, GPIO_PINCFG124_IRPTEN124_INTANY = 3
} |
| |
| enum | GPIO_PINCFG124_FNCSEL124_Enum {
GPIO_PINCFG124_FNCSEL124_RESERVED0 = 0
, GPIO_PINCFG124_FNCSEL124_RESERVED1 = 1
, GPIO_PINCFG124_FNCSEL124_RESERVED2 = 2
, GPIO_PINCFG124_FNCSEL124_GPIO = 3
,
GPIO_PINCFG124_FNCSEL124_RESERVED4 = 4
, GPIO_PINCFG124_FNCSEL124_RESERVED5 = 5
, GPIO_PINCFG124_FNCSEL124_CT124 = 6
, GPIO_PINCFG124_FNCSEL124_RESERVED7 = 7
,
GPIO_PINCFG124_FNCSEL124_OBSBUS12 = 8
, GPIO_PINCFG124_FNCSEL124_RESERVED9 = 9
, GPIO_PINCFG124_FNCSEL124_RESERVED10 = 10
, GPIO_PINCFG124_FNCSEL124_RESERVED11 = 11
,
GPIO_PINCFG124_FNCSEL124_RESERVED12 = 12
, GPIO_PINCFG124_FNCSEL124_RESERVED13 = 13
, GPIO_PINCFG124_FNCSEL124_RESERVED14 = 14
, GPIO_PINCFG124_FNCSEL124_RESERVED15 = 15
} |
| |
| enum | GPIO_PINCFG125_OUTCFG125_Enum { GPIO_PINCFG125_OUTCFG125_DIS = 0
, GPIO_PINCFG125_OUTCFG125_PUSHPULL = 1
, GPIO_PINCFG125_OUTCFG125_OD = 2
, GPIO_PINCFG125_OUTCFG125_TS = 3
} |
| |
| enum | GPIO_PINCFG125_IRPTEN125_Enum { GPIO_PINCFG125_IRPTEN125_DIS = 0
, GPIO_PINCFG125_IRPTEN125_INTFALL = 1
, GPIO_PINCFG125_IRPTEN125_INTRISE = 2
, GPIO_PINCFG125_IRPTEN125_INTANY = 3
} |
| |
| enum | GPIO_PINCFG125_FNCSEL125_Enum {
GPIO_PINCFG125_FNCSEL125_RESERVED0 = 0
, GPIO_PINCFG125_FNCSEL125_RESERVED1 = 1
, GPIO_PINCFG125_FNCSEL125_RESERVED2 = 2
, GPIO_PINCFG125_FNCSEL125_GPIO = 3
,
GPIO_PINCFG125_FNCSEL125_RESERVED4 = 4
, GPIO_PINCFG125_FNCSEL125_RESERVED5 = 5
, GPIO_PINCFG125_FNCSEL125_CT125 = 6
, GPIO_PINCFG125_FNCSEL125_RESERVED7 = 7
,
GPIO_PINCFG125_FNCSEL125_OBSBUS13 = 8
, GPIO_PINCFG125_FNCSEL125_RESERVED9 = 9
, GPIO_PINCFG125_FNCSEL125_RESERVED10 = 10
, GPIO_PINCFG125_FNCSEL125_RESERVED11 = 11
,
GPIO_PINCFG125_FNCSEL125_RESERVED12 = 12
, GPIO_PINCFG125_FNCSEL125_RESERVED13 = 13
, GPIO_PINCFG125_FNCSEL125_RESERVED14 = 14
, GPIO_PINCFG125_FNCSEL125_RESERVED15 = 15
} |
| |
| enum | GPIO_PINCFG126_OUTCFG126_Enum { GPIO_PINCFG126_OUTCFG126_DIS = 0
, GPIO_PINCFG126_OUTCFG126_PUSHPULL = 1
, GPIO_PINCFG126_OUTCFG126_OD = 2
, GPIO_PINCFG126_OUTCFG126_TS = 3
} |
| |
| enum | GPIO_PINCFG126_IRPTEN126_Enum { GPIO_PINCFG126_IRPTEN126_DIS = 0
, GPIO_PINCFG126_IRPTEN126_INTFALL = 1
, GPIO_PINCFG126_IRPTEN126_INTRISE = 2
, GPIO_PINCFG126_IRPTEN126_INTANY = 3
} |
| |
| enum | GPIO_PINCFG126_FNCSEL126_Enum {
GPIO_PINCFG126_FNCSEL126_RESERVED0 = 0
, GPIO_PINCFG126_FNCSEL126_RESERVED1 = 1
, GPIO_PINCFG126_FNCSEL126_RESERVED2 = 2
, GPIO_PINCFG126_FNCSEL126_GPIO = 3
,
GPIO_PINCFG126_FNCSEL126_RESERVED4 = 4
, GPIO_PINCFG126_FNCSEL126_RESERVED5 = 5
, GPIO_PINCFG126_FNCSEL126_CT126 = 6
, GPIO_PINCFG126_FNCSEL126_RESERVED7 = 7
,
GPIO_PINCFG126_FNCSEL126_OBSBUS14 = 8
, GPIO_PINCFG126_FNCSEL126_RESERVED9 = 9
, GPIO_PINCFG126_FNCSEL126_RESERVED10 = 10
, GPIO_PINCFG126_FNCSEL126_RESERVED11 = 11
,
GPIO_PINCFG126_FNCSEL126_RESERVED12 = 12
, GPIO_PINCFG126_FNCSEL126_RESERVED13 = 13
, GPIO_PINCFG126_FNCSEL126_RESERVED14 = 14
, GPIO_PINCFG126_FNCSEL126_RESERVED15 = 15
} |
| |
| enum | GPIO_PINCFG127_OUTCFG127_Enum { GPIO_PINCFG127_OUTCFG127_DIS = 0
, GPIO_PINCFG127_OUTCFG127_PUSHPULL = 1
, GPIO_PINCFG127_OUTCFG127_OD = 2
, GPIO_PINCFG127_OUTCFG127_TS = 3
} |
| |
| enum | GPIO_PINCFG127_IRPTEN127_Enum { GPIO_PINCFG127_IRPTEN127_DIS = 0
, GPIO_PINCFG127_IRPTEN127_INTFALL = 1
, GPIO_PINCFG127_IRPTEN127_INTRISE = 2
, GPIO_PINCFG127_IRPTEN127_INTANY = 3
} |
| |
| enum | GPIO_PINCFG127_FNCSEL127_Enum {
GPIO_PINCFG127_FNCSEL127_RESERVED0 = 0
, GPIO_PINCFG127_FNCSEL127_RESERVED1 = 1
, GPIO_PINCFG127_FNCSEL127_RESERVED2 = 2
, GPIO_PINCFG127_FNCSEL127_GPIO = 3
,
GPIO_PINCFG127_FNCSEL127_RESERVED4 = 4
, GPIO_PINCFG127_FNCSEL127_RESERVED5 = 5
, GPIO_PINCFG127_FNCSEL127_CT127 = 6
, GPIO_PINCFG127_FNCSEL127_RESERVED7 = 7
,
GPIO_PINCFG127_FNCSEL127_OBSBUS15 = 8
, GPIO_PINCFG127_FNCSEL127_RESERVED9 = 9
, GPIO_PINCFG127_FNCSEL127_RESERVED10 = 10
, GPIO_PINCFG127_FNCSEL127_RESERVED11 = 11
,
GPIO_PINCFG127_FNCSEL127_RESERVED12 = 12
, GPIO_PINCFG127_FNCSEL127_RESERVED13 = 13
, GPIO_PINCFG127_FNCSEL127_RESERVED14 = 14
, GPIO_PINCFG127_FNCSEL127_RESERVED15 = 15
} |
| |
| enum | GPIO_PADKEY_PADKEY_Enum { GPIO_PADKEY_PADKEY_Key = 115
} |
| |
| enum | GPU_TEX0STRIDE_IMGFMT_Enum {
GPU_TEX0STRIDE_IMGFMT_RGBX8888 = 0
, GPU_TEX0STRIDE_IMGFMT_RGBA8888 = 1
, GPU_TEX0STRIDE_IMGFMT_XRGB8888 = 2
, GPU_TEX0STRIDE_IMGFMT_ARGB8888 = 3
,
GPU_TEX0STRIDE_IMGFMT_RGBA565 = 4
, GPU_TEX0STRIDE_IMGFMT_RGBA5551 = 5
, GPU_TEX0STRIDE_IMGFMT_L8 = 9
, GPU_TEX0STRIDE_IMGFMT_TSC4 = 18
,
GPU_TEX0STRIDE_IMGFMT_TSC6 = 22
, GPU_TEX0STRIDE_IMGFMT_TSC6A = 23
} |
| |
| enum | GPU_TEX0STRIDE_IMGMODE_Enum { GPU_TEX0STRIDE_IMGMODE_POINTSAMPLE = 0
, GPU_TEX0STRIDE_IMGMODE_BILINEARFILTERING = 1
} |
| |
| enum | GPU_TEX1STRIDE_IMGFMT_Enum {
GPU_TEX1STRIDE_IMGFMT_RGBX8888 = 0
, GPU_TEX1STRIDE_IMGFMT_RGBA8888 = 1
, GPU_TEX1STRIDE_IMGFMT_XRGB8888 = 2
, GPU_TEX1STRIDE_IMGFMT_ARGB8888 = 3
,
GPU_TEX1STRIDE_IMGFMT_RGBA565 = 4
, GPU_TEX1STRIDE_IMGFMT_RGBA5551 = 5
, GPU_TEX1STRIDE_IMGFMT_L8 = 9
, GPU_TEX1STRIDE_IMGFMT_TSC4 = 18
,
GPU_TEX1STRIDE_IMGFMT_TSC6 = 22
, GPU_TEX1STRIDE_IMGFMT_TSC6A = 23
} |
| |
| enum | GPU_TEX1STRIDE_IMGMODE_Enum { GPU_TEX1STRIDE_IMGMODE_POINTSAMPLE = 0
, GPU_TEX1STRIDE_IMGMODE_BILINEARFILTERING = 1
} |
| |
| enum | GPU_TEX2STRIDE_IMGFMT_Enum {
GPU_TEX2STRIDE_IMGFMT_RGBX8888 = 0
, GPU_TEX2STRIDE_IMGFMT_RGBA8888 = 1
, GPU_TEX2STRIDE_IMGFMT_XRGB8888 = 2
, GPU_TEX2STRIDE_IMGFMT_ARGB8888 = 3
,
GPU_TEX2STRIDE_IMGFMT_RGBA565 = 4
, GPU_TEX2STRIDE_IMGFMT_RGBA5551 = 5
, GPU_TEX2STRIDE_IMGFMT_L8 = 9
, GPU_TEX2STRIDE_IMGFMT_TSC4 = 18
,
GPU_TEX2STRIDE_IMGFMT_TSC6 = 22
, GPU_TEX2STRIDE_IMGFMT_TSC6A = 23
} |
| |
| enum | GPU_TEX2STRIDE_IMGMODE_Enum { GPU_TEX2STRIDE_IMGMODE_POINTSAMPLE = 0
, GPU_TEX2STRIDE_IMGMODE_BILINEARFILTERING = 1
} |
| |
| enum | GPU_TEX3STRIDE_IMGFMT_Enum {
GPU_TEX3STRIDE_IMGFMT_RGBX8888 = 0
, GPU_TEX3STRIDE_IMGFMT_RGBA8888 = 1
, GPU_TEX3STRIDE_IMGFMT_XRGB8888 = 2
, GPU_TEX3STRIDE_IMGFMT_ARGB8888 = 3
,
GPU_TEX3STRIDE_IMGFMT_RGBA565 = 4
, GPU_TEX3STRIDE_IMGFMT_RGBA5551 = 5
, GPU_TEX3STRIDE_IMGFMT_L8 = 9
, GPU_TEX3STRIDE_IMGFMT_TSC4 = 18
,
GPU_TEX3STRIDE_IMGFMT_TSC6 = 22
, GPU_TEX3STRIDE_IMGFMT_TSC6A = 23
} |
| |
| enum | GPU_TEX3STRIDE_IMGMODE_Enum { GPU_TEX3STRIDE_IMGMODE_POINTSAMPLE = 0
, GPU_TEX3STRIDE_IMGMODE_BILINEARFILTERING = 1
} |
| |
| enum | GPU_DRAWCMD_START_Enum {
GPU_DRAWCMD_START_PIXEL = 0
, GPU_DRAWCMD_START_LINE = 1
, GPU_DRAWCMD_START_RECT = 2
, GPU_DRAWCMD_START_TRI = 3
,
GPU_DRAWCMD_START_QUAD = 4
} |
| |
| enum | I2S0_I2SDATACFG_FRLEN2_Enum {
I2S0_I2SDATACFG_FRLEN2_1CHLS = 0
, I2S0_I2SDATACFG_FRLEN2_2CHLS = 1
, I2S0_I2SDATACFG_FRLEN2_3CHLS = 2
, I2S0_I2SDATACFG_FRLEN2_4CHLS = 3
,
I2S0_I2SDATACFG_FRLEN2_5CHLS = 4
, I2S0_I2SDATACFG_FRLEN2_6CHLS = 5
, I2S0_I2SDATACFG_FRLEN2_7CHLS = 6
, I2S0_I2SDATACFG_FRLEN2_8CHLS = 7
} |
| |
| enum | I2S0_I2SDATACFG_WDLEN2_Enum { I2S0_I2SDATACFG_WDLEN2_8b = 0
, I2S0_I2SDATACFG_WDLEN2_16b = 2
, I2S0_I2SDATACFG_WDLEN2_24b = 4
, I2S0_I2SDATACFG_WDLEN2_32b = 5
} |
| |
| enum | I2S0_I2SDATACFG_SSZ2_Enum { I2S0_I2SDATACFG_SSZ2_8b = 0
, I2S0_I2SDATACFG_SSZ2_16b = 2
, I2S0_I2SDATACFG_SSZ2_24b = 4
, I2S0_I2SDATACFG_SSZ2_32b = 5
} |
| |
| enum | I2S0_I2SDATACFG_FRLEN1_Enum {
I2S0_I2SDATACFG_FRLEN1_1CHLS = 0
, I2S0_I2SDATACFG_FRLEN1_2CHLS = 1
, I2S0_I2SDATACFG_FRLEN1_3CHLS = 2
, I2S0_I2SDATACFG_FRLEN1_4CHLS = 3
,
I2S0_I2SDATACFG_FRLEN1_5CHLS = 4
, I2S0_I2SDATACFG_FRLEN1_6CHLS = 5
, I2S0_I2SDATACFG_FRLEN1_7CHLS = 6
, I2S0_I2SDATACFG_FRLEN1_8CHLS = 7
} |
| |
| enum | I2S0_I2SDATACFG_WDLEN1_Enum { I2S0_I2SDATACFG_WDLEN1_8b = 0
, I2S0_I2SDATACFG_WDLEN1_16b = 2
, I2S0_I2SDATACFG_WDLEN1_24b = 4
, I2S0_I2SDATACFG_WDLEN1_32b = 5
} |
| |
| enum | I2S0_I2SDATACFG_SSZ1_Enum { I2S0_I2SDATACFG_SSZ1_8b = 0
, I2S0_I2SDATACFG_SSZ1_16b = 2
, I2S0_I2SDATACFG_SSZ1_24b = 4
, I2S0_I2SDATACFG_SSZ1_32b = 5
} |
| |
| enum | I2S0_DMACFG_TXDMAPRI_Enum { I2S0_DMACFG_TXDMAPRI_LOW = 0
, I2S0_DMACFG_TXDMAPRI_HIGH = 1
} |
| |
| enum | I2S0_DMACFG_TXDMAEN_Enum { I2S0_DMACFG_TXDMAEN_DIS = 0
, I2S0_DMACFG_TXDMAEN_EN = 1
} |
| |
| enum | I2S0_DMACFG_RXDMAPRI_Enum { I2S0_DMACFG_RXDMAPRI_LOW = 0
, I2S0_DMACFG_RXDMAPRI_HIGH = 1
} |
| |
| enum | I2S0_DMACFG_RXDMAEN_Enum { I2S0_DMACFG_RXDMAEN_DIS = 0
, I2S0_DMACFG_RXDMAEN_EN = 1
} |
| |
| enum | IOM0_CLKCFG_DIVEN_Enum { IOM0_CLKCFG_DIVEN_DIS = 0
, IOM0_CLKCFG_DIVEN_EN = 1
} |
| |
| enum | IOM0_CLKCFG_DIV3_Enum { IOM0_CLKCFG_DIV3_DIS = 0
, IOM0_CLKCFG_DIV3_EN = 1
} |
| |
| enum | IOM0_CLKCFG_FSEL_Enum {
IOM0_CLKCFG_FSEL_MIN_PWR = 0
, IOM0_CLKCFG_FSEL_OFF = 1
, IOM0_CLKCFG_FSEL_HFRC48MHZ = 2
, IOM0_CLKCFG_FSEL_HFRC24MHZ = 3
,
IOM0_CLKCFG_FSEL_HFRC12MHZ = 4
, IOM0_CLKCFG_FSEL_HFRC6MHZ = 5
, IOM0_CLKCFG_FSEL_HFRC3MHZ = 6
, IOM0_CLKCFG_FSEL_HFRC1p5MHZ = 7
} |
| |
| enum | IOM0_SUBMODCTRL_SMOD2TYPE_Enum {
IOM0_SUBMODCTRL_SMOD2TYPE_MSPI = 0
, IOM0_SUBMODCTRL_SMOD2TYPE_MI2C = 1
, IOM0_SUBMODCTRL_SMOD2TYPE_SSPI = 2
, IOM0_SUBMODCTRL_SMOD2TYPE_SI2C = 3
,
IOM0_SUBMODCTRL_SMOD2TYPE_MSI2S = 4
, IOM0_SUBMODCTRL_SMOD2TYPE_NA = 7
} |
| |
| enum | IOM0_SUBMODCTRL_SMOD1TYPE_Enum {
IOM0_SUBMODCTRL_SMOD1TYPE_MSPI = 0
, IOM0_SUBMODCTRL_SMOD1TYPE_MI2C = 1
, IOM0_SUBMODCTRL_SMOD1TYPE_SSPI = 2
, IOM0_SUBMODCTRL_SMOD1TYPE_SI2C = 3
,
IOM0_SUBMODCTRL_SMOD1TYPE_MSI2S = 4
, IOM0_SUBMODCTRL_SMOD1TYPE_NA = 7
} |
| |
| enum | IOM0_SUBMODCTRL_SMOD0TYPE_Enum { IOM0_SUBMODCTRL_SMOD0TYPE_MSPI = 0
, IOM0_SUBMODCTRL_SMOD0TYPE_MI2C = 1
, IOM0_SUBMODCTRL_SMOD0TYPE_MSI2S = 2
, IOM0_SUBMODCTRL_SMOD0TYPE_NA = 7
} |
| |
| enum | IOM0_CMD_CMD_Enum { IOM0_CMD_CMD_WRITE = 1
, IOM0_CMD_CMD_READ = 2
, IOM0_CMD_CMD_TMW = 3
, IOM0_CMD_CMD_TMR = 4
} |
| |
| enum | IOM0_CMDSTAT_CMDSTAT_Enum { IOM0_CMDSTAT_CMDSTAT_ERR = 1
, IOM0_CMDSTAT_CMDSTAT_ACTIVE = 2
, IOM0_CMDSTAT_CMDSTAT_IDLE = 4
, IOM0_CMDSTAT_CMDSTAT_WAIT = 6
} |
| |
| enum | IOM0_DMACFG_DPWROFF_Enum { IOM0_DMACFG_DPWROFF_DIS = 0
, IOM0_DMACFG_DPWROFF_EN = 1
} |
| |
| enum | IOM0_DMACFG_DMAPRI_Enum { IOM0_DMACFG_DMAPRI_LOW = 0
, IOM0_DMACFG_DMAPRI_HIGH = 1
} |
| |
| enum | IOM0_DMACFG_DMADIR_Enum { IOM0_DMACFG_DMADIR_P2M = 0
, IOM0_DMACFG_DMADIR_M2P = 1
} |
| |
| enum | IOM0_DMACFG_DMAEN_Enum { IOM0_DMACFG_DMAEN_DIS = 0
, IOM0_DMACFG_DMAEN_EN = 1
} |
| |
| enum | IOM0_CQCFG_MSPIFLGSEL_Enum { IOM0_CQCFG_MSPIFLGSEL_MSPI0FLGSEL = 0
, IOM0_CQCFG_MSPIFLGSEL_MSPI1FLGSEL = 1
, IOM0_CQCFG_MSPIFLGSEL_MSPI2FLGSEL = 2
} |
| |
| enum | IOM0_CQCFG_CQPRI_Enum { IOM0_CQCFG_CQPRI_LOW = 0
, IOM0_CQCFG_CQPRI_HIGH = 1
} |
| |
| enum | IOM0_CQCFG_CQEN_Enum { IOM0_CQCFG_CQEN_DIS = 0
, IOM0_CQCFG_CQEN_EN = 1
} |
| |
| enum | IOM0_CQPAUSEEN_CQPEN_Enum {
IOM0_CQPAUSEEN_CQPEN_IDXEQ = 32768
, IOM0_CQPAUSEEN_CQPEN_BLEXOREN = 16384
, IOM0_CQPAUSEEN_CQPEN_IOMXOREN = 8192
, IOM0_CQPAUSEEN_CQPEN_GPIOXOREN = 4096
,
IOM0_CQPAUSEEN_CQPEN_MSPI1XNOREN = 2048
, IOM0_CQPAUSEEN_CQPEN_MSPI0XNOREN = 1024
, IOM0_CQPAUSEEN_CQPEN_MSPI1XOREN = 512
, IOM0_CQPAUSEEN_CQPEN_MSPI0XOREN = 256
,
IOM0_CQPAUSEEN_CQPEN_SWFLAGEN7 = 128
, IOM0_CQPAUSEEN_CQPEN_SWFLAGEN6 = 64
, IOM0_CQPAUSEEN_CQPEN_SWFLAGEN5 = 32
, IOM0_CQPAUSEEN_CQPEN_SWFLAGEN4 = 16
,
IOM0_CQPAUSEEN_CQPEN_SWFLAGEN3 = 8
, IOM0_CQPAUSEEN_CQPEN_SWFLAGEN2 = 4
, IOM0_CQPAUSEEN_CQPEN_SWFLAGEN1 = 2
, IOM0_CQPAUSEEN_CQPEN_SWFLAGEN0 = 1
} |
| |
| enum | IOM0_STATUS_IDLEST_Enum { IOM0_STATUS_IDLEST_IDLE = 1
, IOM0_STATUS_IDLEST_RUN = 0
} |
| |
| enum | IOM0_STATUS_CMDACT_Enum { IOM0_STATUS_CMDACT_ACTIVE = 1
, IOM0_STATUS_CMDACT_INACTIVE = 0
} |
| |
| enum | IOM0_STATUS_ERR_Enum { IOM0_STATUS_ERR_ERROR = 1
, IOM0_STATUS_ERR_DEFAULT = 0
} |
| |
| enum | IOM0_MSPICFG_SPILSB_Enum { IOM0_MSPICFG_SPILSB_MSB = 0
, IOM0_MSPICFG_SPILSB_LSB = 1
} |
| |
| enum | IOM0_MSPICFG_RDFCPOL_Enum { IOM0_MSPICFG_RDFCPOL_HIGH = 0
, IOM0_MSPICFG_RDFCPOL_LOW = 1
} |
| |
| enum | IOM0_MSPICFG_WTFCPOL_Enum { IOM0_MSPICFG_WTFCPOL_HIGH = 0
, IOM0_MSPICFG_WTFCPOL_LOW = 1
} |
| |
| enum | IOM0_MSPICFG_WTFCIRQ_Enum { IOM0_MSPICFG_WTFCIRQ_MISO = 0
, IOM0_MSPICFG_WTFCIRQ_IRQ = 1
} |
| |
| enum | IOM0_MSPICFG_MOSIINV_Enum { IOM0_MSPICFG_MOSIINV_NORMAL = 0
, IOM0_MSPICFG_MOSIINV_INVERT = 1
} |
| |
| enum | IOM0_MSPICFG_RDFC_Enum { IOM0_MSPICFG_RDFC_DIS = 0
, IOM0_MSPICFG_RDFC_EN = 1
} |
| |
| enum | IOM0_MSPICFG_WTFC_Enum { IOM0_MSPICFG_WTFC_DIS = 0
, IOM0_MSPICFG_WTFC_EN = 1
} |
| |
| enum | IOM0_MSPICFG_SPHA_Enum { IOM0_MSPICFG_SPHA_SAMPLE_LEADING_EDGE = 0
, IOM0_MSPICFG_SPHA_SAMPLE_TRAILING_EDGE = 1
} |
| |
| enum | IOM0_MSPICFG_SPOL_Enum { IOM0_MSPICFG_SPOL_CLK_BASE_0 = 0
, IOM0_MSPICFG_SPOL_CLK_BASE_1 = 1
} |
| |
| enum | IOM0_MI2CCFG_ARBEN_Enum { IOM0_MI2CCFG_ARBEN_ARBENABLE = 1
, IOM0_MI2CCFG_ARBEN_ARBDISABLE = 0
} |
| |
| enum | IOM0_MI2CCFG_I2CLSB_Enum { IOM0_MI2CCFG_I2CLSB_MSBFIRST = 0
, IOM0_MI2CCFG_I2CLSB_LSBFIRST = 1
} |
| |
| enum | IOM0_MI2CCFG_ADDRSZ_Enum { IOM0_MI2CCFG_ADDRSZ_ADDRSZ7 = 0
, IOM0_MI2CCFG_ADDRSZ_ADDRSZ10 = 1
} |
| |
| enum | IOM0_I2SCLK_ASEL_Enum {
IOM0_I2SCLK_ASEL_MIN_PWR = 0
, IOM0_I2SCLK_ASEL_AUDCLK = 1
, IOM0_I2SCLK_ASEL_AUDCLK_DIV2 = 2
, IOM0_I2SCLK_ASEL_AUDCLK_DIV4 = 3
,
IOM0_I2SCLK_ASEL_AUDCLK_DIV8 = 4
, IOM0_I2SCLK_ASEL_AUDCLK_DIV16 = 5
, IOM0_I2SCLK_ASEL_AUDCLK_DIV32 = 6
, IOM0_I2SCLK_ASEL_AUDCLK_DIV64 = 7
} |
| |
| enum | IOSLAVE_CFG_IFCEN_Enum { IOSLAVE_CFG_IFCEN_DIS = 0
, IOSLAVE_CFG_IFCEN_EN = 1
} |
| |
| enum | IOSLAVE_CFG_WRAPPTR_Enum { IOSLAVE_CFG_WRAPPTR_NOWRAP = 0
, IOSLAVE_CFG_WRAPPTR_WRAP = 1
} |
| |
| enum | IOSLAVE_CFG_STARTRD_Enum { IOSLAVE_CFG_STARTRD_LATE = 0
, IOSLAVE_CFG_STARTRD_EARLY = 1
} |
| |
| enum | IOSLAVE_CFG_LSB_Enum { IOSLAVE_CFG_LSB_MSB_FIRST = 0
, IOSLAVE_CFG_LSB_LSB_FIRST = 1
} |
| |
| enum | IOSLAVE_CFG_SPOL_Enum { IOSLAVE_CFG_SPOL_SPI_MODES_0_3 = 0
, IOSLAVE_CFG_SPOL_SPI_MODES_1_2 = 1
} |
| |
| enum | IOSLAVE_CFG_IFCSEL_Enum { IOSLAVE_CFG_IFCSEL_I2C = 0
, IOSLAVE_CFG_IFCSEL_SPI = 1
} |
| |
| enum | MCUCTRL_CHIPPN_PN_Enum {
MCUCTRL_CHIPPN_PN_APOLLO4 = 8
, MCUCTRL_CHIPPN_PN_APOLLO3P = 7
, MCUCTRL_CHIPPN_PN_APOLLO3 = 6
, MCUCTRL_CHIPPN_PN_APOLLO2 = 3
,
MCUCTRL_CHIPPN_PN_APOLLO = 1
} |
| |
| enum | MCUCTRL_CHIPPN_MRAMSIZE_Enum { MCUCTRL_CHIPPN_MRAMSIZE_0P5MB = 0
, MCUCTRL_CHIPPN_MRAMSIZE_1P0MB = 1
, MCUCTRL_CHIPPN_MRAMSIZE_1P5MB = 2
, MCUCTRL_CHIPPN_MRAMSIZE_2P0MB = 3
} |
| |
| enum | MCUCTRL_CHIPPN_SRAMSIZE_Enum { MCUCTRL_CHIPPN_SRAMSIZE_384_512 = 0
, MCUCTRL_CHIPPN_SRAMSIZE_384_1024 = 1
, MCUCTRL_CHIPPN_SRAMSIZE_384_1024_384_96 = 2
} |
| |
| enum | MCUCTRL_CHIPPN_REVMAJ_Enum { MCUCTRL_CHIPPN_REVMAJ_A = 0
, MCUCTRL_CHIPPN_REVMAJ_B = 1
, MCUCTRL_CHIPPN_REVMAJ_C = 2
} |
| |
| enum | MCUCTRL_CHIPPN_REVMIN_Enum { MCUCTRL_CHIPPN_REVMIN_0 = 0
, MCUCTRL_CHIPPN_REVMIN_1 = 1
} |
| |
| enum | MCUCTRL_CHIPPN_PKG_Enum { MCUCTRL_CHIPPN_PKG_SIP = 0
, MCUCTRL_CHIPPN_PKG_QFN = 1
, MCUCTRL_CHIPPN_PKG_BGA = 2
, MCUCTRL_CHIPPN_PKG_CSP = 3
} |
| |
| enum | MCUCTRL_CHIPPN_PINS_Enum { MCUCTRL_CHIPPN_PINS_25 = 0
, MCUCTRL_CHIPPN_PINS_49 = 1
, MCUCTRL_CHIPPN_PINS_64 = 2
, MCUCTRL_CHIPPN_PINS_81 = 3
} |
| |
| enum | MCUCTRL_CHIPPN_TEMP_Enum { MCUCTRL_CHIPPN_TEMP_COM = 0
, MCUCTRL_CHIPPN_TEMP_MIL = 1
, MCUCTRL_CHIPPN_TEMP_AUTO = 2
, MCUCTRL_CHIPPN_TEMP_IND = 3
} |
| |
| enum | MCUCTRL_CHIPPN_QUAL_Enum { MCUCTRL_CHIPPN_QUAL_SAMPLE = 0
, MCUCTRL_CHIPPN_QUAL_QUALIFIED = 1
} |
| |
| enum | MCUCTRL_CHIPREV_REVMAJ_Enum { MCUCTRL_CHIPREV_REVMAJ_C = 3
, MCUCTRL_CHIPREV_REVMAJ_B = 2
, MCUCTRL_CHIPREV_REVMAJ_A = 1
} |
| |
| enum | MCUCTRL_CHIPREV_REVMIN_Enum { MCUCTRL_CHIPREV_REVMIN_REV2 = 3
, MCUCTRL_CHIPREV_REVMIN_REV1 = 2
, MCUCTRL_CHIPREV_REVMIN_REV0 = 1
} |
| |
| enum | MCUCTRL_VENDORID_VENDORID_Enum { MCUCTRL_VENDORID_VENDORID_AMBIQ = 1095582289
, MCUCTRL_VENDORID_VENDORID_DEFAULT = 0
} |
| |
| enum | MCUCTRL_ACRG_ACRGIBIASSEL_Enum { MCUCTRL_ACRG_ACRGIBIASSEL_BGSEL = 0
, MCUCTRL_ACRG_ACRGIBIASSEL_CCRGSEL = 1
} |
| |
| enum | MCUCTRL_ACRG_ACRGPWD_Enum { MCUCTRL_ACRG_ACRGPWD_ACRG_PWR_DN = 1
, MCUCTRL_ACRG_ACRGPWD_ACRG_PWR_UP = 0
} |
| |
| enum | MCUCTRL_VREFGEN2_TVRG2PWD_Enum { MCUCTRL_VREFGEN2_TVRG2PWD_PWR_DN = 1
, MCUCTRL_VREFGEN2_TVRG2PWD_PWR_UP = 0
} |
| |
| enum | MCUCTRL_VREFGEN2_TVRGPWD_Enum { MCUCTRL_VREFGEN2_TVRGPWD_PWR_DN = 1
, MCUCTRL_VREFGEN2_TVRGPWD_PWR_UP = 0
} |
| |
| enum | MCUCTRL_LFRC_LFRCSIMOCLKDIV_Enum {
MCUCTRL_LFRC_LFRCSIMOCLKDIV_DIV1 = 0
, MCUCTRL_LFRC_LFRCSIMOCLKDIV_DIV2 = 1
, MCUCTRL_LFRC_LFRCSIMOCLKDIV_DIV4 = 2
, MCUCTRL_LFRC_LFRCSIMOCLKDIV_DIV8 = 3
,
MCUCTRL_LFRC_LFRCSIMOCLKDIV_DIV16 = 4
, MCUCTRL_LFRC_LFRCSIMOCLKDIV_DIV32 = 5
} |
| |
| enum | MCUCTRL_LFRC_RESETLFRC_Enum { MCUCTRL_LFRC_RESETLFRC_EN = 0
, MCUCTRL_LFRC_RESETLFRC_RESET = 1
} |
| |
| enum | MCUCTRL_LFRC_PWDLFRC_Enum { MCUCTRL_LFRC_PWDLFRC_PWRUP = 0
, MCUCTRL_LFRC_PWDLFRC_PWRDN = 1
} |
| |
| enum | MCUCTRL_LFRC_LFRCSWE_Enum { MCUCTRL_LFRC_LFRCSWE_OVERRIDE_DIS = 0
, MCUCTRL_LFRC_LFRCSWE_OVERRIDE_EN = 1
} |
| |
| enum | MCUCTRL_ADCPWRCTRL_VDDADCRESETN_Enum { MCUCTRL_ADCPWRCTRL_VDDADCRESETN_ASSERT = 0
, MCUCTRL_ADCPWRCTRL_VDDADCRESETN_DEASSERT = 1
} |
| |
| enum | MCUCTRL_ADCPWRCTRL_VDDADCDIGISOLATE_Enum { MCUCTRL_ADCPWRCTRL_VDDADCDIGISOLATE_DIS = 0
, MCUCTRL_ADCPWRCTRL_VDDADCDIGISOLATE_EN = 1
} |
| |
| enum | MCUCTRL_ADCPWRCTRL_VDDADCSARISOLATE_Enum { MCUCTRL_ADCPWRCTRL_VDDADCSARISOLATE_DIS = 0
, MCUCTRL_ADCPWRCTRL_VDDADCSARISOLATE_EN = 1
} |
| |
| enum | MCUCTRL_ADCPWRCTRL_REFKEEPPEN_Enum { MCUCTRL_ADCPWRCTRL_REFKEEPPEN_DIS = 0
, MCUCTRL_ADCPWRCTRL_REFKEEPPEN_EN = 1
} |
| |
| enum | MCUCTRL_ADCPWRCTRL_REFBUFPEN_Enum { MCUCTRL_ADCPWRCTRL_REFBUFPEN_DIS = 0
, MCUCTRL_ADCPWRCTRL_REFBUFPEN_EN = 1
} |
| |
| enum | MCUCTRL_ADCPWRCTRL_BGTLPPEN_Enum { MCUCTRL_ADCPWRCTRL_BGTLPPEN_DIS = 0
, MCUCTRL_ADCPWRCTRL_BGTLPPEN_EN = 1
} |
| |
| enum | MCUCTRL_ADCPWRCTRL_BGTPEN_Enum { MCUCTRL_ADCPWRCTRL_BGTPEN_DIS = 0
, MCUCTRL_ADCPWRCTRL_BGTPEN_EN = 1
} |
| |
| enum | MCUCTRL_ADCPWRCTRL_ADCBPSEN_Enum { MCUCTRL_ADCPWRCTRL_ADCBPSEN_DIS = 0
, MCUCTRL_ADCPWRCTRL_ADCBPSEN_EN = 1
} |
| |
| enum | MCUCTRL_ADCPWRCTRL_ADCAPSEN_Enum { MCUCTRL_ADCPWRCTRL_ADCAPSEN_DIS = 0
, MCUCTRL_ADCPWRCTRL_ADCAPSEN_EN = 1
} |
| |
| enum | MCUCTRL_ADCPWRCTRL_ADCPWRCTRLSWE_Enum { MCUCTRL_ADCPWRCTRL_ADCPWRCTRLSWE_OVERRIDE_DIS = 0
, MCUCTRL_ADCPWRCTRL_ADCPWRCTRLSWE_OVERRIDE_EN = 1
} |
| |
| enum | MCUCTRL_ADCCAL_ADCCALIBRATED_Enum { MCUCTRL_ADCCAL_ADCCALIBRATED_FALSE = 0
, MCUCTRL_ADCCAL_ADCCALIBRATED_TRUE = 1
} |
| |
| enum | MCUCTRL_ADCCAL_CALONPWRUP_Enum { MCUCTRL_ADCCAL_CALONPWRUP_DIS = 0
, MCUCTRL_ADCCAL_CALONPWRUP_EN = 1
} |
| |
| enum | MCUCTRL_ADCBATTLOAD_BATTLOAD_Enum { MCUCTRL_ADCBATTLOAD_BATTLOAD_DIS = 0
, MCUCTRL_ADCBATTLOAD_BATTLOAD_EN = 1
} |
| |
| enum | MCUCTRL_XTALCTRL_XTALCOMPPDNB_Enum { MCUCTRL_XTALCTRL_XTALCOMPPDNB_PWRUPCOMP = 1
, MCUCTRL_XTALCTRL_XTALCOMPPDNB_PWRDNCOMP = 0
} |
| |
| enum | MCUCTRL_XTALCTRL_XTALPDNB_Enum { MCUCTRL_XTALCTRL_XTALPDNB_PWRUPCORE = 1
, MCUCTRL_XTALCTRL_XTALPDNB_PWRDNCORE = 0
} |
| |
| enum | MCUCTRL_XTALCTRL_XTALCOMPBYPASS_Enum { MCUCTRL_XTALCTRL_XTALCOMPBYPASS_USECOMP = 0
, MCUCTRL_XTALCTRL_XTALCOMPBYPASS_BYPCOMP = 1
} |
| |
| enum | MCUCTRL_XTALCTRL_XTALCOREDISFB_Enum { MCUCTRL_XTALCTRL_XTALCOREDISFB_EN = 0
, MCUCTRL_XTALCTRL_XTALCOREDISFB_DIS = 1
} |
| |
| enum | MCUCTRL_XTALCTRL_XTALSWE_Enum { MCUCTRL_XTALCTRL_XTALSWE_OVERRIDE_DIS = 0
, MCUCTRL_XTALCTRL_XTALSWE_OVERRIDE_EN = 1
} |
| |
| enum | MCUCTRL_XTALGENCTRL_ACWARMUP_Enum { MCUCTRL_XTALGENCTRL_ACWARMUP_SEC1 = 0
, MCUCTRL_XTALGENCTRL_ACWARMUP_SEC2 = 1
, MCUCTRL_XTALGENCTRL_ACWARMUP_SEC4 = 2
, MCUCTRL_XTALGENCTRL_ACWARMUP_SEC8 = 3
} |
| |
| enum | MCUCTRL_BODISABLE_BODCLVREN_Enum { MCUCTRL_BODISABLE_BODCLVREN_EN = 1
, MCUCTRL_BODISABLE_BODCLVREN_DIS = 0
} |
| |
| enum | MCUCTRL_BODISABLE_BODSREN_Enum { MCUCTRL_BODISABLE_BODSREN_EN = 1
, MCUCTRL_BODISABLE_BODSREN_DIS = 0
} |
| |
| enum | MCUCTRL_BODISABLE_BODFREN_Enum { MCUCTRL_BODISABLE_BODFREN_EN = 1
, MCUCTRL_BODISABLE_BODFREN_DIS = 0
} |
| |
| enum | MCUCTRL_BODISABLE_BODCREN_Enum { MCUCTRL_BODISABLE_BODCREN_EN = 1
, MCUCTRL_BODISABLE_BODCREN_DIS = 0
} |
| |
| enum | MCUCTRL_BODISABLE_BODLRDE_Enum { MCUCTRL_BODISABLE_BODLRDE_EN = 0
, MCUCTRL_BODISABLE_BODLRDE_DIS = 1
} |
| |
| enum | MCUCTRL_BOOTLOADER_SECBOOTONRST_Enum { MCUCTRL_BOOTLOADER_SECBOOTONRST_DISABLED = 0
, MCUCTRL_BOOTLOADER_SECBOOTONRST_ENABLED = 1
, MCUCTRL_BOOTLOADER_SECBOOTONRST_ERROR = 2
} |
| |
| enum | MCUCTRL_BOOTLOADER_SECBOOT_Enum { MCUCTRL_BOOTLOADER_SECBOOT_DISABLED = 0
, MCUCTRL_BOOTLOADER_SECBOOT_ENABLED = 1
, MCUCTRL_BOOTLOADER_SECBOOT_ERROR = 2
} |
| |
| enum | MCUCTRL_BOOTLOADER_SECBOOTFEATURE_Enum { MCUCTRL_BOOTLOADER_SECBOOTFEATURE_DISABLED = 0
, MCUCTRL_BOOTLOADER_SECBOOTFEATURE_ENABLED = 1
, MCUCTRL_BOOTLOADER_SECBOOTFEATURE_ERROR = 2
} |
| |
| enum | MCUCTRL_BOOTLOADER_SBLLOCK_Enum { MCUCTRL_BOOTLOADER_SBLLOCK_LOCK = 1
, MCUCTRL_BOOTLOADER_SBLLOCK_UNLOCK = 0
} |
| |
| enum | MCUCTRL_BOOTLOADER_PROTLOCK_Enum { MCUCTRL_BOOTLOADER_PROTLOCK_LOCK = 1
, MCUCTRL_BOOTLOADER_PROTLOCK_DEFAULT = 0
} |
| |
| enum | MCUCTRL_BOOTLOADER_SBRLOCK_Enum { MCUCTRL_BOOTLOADER_SBRLOCK_LOCK = 1
, MCUCTRL_BOOTLOADER_SBRLOCK_DEFAULT = 0
} |
| |
| enum | MCUCTRL_BOOTLOADER_BOOTLOADERLOW_Enum { MCUCTRL_BOOTLOADER_BOOTLOADERLOW_ADDR0 = 1
, MCUCTRL_BOOTLOADER_BOOTLOADERLOW_NOADDR0 = 0
} |
| |
| enum | MCUCTRL_SHADOWVALID_INFO0VALID_Enum { MCUCTRL_SHADOWVALID_INFO0VALID_VALID = 1
, MCUCTRL_SHADOWVALID_INFO0VALID_DEFAULT = 0
} |
| |
| enum | MCUCTRL_SHADOWVALID_BLDSLEEP_Enum { MCUCTRL_SHADOWVALID_BLDSLEEP_DEEPSLEEP = 1
, MCUCTRL_SHADOWVALID_BLDSLEEP_SLEEP = 0
} |
| |
| enum | MCUCTRL_SHADOWVALID_VALID_Enum { MCUCTRL_SHADOWVALID_VALID_VALID = 1
, MCUCTRL_SHADOWVALID_VALID_DEFAULT = 0
} |
| |
| enum | MCUCTRL_PMUENABLE_ENABLE_Enum { MCUCTRL_PMUENABLE_ENABLE_DIS = 0
, MCUCTRL_PMUENABLE_ENABLE_EN = 1
} |
| |
| enum | MCUCTRL_DBGCTRL_DBGDSP1OCDHALTONRST_Enum { MCUCTRL_DBGCTRL_DBGDSP1OCDHALTONRST_DIS = 0
, MCUCTRL_DBGCTRL_DBGDSP1OCDHALTONRST_EN = 1
} |
| |
| enum | MCUCTRL_DBGCTRL_DBGDSP0OCDHALTONRST_Enum { MCUCTRL_DBGCTRL_DBGDSP0OCDHALTONRST_DIS = 0
, MCUCTRL_DBGCTRL_DBGDSP0OCDHALTONRST_EN = 1
} |
| |
| enum | MCUCTRL_DBGCTRL_DBGTSCLKSEL_Enum {
MCUCTRL_DBGCTRL_DBGTSCLKSEL_LOWPWR = 0
, MCUCTRL_DBGCTRL_DBGTSCLKSEL_HFRCDIV2 = 1
, MCUCTRL_DBGCTRL_DBGTSCLKSEL_HFRCDIV8 = 2
, MCUCTRL_DBGCTRL_DBGTSCLKSEL_HFRCDIV16 = 3
,
MCUCTRL_DBGCTRL_DBGTSCLKSEL_HFRCDIV32 = 4
} |
| |
| enum | MCUCTRL_DBGCTRL_DBGDSP1TRACEEN_Enum { MCUCTRL_DBGCTRL_DBGDSP1TRACEEN_DIS = 0
, MCUCTRL_DBGCTRL_DBGDSP1TRACEEN_EN = 1
} |
| |
| enum | MCUCTRL_DBGCTRL_DBGDSP0TRACEEN_Enum { MCUCTRL_DBGCTRL_DBGDSP0TRACEEN_DIS = 0
, MCUCTRL_DBGCTRL_DBGDSP0TRACEEN_EN = 1
} |
| |
| enum | MCUCTRL_DBGCTRL_DBGETMTRACEEN_Enum { MCUCTRL_DBGCTRL_DBGETMTRACEEN_DIS = 0
, MCUCTRL_DBGCTRL_DBGETMTRACEEN_EN = 1
} |
| |
| enum | MCUCTRL_DBGCTRL_DBGETBENABLE_Enum { MCUCTRL_DBGCTRL_DBGETBENABLE_DIS = 0
, MCUCTRL_DBGCTRL_DBGETBENABLE_EN = 1
} |
| |
| enum | MCUCTRL_DBGCTRL_CM4CLKSEL_Enum {
MCUCTRL_DBGCTRL_CM4CLKSEL_LOWPWR = 0
, MCUCTRL_DBGCTRL_CM4CLKSEL_HFRC96 = 1
, MCUCTRL_DBGCTRL_CM4CLKSEL_HFRC48 = 2
, MCUCTRL_DBGCTRL_CM4CLKSEL_HFRC24 = 3
,
MCUCTRL_DBGCTRL_CM4CLKSEL_HFRC6 = 4
, MCUCTRL_DBGCTRL_CM4CLKSEL_HFRC3 = 5
, MCUCTRL_DBGCTRL_CM4CLKSEL_HFRC1P5 = 6
, MCUCTRL_DBGCTRL_CM4CLKSEL_HFRC2_192 = 7
} |
| |
| enum | MCUCTRL_DBGCTRL_CM4TPIUENABLE_Enum { MCUCTRL_DBGCTRL_CM4TPIUENABLE_DIS = 0
, MCUCTRL_DBGCTRL_CM4TPIUENABLE_EN = 1
} |
| |
| enum | MCUCTRL_APBDMACTRL_DECODEABORT_Enum { MCUCTRL_APBDMACTRL_DECODEABORT_DISABLE = 0
, MCUCTRL_APBDMACTRL_DECODEABORT_ENABLE = 1
} |
| |
| enum | MCUCTRL_APBDMACTRL_DMAENABLE_Enum { MCUCTRL_APBDMACTRL_DMAENABLE_DISABLE = 0
, MCUCTRL_APBDMACTRL_DMAENABLE_ENABLE = 1
} |
| |
| enum | MCUCTRL_KEXTCLKSEL_KEXTCLKSEL_Enum { MCUCTRL_KEXTCLKSEL_KEXTCLKSEL_Key = 83
} |
| |
| enum | MCUCTRL_PWRSW0_PWRSWVDDRCPUSTATSEL_Enum { MCUCTRL_PWRSW0_PWRSWVDDRCPUSTATSEL_VDDC = 1
, MCUCTRL_PWRSW0_PWRSWVDDRCPUSTATSEL_VDDFLP = 0
} |
| |
| enum | MCUCTRL_PWRSW0_PWRSWVDDMLSTATSEL_Enum { MCUCTRL_PWRSW0_PWRSWVDDMLSTATSEL_VDDC = 0
, MCUCTRL_PWRSW0_PWRSWVDDMLSTATSEL_VDDF = 1
} |
| |
| enum | MCUCTRL_PWRSW0_PWRSWVDDMDSP1STATSEL_Enum { MCUCTRL_PWRSW0_PWRSWVDDMDSP1STATSEL_VDDC = 0
, MCUCTRL_PWRSW0_PWRSWVDDMDSP1STATSEL_VDDF = 1
} |
| |
| enum | MCUCTRL_PWRSW0_PWRSWVDDMDSP0STATSEL_Enum { MCUCTRL_PWRSW0_PWRSWVDDMDSP0STATSEL_VDDC = 0
, MCUCTRL_PWRSW0_PWRSWVDDMDSP0STATSEL_VDDF = 1
} |
| |
| enum | MCUCTRL_PWRSW0_PWRSWVDDMCPUSTATSEL_Enum { MCUCTRL_PWRSW0_PWRSWVDDMCPUSTATSEL_VDDC = 0
, MCUCTRL_PWRSW0_PWRSWVDDMCPUSTATSEL_VDDF = 1
} |
| |
| enum | MCUCTRL_PWRSW1_PWRSWVDDRMSTATSEL_Enum { MCUCTRL_PWRSW1_PWRSWVDDRMSTATSEL_VDDC = 1
, MCUCTRL_PWRSW1_PWRSWVDDRMSTATSEL_VDDFLP = 0
} |
| |
| enum | MCUCTRL_PWRSW1_PWRSWVDDRLSTATSEL_Enum { MCUCTRL_PWRSW1_PWRSWVDDRLSTATSEL_VDDC = 1
, MCUCTRL_PWRSW1_PWRSWVDDRLSTATSEL_VDDFLP = 0
} |
| |
| enum | MCUCTRL_PWRSW1_PWRSWVDDRDSP1STATSEL_Enum { MCUCTRL_PWRSW1_PWRSWVDDRDSP1STATSEL_VDDC = 1
, MCUCTRL_PWRSW1_PWRSWVDDRDSP1STATSEL_VDDFLP = 0
} |
| |
| enum | MCUCTRL_PWRSW1_PWRSWVDDRDSP0STATSEL_Enum { MCUCTRL_PWRSW1_PWRSWVDDRDSP0STATSEL_VDDC = 1
, MCUCTRL_PWRSW1_PWRSWVDDRDSP0STATSEL_VDDFLP = 0
} |
| |
| enum | MCUCTRL_AUDADCPWRCTRL_VDDAUDADCRESETN_Enum { MCUCTRL_AUDADCPWRCTRL_VDDAUDADCRESETN_ASSERT = 0
, MCUCTRL_AUDADCPWRCTRL_VDDAUDADCRESETN_DEASSERT = 1
} |
| |
| enum | MCUCTRL_AUDADCPWRCTRL_VDDAUDADCDIGISOLATE_Enum { MCUCTRL_AUDADCPWRCTRL_VDDAUDADCDIGISOLATE_DIS = 0
, MCUCTRL_AUDADCPWRCTRL_VDDAUDADCDIGISOLATE_EN = 1
} |
| |
| enum | MCUCTRL_AUDADCPWRCTRL_VDDAUDADCSARISOLATE_Enum { MCUCTRL_AUDADCPWRCTRL_VDDAUDADCSARISOLATE_DIS = 0
, MCUCTRL_AUDADCPWRCTRL_VDDAUDADCSARISOLATE_EN = 1
} |
| |
| enum | MCUCTRL_AUDADCPWRCTRL_AUDREFKEEPPEN_Enum { MCUCTRL_AUDADCPWRCTRL_AUDREFKEEPPEN_DIS = 0
, MCUCTRL_AUDADCPWRCTRL_AUDREFKEEPPEN_EN = 1
} |
| |
| enum | MCUCTRL_AUDADCPWRCTRL_AUDREFBUFPEN_Enum { MCUCTRL_AUDADCPWRCTRL_AUDREFBUFPEN_DIS = 0
, MCUCTRL_AUDADCPWRCTRL_AUDREFBUFPEN_EN = 1
} |
| |
| enum | MCUCTRL_AUDADCPWRCTRL_AUDBGTPEN_Enum { MCUCTRL_AUDADCPWRCTRL_AUDBGTPEN_DIS = 0
, MCUCTRL_AUDADCPWRCTRL_AUDBGTPEN_EN = 1
} |
| |
| enum | MCUCTRL_AUDADCPWRCTRL_AUDADCBPSEN_Enum { MCUCTRL_AUDADCPWRCTRL_AUDADCBPSEN_DIS = 0
, MCUCTRL_AUDADCPWRCTRL_AUDADCBPSEN_EN = 1
} |
| |
| enum | MCUCTRL_AUDADCPWRCTRL_AUDADCAPSEN_Enum { MCUCTRL_AUDADCPWRCTRL_AUDADCAPSEN_DIS = 0
, MCUCTRL_AUDADCPWRCTRL_AUDADCAPSEN_EN = 1
} |
| |
| enum | MCUCTRL_AUDADCPWRCTRL_AUDADCPWRCTRLSWE_Enum { MCUCTRL_AUDADCPWRCTRL_AUDADCPWRCTRLSWE_OVERRIDE_DIS = 0
, MCUCTRL_AUDADCPWRCTRL_AUDADCPWRCTRLSWE_OVERRIDE_EN = 1
} |
| |
| enum | MSPI0_CTRL_PIODEV_Enum { MSPI0_CTRL_PIODEV_DEVICE0 = 0
, MSPI0_CTRL_PIODEV_DEVICE1 = 1
} |
| |
| enum | MSPI0_CTRL1_PIOMIXED_Enum {
MSPI0_CTRL1_PIOMIXED_NORMAL = 0
, MSPI0_CTRL1_PIOMIXED_D2 = 1
, MSPI0_CTRL1_PIOMIXED_AD2 = 3
, MSPI0_CTRL1_PIOMIXED_D4 = 5
,
MSPI0_CTRL1_PIOMIXED_AD4 = 7
, MSPI0_CTRL1_PIOMIXED_D8 = 9
, MSPI0_CTRL1_PIOMIXED_AD8 = 11
} |
| |
| enum | MSPI0_MSPICFG_IOMSEL_Enum {
MSPI0_MSPICFG_IOMSEL_IOM0 = 0
, MSPI0_MSPICFG_IOMSEL_IOM1 = 1
, MSPI0_MSPICFG_IOMSEL_IOM2 = 2
, MSPI0_MSPICFG_IOMSEL_IOM3 = 3
,
MSPI0_MSPICFG_IOMSEL_IOM4 = 4
, MSPI0_MSPICFG_IOMSEL_IOM5 = 5
, MSPI0_MSPICFG_IOMSEL_IOM6 = 6
, MSPI0_MSPICFG_IOMSEL_IOM7 = 7
,
MSPI0_MSPICFG_IOMSEL_MSPI0 = 8
, MSPI0_MSPICFG_IOMSEL_MSPI1 = 9
, MSPI0_MSPICFG_IOMSEL_MSPI2 = 10
} |
| |
| enum | MSPI0_MSPICFG_APBCLK_Enum { MSPI0_MSPICFG_APBCLK_DIS = 0
, MSPI0_MSPICFG_APBCLK_EN = 1
} |
| |
| enum | MSPI0_PADOUTEN_OUTEN_Enum {
MSPI0_PADOUTEN_OUTEN_QUAD0 = 271
, MSPI0_PADOUTEN_OUTEN_QUAD1 = 496
, MSPI0_PADOUTEN_OUTEN_OCTAL = 1023
, MSPI0_PADOUTEN_OUTEN_SERIAL0 = 259
,
MSPI0_PADOUTEN_OUTEN_SERIAL1 = 304
, MSPI0_PADOUTEN_OUTEN_HEX = 524287
} |
| |
| enum | MSPI0_DEV0AXI_READONLY0_Enum { MSPI0_DEV0AXI_READONLY0_READONLY = 1
, MSPI0_DEV0AXI_READONLY0_READWRITE = 0
} |
| |
| enum | MSPI0_DEV0AXI_SIZE0_Enum {
MSPI0_DEV0AXI_SIZE0_SIZE64K = 0
, MSPI0_DEV0AXI_SIZE0_SIZE128K = 1
, MSPI0_DEV0AXI_SIZE0_SIZE256K = 2
, MSPI0_DEV0AXI_SIZE0_SIZE512K = 3
,
MSPI0_DEV0AXI_SIZE0_SIZE1M = 4
, MSPI0_DEV0AXI_SIZE0_SIZE2M = 5
, MSPI0_DEV0AXI_SIZE0_SIZE4M = 6
, MSPI0_DEV0AXI_SIZE0_SIZE8M = 7
,
MSPI0_DEV0AXI_SIZE0_SIZE16M = 8
, MSPI0_DEV0AXI_SIZE0_SIZE32M = 9
, MSPI0_DEV0AXI_SIZE0_SIZE64M = 10
} |
| |
| enum | MSPI0_DEV0CFG_TXNEG0_Enum { MSPI0_DEV0CFG_TXNEG0_NORMAL = 0
, MSPI0_DEV0CFG_TXNEG0_NEGEDGE = 1
} |
| |
| enum | MSPI0_DEV0CFG_RXNEG0_Enum { MSPI0_DEV0CFG_RXNEG0_NORMAL = 0
, MSPI0_DEV0CFG_RXNEG0_NEGEDGE = 1
} |
| |
| enum | MSPI0_DEV0CFG_RXCAP0_Enum { MSPI0_DEV0CFG_RXCAP0_NORMAL = 0
, MSPI0_DEV0CFG_RXCAP0_DELAY = 1
} |
| |
| enum | MSPI0_DEV0CFG_CLKDIV0_Enum {
MSPI0_DEV0CFG_CLKDIV0_CLK96 = 1
, MSPI0_DEV0CFG_CLKDIV0_CLK48 = 2
, MSPI0_DEV0CFG_CLKDIV0_CLK32 = 3
, MSPI0_DEV0CFG_CLKDIV0_CLK24 = 4
,
MSPI0_DEV0CFG_CLKDIV0_CLK16 = 6
, MSPI0_DEV0CFG_CLKDIV0_CLK12 = 8
, MSPI0_DEV0CFG_CLKDIV0_CLK8 = 12
, MSPI0_DEV0CFG_CLKDIV0_CLK6 = 16
,
MSPI0_DEV0CFG_CLKDIV0_CLK4 = 24
, MSPI0_DEV0CFG_CLKDIV0_CLK3 = 32
} |
| |
| enum | MSPI0_DEV0CFG_CPOL0_Enum { MSPI0_DEV0CFG_CPOL0_LOW = 0
, MSPI0_DEV0CFG_CPOL0_HIGH = 1
} |
| |
| enum | MSPI0_DEV0CFG_CPHA0_Enum { MSPI0_DEV0CFG_CPHA0_MIDDLE = 0
, MSPI0_DEV0CFG_CPHA0_START = 1
} |
| |
| enum | MSPI0_DEV0CFG_ISIZE0_Enum { MSPI0_DEV0CFG_ISIZE0_I8 = 0
, MSPI0_DEV0CFG_ISIZE0_I16 = 1
} |
| |
| enum | MSPI0_DEV0CFG_ASIZE0_Enum { MSPI0_DEV0CFG_ASIZE0_A1 = 0
, MSPI0_DEV0CFG_ASIZE0_A2 = 1
, MSPI0_DEV0CFG_ASIZE0_A3 = 2
, MSPI0_DEV0CFG_ASIZE0_A4 = 3
} |
| |
| enum | MSPI0_DEV0CFG_DEVCFG0_Enum {
MSPI0_DEV0CFG_DEVCFG0_SERIAL0 = 1
, MSPI0_DEV0CFG_DEVCFG0_SERIAL1 = 2
, MSPI0_DEV0CFG_DEVCFG0_DUAL0 = 5
, MSPI0_DEV0CFG_DEVCFG0_DUAL1 = 6
,
MSPI0_DEV0CFG_DEVCFG0_QUAD0 = 9
, MSPI0_DEV0CFG_DEVCFG0_QUAD1 = 10
, MSPI0_DEV0CFG_DEVCFG0_OCTAL0 = 13
, MSPI0_DEV0CFG_DEVCFG0_OCTAL1 = 14
,
MSPI0_DEV0CFG_DEVCFG0_QUADPAIRED = 15
, MSPI0_DEV0CFG_DEVCFG0_QUADPAIRED_SERIAL = 3
, MSPI0_DEV0CFG_DEVCFG0_HEX0 = 17
, MSPI0_DEV0CFG_DEVCFG0_HEX1 = 18
} |
| |
| enum | MSPI0_DEV0XIP_XIPMIXED0_Enum {
MSPI0_DEV0XIP_XIPMIXED0_NORMAL = 0
, MSPI0_DEV0XIP_XIPMIXED0_D2 = 1
, MSPI0_DEV0XIP_XIPMIXED0_AD2 = 3
, MSPI0_DEV0XIP_XIPMIXED0_D4 = 5
,
MSPI0_DEV0XIP_XIPMIXED0_AD4 = 7
, MSPI0_DEV0XIP_XIPMIXED0_D8 = 9
, MSPI0_DEV0XIP_XIPMIXED0_AD8 = 11
} |
| |
| enum | MSPI0_DEV0XIP_XIPACK0_Enum { MSPI0_DEV0XIP_XIPACK0_NOACK = 0
, MSPI0_DEV0XIP_XIPACK0_ACK = 2
, MSPI0_DEV0XIP_XIPACK0_TERMINATE = 3
} |
| |
| enum | MSPI0_DEV0BOUNDARY_DMABOUND0_Enum {
MSPI0_DEV0BOUNDARY_DMABOUND0_NONE = 0
, MSPI0_DEV0BOUNDARY_DMABOUND0_BREAK32 = 1
, MSPI0_DEV0BOUNDARY_DMABOUND0_BREAK64 = 2
, MSPI0_DEV0BOUNDARY_DMABOUND0_BREAK128 = 3
,
MSPI0_DEV0BOUNDARY_DMABOUND0_BREAK256 = 4
, MSPI0_DEV0BOUNDARY_DMABOUND0_BREAK512 = 5
, MSPI0_DEV0BOUNDARY_DMABOUND0_BREAK1K = 6
, MSPI0_DEV0BOUNDARY_DMABOUND0_BREAK2K = 7
,
MSPI0_DEV0BOUNDARY_DMABOUND0_BREAK4K = 8
, MSPI0_DEV0BOUNDARY_DMABOUND0_BREAK8K = 9
, MSPI0_DEV0BOUNDARY_DMABOUND0_BREAK16K = 10
} |
| |
| enum | MSPI0_DEV0XIPMISC_APNDODD0_Enum { MSPI0_DEV0XIPMISC_APNDODD0_DIS = 0
, MSPI0_DEV0XIPMISC_APNDODD0_EN = 1
} |
| |
| enum | MSPI0_DEV0XIPMISC_XIPBOUNDARY0_Enum { MSPI0_DEV0XIPMISC_XIPBOUNDARY0_DIS = 0
, MSPI0_DEV0XIPMISC_XIPBOUNDARY0_EN = 1
} |
| |
| enum | MSPI0_DEV0XIPMISC_BEON0_Enum { MSPI0_DEV0XIPMISC_BEON0_DIS = 0
, MSPI0_DEV0XIPMISC_BEON0_EN = 1
} |
| |
| enum | MSPI0_DEV0XIPMISC_XIPODD0_Enum { MSPI0_DEV0XIPMISC_XIPODD0_DIS = 0
, MSPI0_DEV0XIPMISC_XIPODD0_EN = 1
} |
| |
| enum | MSPI0_DMACFG_DMAPRI_Enum { MSPI0_DMACFG_DMAPRI_LOW = 0
, MSPI0_DMACFG_DMAPRI_HIGH = 1
, MSPI0_DMACFG_DMAPRI_AUTO = 2
} |
| |
| enum | MSPI0_DMACFG_DMADEV_Enum { MSPI0_DMACFG_DMADEV_DEV0 = 0
} |
| |
| enum | MSPI0_DMACFG_DMADIR_Enum { MSPI0_DMACFG_DMADIR_P2M = 0
, MSPI0_DMACFG_DMADIR_M2P = 1
} |
| |
| enum | MSPI0_DMACFG_DMAEN_Enum { MSPI0_DMACFG_DMAEN_DIS = 0
, MSPI0_DMACFG_DMAEN_EN = 3
} |
| |
| enum | MSPI0_CQCFG_CQPRI_Enum { MSPI0_CQCFG_CQPRI_LOW = 0
, MSPI0_CQCFG_CQPRI_HIGH = 1
} |
| |
| enum | MSPI0_CQCFG_CQEN_Enum { MSPI0_CQCFG_CQEN_DIS = 0
, MSPI0_CQCFG_CQEN_EN = 1
} |
| |
| enum | MSPI0_CQFLAGS_CQFLAGS_Enum {
MSPI0_CQFLAGS_CQFLAGS_STOP = 32768
, MSPI0_CQFLAGS_CQFLAGS_CQIDX = 16384
, MSPI0_CQFLAGS_CQFLAGS_BUF1XOREN = 8192
, MSPI0_CQFLAGS_CQFLAGS_BUF0XOREN = 4096
,
MSPI0_CQFLAGS_CQFLAGS_DMACPL = 2048
, MSPI0_CQFLAGS_CQFLAGS_CMDCPL = 1024
, MSPI0_CQFLAGS_CQFLAGS_IOM1READY = 512
, MSPI0_CQFLAGS_CQFLAGS_IOM0READY = 256
,
MSPI0_CQFLAGS_CQFLAGS_SWFLAG7 = 128
, MSPI0_CQFLAGS_CQFLAGS_SWFLAG6 = 64
, MSPI0_CQFLAGS_CQFLAGS_SWFLAG5 = 32
, MSPI0_CQFLAGS_CQFLAGS_SWFLAG4 = 16
,
MSPI0_CQFLAGS_CQFLAGS_SWFLAG3 = 8
, MSPI0_CQFLAGS_CQFLAGS_SWFLAG2 = 4
, MSPI0_CQFLAGS_CQFLAGS_SWFLAG1 = 2
, MSPI0_CQFLAGS_CQFLAGS_SWFLAG0 = 1
} |
| |
| enum | MSPI0_CQPAUSE_CQMASK_Enum {
MSPI0_CQPAUSE_CQMASK_STOP = 32768
, MSPI0_CQPAUSE_CQMASK_CQIDX = 16384
, MSPI0_CQPAUSE_CQMASK_BUF1XOREN = 8192
, MSPI0_CQPAUSE_CQMASK_BUF0XOREN = 4096
,
MSPI0_CQPAUSE_CQMASK_DMACPL = 2048
, MSPI0_CQPAUSE_CQMASK_CMDCPL = 1024
, MSPI0_CQPAUSE_CQMASK_IOM1READY = 512
, MSPI0_CQPAUSE_CQMASK_IOM0READY = 256
,
MSPI0_CQPAUSE_CQMASK_SWFLAG7 = 128
, MSPI0_CQPAUSE_CQMASK_SWFLAG6 = 64
, MSPI0_CQPAUSE_CQMASK_SWFLAG5 = 32
, MSPI0_CQPAUSE_CQMASK_SWFLAG4 = 16
,
MSPI0_CQPAUSE_CQMASK_SWFLAG3 = 8
, MSPI0_CQPAUSE_CQMASK_SWFLAG2 = 4
, MSPI0_CQPAUSE_CQMASK_SWFLAG1 = 2
, MSPI0_CQPAUSE_CQMASK_SWFLAG0 = 1
} |
| |
| enum | MSPI0_STATXIPDMA_FLD32_Enum { MSPI0_STATXIPDMA_FLD32_XIPDMAIDLE = 2048
} |
| |
| enum | PDM0_CTRL_EN_Enum { PDM0_CTRL_EN_DIS = 0
, PDM0_CTRL_EN_EN = 1
} |
| |
| enum | PDM0_CTRL_PCMPACK_Enum { PDM0_CTRL_PCMPACK_DIS = 0
, PDM0_CTRL_PCMPACK_EN = 1
} |
| |
| enum | PDM0_CTRL_RSTB_Enum { PDM0_CTRL_RSTB_RESET = 0
, PDM0_CTRL_RSTB_NORMAL = 1
} |
| |
| enum | PDM0_CTRL_CLKEN_Enum { PDM0_CTRL_CLKEN_DIS = 0
, PDM0_CTRL_CLKEN_EN = 1
} |
| |
| enum | PDM0_CORECFG0_PGAR_Enum {
PDM0_CORECFG0_PGAR_M12_0DB = 0
, PDM0_CORECFG0_PGAR_M10_5DB = 1
, PDM0_CORECFG0_PGAR_M9_0DB = 2
, PDM0_CORECFG0_PGAR_M7_5DB = 3
,
PDM0_CORECFG0_PGAR_M6_0DB = 4
, PDM0_CORECFG0_PGAR_M4_5DB = 5
, PDM0_CORECFG0_PGAR_M3_0DB = 6
, PDM0_CORECFG0_PGAR_M1_5DB = 7
,
PDM0_CORECFG0_PGAR_0DB = 8
, PDM0_CORECFG0_PGAR_P1_5DB = 9
, PDM0_CORECFG0_PGAR_P3_0DB = 10
, PDM0_CORECFG0_PGAR_P4_5DB = 11
,
PDM0_CORECFG0_PGAR_P6_0DB = 12
, PDM0_CORECFG0_PGAR_P7_5DB = 13
, PDM0_CORECFG0_PGAR_P9_0DB = 14
, PDM0_CORECFG0_PGAR_P10_5DB = 15
,
PDM0_CORECFG0_PGAR_P12_0DB = 16
, PDM0_CORECFG0_PGAR_P13_5DB = 17
, PDM0_CORECFG0_PGAR_P15_0DB = 18
, PDM0_CORECFG0_PGAR_P16_5DB = 19
,
PDM0_CORECFG0_PGAR_P18_0DB = 20
, PDM0_CORECFG0_PGAR_P19_5DB = 21
, PDM0_CORECFG0_PGAR_P21_0DB = 22
, PDM0_CORECFG0_PGAR_P22_5DB = 23
,
PDM0_CORECFG0_PGAR_P24_0DB = 24
, PDM0_CORECFG0_PGAR_P25_5DB = 25
, PDM0_CORECFG0_PGAR_P27_0DB = 26
, PDM0_CORECFG0_PGAR_P28_5DB = 27
,
PDM0_CORECFG0_PGAR_P30_0DB = 28
, PDM0_CORECFG0_PGAR_P31_5DB = 29
, PDM0_CORECFG0_PGAR_P33_0DB = 30
, PDM0_CORECFG0_PGAR_P34_5DB = 31
} |
| |
| enum | PDM0_CORECFG0_PGAL_Enum {
PDM0_CORECFG0_PGAL_M10_5DB = 1
, PDM0_CORECFG0_PGAL_M9_0DB = 2
, PDM0_CORECFG0_PGAL_M7_5DB = 3
, PDM0_CORECFG0_PGAL_M6_0DB = 4
,
PDM0_CORECFG0_PGAL_M4_5DB = 5
, PDM0_CORECFG0_PGAL_M3_0DB = 6
, PDM0_CORECFG0_PGAL_M1_5DB = 7
, PDM0_CORECFG0_PGAL_0DB = 8
,
PDM0_CORECFG0_PGAL_P1_5DB = 9
, PDM0_CORECFG0_PGAL_P3_0DB = 10
, PDM0_CORECFG0_PGAL_P4_5DB = 11
, PDM0_CORECFG0_PGAL_P6_0DB = 12
,
PDM0_CORECFG0_PGAL_P7_5DB = 13
, PDM0_CORECFG0_PGAL_P9_0DB = 14
, PDM0_CORECFG0_PGAL_P10_5DB = 15
, PDM0_CORECFG0_PGAL_P12_0DB = 16
,
PDM0_CORECFG0_PGAL_P13_5DB = 17
, PDM0_CORECFG0_PGAL_P15_0DB = 18
, PDM0_CORECFG0_PGAL_P16_5DB = 19
, PDM0_CORECFG0_PGAL_P18_0DB = 20
,
PDM0_CORECFG0_PGAL_P19_5DB = 21
, PDM0_CORECFG0_PGAL_P21_0DB = 22
, PDM0_CORECFG0_PGAL_P22_5DB = 23
, PDM0_CORECFG0_PGAL_P24_0DB = 24
,
PDM0_CORECFG0_PGAL_P25_5DB = 25
, PDM0_CORECFG0_PGAL_P27_0DB = 26
, PDM0_CORECFG0_PGAL_P28_5DB = 27
, PDM0_CORECFG0_PGAL_P30_0DB = 28
,
PDM0_CORECFG0_PGAL_P31_5DB = 29
, PDM0_CORECFG0_PGAL_P33_0DB = 30
, PDM0_CORECFG0_PGAL_P34_5DB = 31
} |
| |
| enum | PDM0_CORECFG0_ADCHPD_Enum { PDM0_CORECFG0_ADCHPD_DIS = 0
, PDM0_CORECFG0_ADCHPD_EN = 1
} |
| |
| enum | PDM0_CORECFG0_SCYCLES_Enum {
PDM0_CORECFG0_SCYCLES_0CYCLES = 0
, PDM0_CORECFG0_SCYCLES_1CYCLES = 1
, PDM0_CORECFG0_SCYCLES_2CYCLES = 2
, PDM0_CORECFG0_SCYCLES_3CYCLES = 3
,
PDM0_CORECFG0_SCYCLES_4CYCLES = 4
, PDM0_CORECFG0_SCYCLES_5CYCLES = 5
, PDM0_CORECFG0_SCYCLES_6CYCLES = 6
, PDM0_CORECFG0_SCYCLES_7CYCLES = 7
} |
| |
| enum | PDM0_CORECFG0_LRSWAP_Enum { PDM0_CORECFG0_LRSWAP_DIS = 0
, PDM0_CORECFG0_LRSWAP_EN = 1
} |
| |
| enum | PDM0_CORECFG1_SELSTEP_Enum { PDM0_CORECFG1_SELSTEP_0_13DB = 0
, PDM0_CORECFG1_SELSTEP_0_26DB = 1
} |
| |
| enum | PDM0_CORECFG1_CKODLY_Enum {
PDM0_CORECFG1_CKODLY_0CYCLES = 0
, PDM0_CORECFG1_CKODLY_1CYCLES = 1
, PDM0_CORECFG1_CKODLY_2CYCLES = 2
, PDM0_CORECFG1_CKODLY_3CYCLES = 3
,
PDM0_CORECFG1_CKODLY_4CYCLES = 4
, PDM0_CORECFG1_CKODLY_5CYCLES = 5
, PDM0_CORECFG1_CKODLY_6CYCLES = 6
, PDM0_CORECFG1_CKODLY_7CYCLES = 7
} |
| |
| enum | PDM0_CORECFG1_PCMCHSET_Enum { PDM0_CORECFG1_PCMCHSET_CHANDIS = 0
, PDM0_CORECFG1_PCMCHSET_MONOL = 1
, PDM0_CORECFG1_PCMCHSET_MONOR = 2
, PDM0_CORECFG1_PCMCHSET_STEREO = 3
} |
| |
| enum | PDM0_DMACFG_DMAPRI_Enum { PDM0_DMACFG_DMAPRI_LOW = 0
, PDM0_DMACFG_DMAPRI_HIGH = 1
} |
| |
| enum | PDM0_DMACFG_DMADIR_Enum { PDM0_DMACFG_DMADIR_P2M = 0
, PDM0_DMACFG_DMADIR_M2P = 1
} |
| |
| enum | PDM0_DMACFG_DMAEN_Enum { PDM0_DMACFG_DMAEN_DIS = 0
, PDM0_DMACFG_DMAEN_EN = 1
} |
| |
| enum | PWRCTRL_MCUPERFREQ_MCUPERFSTATUS_Enum { PWRCTRL_MCUPERFREQ_MCUPERFSTATUS_ULP = 0
, PWRCTRL_MCUPERFREQ_MCUPERFSTATUS_LP = 1
, PWRCTRL_MCUPERFREQ_MCUPERFSTATUS_HP = 2
} |
| |
| enum | PWRCTRL_MCUPERFREQ_MCUPERFREQ_Enum { PWRCTRL_MCUPERFREQ_MCUPERFREQ_ULP = 0
, PWRCTRL_MCUPERFREQ_MCUPERFREQ_LP = 1
, PWRCTRL_MCUPERFREQ_MCUPERFREQ_HP = 2
} |
| |
| enum | PWRCTRL_DEVPWREN_PWRENI3C1_Enum { PWRCTRL_DEVPWREN_PWRENI3C1_EN = 1
, PWRCTRL_DEVPWREN_PWRENI3C1_DIS = 0
} |
| |
| enum | PWRCTRL_DEVPWREN_PWRENI3C0_Enum { PWRCTRL_DEVPWREN_PWRENI3C0_EN = 1
, PWRCTRL_DEVPWREN_PWRENI3C0_DIS = 0
} |
| |
| enum | PWRCTRL_DEVPWREN_PWRENDBG_Enum { PWRCTRL_DEVPWREN_PWRENDBG_EN = 1
, PWRCTRL_DEVPWREN_PWRENDBG_DIS = 0
} |
| |
| enum | PWRCTRL_DEVPWREN_PWRENUSBPHY_Enum { PWRCTRL_DEVPWREN_PWRENUSBPHY_EN = 1
, PWRCTRL_DEVPWREN_PWRENUSBPHY_DIS = 0
} |
| |
| enum | PWRCTRL_DEVPWREN_PWRENUSB_Enum { PWRCTRL_DEVPWREN_PWRENUSB_EN = 1
, PWRCTRL_DEVPWREN_PWRENUSB_DIS = 0
} |
| |
| enum | PWRCTRL_DEVPWREN_PWRENSDIO_Enum { PWRCTRL_DEVPWREN_PWRENSDIO_EN = 1
, PWRCTRL_DEVPWREN_PWRENSDIO_DIS = 0
} |
| |
| enum | PWRCTRL_DEVPWREN_PWRENCRYPTO_Enum { PWRCTRL_DEVPWREN_PWRENCRYPTO_EN = 1
, PWRCTRL_DEVPWREN_PWRENCRYPTO_DIS = 0
} |
| |
| enum | PWRCTRL_DEVPWREN_PWRENDISPPHY_Enum { PWRCTRL_DEVPWREN_PWRENDISPPHY_EN = 1
, PWRCTRL_DEVPWREN_PWRENDISPPHY_DIS = 0
} |
| |
| enum | PWRCTRL_DEVPWREN_PWRENDISP_Enum { PWRCTRL_DEVPWREN_PWRENDISP_EN = 1
, PWRCTRL_DEVPWREN_PWRENDISP_DIS = 0
} |
| |
| enum | PWRCTRL_DEVPWREN_PWRENGFX_Enum { PWRCTRL_DEVPWREN_PWRENGFX_EN = 1
, PWRCTRL_DEVPWREN_PWRENGFX_DIS = 0
} |
| |
| enum | PWRCTRL_DEVPWREN_PWRENMSPI2_Enum { PWRCTRL_DEVPWREN_PWRENMSPI2_EN = 1
, PWRCTRL_DEVPWREN_PWRENMSPI2_DIS = 0
} |
| |
| enum | PWRCTRL_DEVPWREN_PWRENMSPI1_Enum { PWRCTRL_DEVPWREN_PWRENMSPI1_EN = 1
, PWRCTRL_DEVPWREN_PWRENMSPI1_DIS = 0
} |
| |
| enum | PWRCTRL_DEVPWREN_PWRENMSPI0_Enum { PWRCTRL_DEVPWREN_PWRENMSPI0_EN = 1
, PWRCTRL_DEVPWREN_PWRENMSPI0_DIS = 0
} |
| |
| enum | PWRCTRL_DEVPWREN_PWRENADC_Enum { PWRCTRL_DEVPWREN_PWRENADC_EN = 1
, PWRCTRL_DEVPWREN_PWRENADC_DIS = 0
} |
| |
| enum | PWRCTRL_DEVPWREN_PWRENUART3_Enum { PWRCTRL_DEVPWREN_PWRENUART3_EN = 1
, PWRCTRL_DEVPWREN_PWRENUART3_DIS = 0
} |
| |
| enum | PWRCTRL_DEVPWREN_PWRENUART2_Enum { PWRCTRL_DEVPWREN_PWRENUART2_EN = 1
, PWRCTRL_DEVPWREN_PWRENUART2_DIS = 0
} |
| |
| enum | PWRCTRL_DEVPWREN_PWRENUART1_Enum { PWRCTRL_DEVPWREN_PWRENUART1_EN = 1
, PWRCTRL_DEVPWREN_PWRENUART1_DIS = 0
} |
| |
| enum | PWRCTRL_DEVPWREN_PWRENUART0_Enum { PWRCTRL_DEVPWREN_PWRENUART0_EN = 1
, PWRCTRL_DEVPWREN_PWRENUART0_DIS = 0
} |
| |
| enum | PWRCTRL_DEVPWREN_PWRENIOM7_Enum { PWRCTRL_DEVPWREN_PWRENIOM7_EN = 1
, PWRCTRL_DEVPWREN_PWRENIOM7_DIS = 0
} |
| |
| enum | PWRCTRL_DEVPWREN_PWRENIOM6_Enum { PWRCTRL_DEVPWREN_PWRENIOM6_EN = 1
, PWRCTRL_DEVPWREN_PWRENIOM6_DIS = 0
} |
| |
| enum | PWRCTRL_DEVPWREN_PWRENIOM5_Enum { PWRCTRL_DEVPWREN_PWRENIOM5_EN = 1
, PWRCTRL_DEVPWREN_PWRENIOM5_DIS = 0
} |
| |
| enum | PWRCTRL_DEVPWREN_PWRENIOM4_Enum { PWRCTRL_DEVPWREN_PWRENIOM4_EN = 1
, PWRCTRL_DEVPWREN_PWRENIOM4_DIS = 0
} |
| |
| enum | PWRCTRL_DEVPWREN_PWRENIOM3_Enum { PWRCTRL_DEVPWREN_PWRENIOM3_EN = 1
, PWRCTRL_DEVPWREN_PWRENIOM3_DIS = 0
} |
| |
| enum | PWRCTRL_DEVPWREN_PWRENIOM2_Enum { PWRCTRL_DEVPWREN_PWRENIOM2_EN = 1
, PWRCTRL_DEVPWREN_PWRENIOM2_DIS = 0
} |
| |
| enum | PWRCTRL_DEVPWREN_PWRENIOM1_Enum { PWRCTRL_DEVPWREN_PWRENIOM1_EN = 1
, PWRCTRL_DEVPWREN_PWRENIOM1_DIS = 0
} |
| |
| enum | PWRCTRL_DEVPWREN_PWRENIOM0_Enum { PWRCTRL_DEVPWREN_PWRENIOM0_EN = 1
, PWRCTRL_DEVPWREN_PWRENIOM0_DIS = 0
} |
| |
| enum | PWRCTRL_DEVPWREN_PWRENIOS_Enum { PWRCTRL_DEVPWREN_PWRENIOS_EN = 1
, PWRCTRL_DEVPWREN_PWRENIOS_DIS = 0
} |
| |
| enum | PWRCTRL_DEVPWRSTATUS_PWRSTI3C1_Enum { PWRCTRL_DEVPWRSTATUS_PWRSTI3C1_ON = 1
, PWRCTRL_DEVPWRSTATUS_PWRSTI3C1_OFF = 0
} |
| |
| enum | PWRCTRL_DEVPWRSTATUS_PWRSTI3C0_Enum { PWRCTRL_DEVPWRSTATUS_PWRSTI3C0_ON = 1
, PWRCTRL_DEVPWRSTATUS_PWRSTI3C0_OFF = 0
} |
| |
| enum | PWRCTRL_DEVPWRSTATUS_PWRSTDBG_Enum { PWRCTRL_DEVPWRSTATUS_PWRSTDBG_ON = 1
, PWRCTRL_DEVPWRSTATUS_PWRSTDBG_OFF = 0
} |
| |
| enum | PWRCTRL_DEVPWRSTATUS_PWRSTUSBPHY_Enum { PWRCTRL_DEVPWRSTATUS_PWRSTUSBPHY_ON = 1
, PWRCTRL_DEVPWRSTATUS_PWRSTUSBPHY_OFF = 0
} |
| |
| enum | PWRCTRL_DEVPWRSTATUS_PWRSTUSB_Enum { PWRCTRL_DEVPWRSTATUS_PWRSTUSB_ON = 1
, PWRCTRL_DEVPWRSTATUS_PWRSTUSB_OFF = 0
} |
| |
| enum | PWRCTRL_DEVPWRSTATUS_PWRSTSDIO_Enum { PWRCTRL_DEVPWRSTATUS_PWRSTSDIO_ON = 1
, PWRCTRL_DEVPWRSTATUS_PWRSTSDIO_OFF = 0
} |
| |
| enum | PWRCTRL_DEVPWRSTATUS_PWRSTCRYPTO_Enum { PWRCTRL_DEVPWRSTATUS_PWRSTCRYPTO_ON = 1
, PWRCTRL_DEVPWRSTATUS_PWRSTCRYPTO_OFF = 0
} |
| |
| enum | PWRCTRL_DEVPWRSTATUS_PWRSTDISPPHY_Enum { PWRCTRL_DEVPWRSTATUS_PWRSTDISPPHY_ON = 1
, PWRCTRL_DEVPWRSTATUS_PWRSTDISPPHY_OFF = 0
} |
| |
| enum | PWRCTRL_DEVPWRSTATUS_PWRSTDISP_Enum { PWRCTRL_DEVPWRSTATUS_PWRSTDISP_ON = 1
, PWRCTRL_DEVPWRSTATUS_PWRSTDISP_OFF = 0
} |
| |
| enum | PWRCTRL_DEVPWRSTATUS_PWRSTGFX_Enum { PWRCTRL_DEVPWRSTATUS_PWRSTGFX_ON = 1
, PWRCTRL_DEVPWRSTATUS_PWRSTGFX_OFF = 0
} |
| |
| enum | PWRCTRL_DEVPWRSTATUS_PWRSTMSPI2_Enum { PWRCTRL_DEVPWRSTATUS_PWRSTMSPI2_ON = 1
, PWRCTRL_DEVPWRSTATUS_PWRSTMSPI2_OFF = 0
} |
| |
| enum | PWRCTRL_DEVPWRSTATUS_PWRSTMSPI1_Enum { PWRCTRL_DEVPWRSTATUS_PWRSTMSPI1_ON = 1
, PWRCTRL_DEVPWRSTATUS_PWRSTMSPI1_OFF = 0
} |
| |
| enum | PWRCTRL_DEVPWRSTATUS_PWRSTMSPI0_Enum { PWRCTRL_DEVPWRSTATUS_PWRSTMSPI0_ON = 1
, PWRCTRL_DEVPWRSTATUS_PWRSTMSPI0_OFF = 0
} |
| |
| enum | PWRCTRL_DEVPWRSTATUS_PWRSTADC_Enum { PWRCTRL_DEVPWRSTATUS_PWRSTADC_ON = 1
, PWRCTRL_DEVPWRSTATUS_PWRSTADC_OFF = 0
} |
| |
| enum | PWRCTRL_DEVPWRSTATUS_PWRSTUART3_Enum { PWRCTRL_DEVPWRSTATUS_PWRSTUART3_ON = 1
, PWRCTRL_DEVPWRSTATUS_PWRSTUART3_OFF = 0
} |
| |
| enum | PWRCTRL_DEVPWRSTATUS_PWRSTUART2_Enum { PWRCTRL_DEVPWRSTATUS_PWRSTUART2_ON = 1
, PWRCTRL_DEVPWRSTATUS_PWRSTUART2_OFF = 0
} |
| |
| enum | PWRCTRL_DEVPWRSTATUS_PWRSTUART1_Enum { PWRCTRL_DEVPWRSTATUS_PWRSTUART1_ON = 1
, PWRCTRL_DEVPWRSTATUS_PWRSTUART1_OFF = 0
} |
| |
| enum | PWRCTRL_DEVPWRSTATUS_PWRSTUART0_Enum { PWRCTRL_DEVPWRSTATUS_PWRSTUART0_ON = 1
, PWRCTRL_DEVPWRSTATUS_PWRSTUART0_OFF = 0
} |
| |
| enum | PWRCTRL_DEVPWRSTATUS_PWRSTIOM7_Enum { PWRCTRL_DEVPWRSTATUS_PWRSTIOM7_ON = 1
, PWRCTRL_DEVPWRSTATUS_PWRSTIOM7_OFF = 0
} |
| |
| enum | PWRCTRL_DEVPWRSTATUS_PWRSTIOM6_Enum { PWRCTRL_DEVPWRSTATUS_PWRSTIOM6_ON = 1
, PWRCTRL_DEVPWRSTATUS_PWRSTIOM6_OFF = 0
} |
| |
| enum | PWRCTRL_DEVPWRSTATUS_PWRSTIOM5_Enum { PWRCTRL_DEVPWRSTATUS_PWRSTIOM5_ON = 1
, PWRCTRL_DEVPWRSTATUS_PWRSTIOM5_OFF = 0
} |
| |
| enum | PWRCTRL_DEVPWRSTATUS_PWRSTIOM4_Enum { PWRCTRL_DEVPWRSTATUS_PWRSTIOM4_ON = 1
, PWRCTRL_DEVPWRSTATUS_PWRSTIOM4_OFF = 0
} |
| |
| enum | PWRCTRL_DEVPWRSTATUS_PWRSTIOM3_Enum { PWRCTRL_DEVPWRSTATUS_PWRSTIOM3_ON = 1
, PWRCTRL_DEVPWRSTATUS_PWRSTIOM3_OFF = 0
} |
| |
| enum | PWRCTRL_DEVPWRSTATUS_PWRSTIOM2_Enum { PWRCTRL_DEVPWRSTATUS_PWRSTIOM2_ON = 1
, PWRCTRL_DEVPWRSTATUS_PWRSTIOM2_OFF = 0
} |
| |
| enum | PWRCTRL_DEVPWRSTATUS_PWRSTIOM1_Enum { PWRCTRL_DEVPWRSTATUS_PWRSTIOM1_ON = 1
, PWRCTRL_DEVPWRSTATUS_PWRSTIOM1_OFF = 0
} |
| |
| enum | PWRCTRL_DEVPWRSTATUS_PWRSTIOM0_Enum { PWRCTRL_DEVPWRSTATUS_PWRSTIOM0_ON = 1
, PWRCTRL_DEVPWRSTATUS_PWRSTIOM0_OFF = 0
} |
| |
| enum | PWRCTRL_DEVPWRSTATUS_PWRSTIOS_Enum { PWRCTRL_DEVPWRSTATUS_PWRSTIOS_ON = 1
, PWRCTRL_DEVPWRSTATUS_PWRSTIOS_OFF = 0
} |
| |
| enum | PWRCTRL_AUDSSPWREN_PWRENDSPA_Enum { PWRCTRL_AUDSSPWREN_PWRENDSPA_EN = 1
, PWRCTRL_AUDSSPWREN_PWRENDSPA_DIS = 0
} |
| |
| enum | PWRCTRL_AUDSSPWREN_PWRENAUDADC_Enum { PWRCTRL_AUDSSPWREN_PWRENAUDADC_EN = 1
, PWRCTRL_AUDSSPWREN_PWRENAUDADC_DIS = 0
} |
| |
| enum | PWRCTRL_AUDSSPWREN_PWRENI2S1_Enum { PWRCTRL_AUDSSPWREN_PWRENI2S1_EN = 1
, PWRCTRL_AUDSSPWREN_PWRENI2S1_DIS = 0
} |
| |
| enum | PWRCTRL_AUDSSPWREN_PWRENI2S0_Enum { PWRCTRL_AUDSSPWREN_PWRENI2S0_EN = 1
, PWRCTRL_AUDSSPWREN_PWRENI2S0_DIS = 0
} |
| |
| enum | PWRCTRL_AUDSSPWREN_PWRENPDM3_Enum { PWRCTRL_AUDSSPWREN_PWRENPDM3_EN = 1
, PWRCTRL_AUDSSPWREN_PWRENPDM3_DIS = 0
} |
| |
| enum | PWRCTRL_AUDSSPWREN_PWRENPDM2_Enum { PWRCTRL_AUDSSPWREN_PWRENPDM2_EN = 1
, PWRCTRL_AUDSSPWREN_PWRENPDM2_DIS = 0
} |
| |
| enum | PWRCTRL_AUDSSPWREN_PWRENPDM1_Enum { PWRCTRL_AUDSSPWREN_PWRENPDM1_EN = 1
, PWRCTRL_AUDSSPWREN_PWRENPDM1_DIS = 0
} |
| |
| enum | PWRCTRL_AUDSSPWREN_PWRENPDM0_Enum { PWRCTRL_AUDSSPWREN_PWRENPDM0_EN = 1
, PWRCTRL_AUDSSPWREN_PWRENPDM0_DIS = 0
} |
| |
| enum | PWRCTRL_AUDSSPWREN_PWRENAUDPB_Enum { PWRCTRL_AUDSSPWREN_PWRENAUDPB_EN = 1
, PWRCTRL_AUDSSPWREN_PWRENAUDPB_DIS = 0
} |
| |
| enum | PWRCTRL_AUDSSPWREN_PWRENAUDREC_Enum { PWRCTRL_AUDSSPWREN_PWRENAUDREC_EN = 1
, PWRCTRL_AUDSSPWREN_PWRENAUDREC_DIS = 0
} |
| |
| enum | PWRCTRL_AUDSSPWRSTATUS_PWRSTDSPA_Enum { PWRCTRL_AUDSSPWRSTATUS_PWRSTDSPA_ON = 1
, PWRCTRL_AUDSSPWRSTATUS_PWRSTDSPA_OFF = 0
} |
| |
| enum | PWRCTRL_AUDSSPWRSTATUS_PWRSTAUDADC_Enum { PWRCTRL_AUDSSPWRSTATUS_PWRSTAUDADC_ON = 1
, PWRCTRL_AUDSSPWRSTATUS_PWRSTAUDADC_OFF = 0
} |
| |
| enum | PWRCTRL_AUDSSPWRSTATUS_PWRSTI2S1_Enum { PWRCTRL_AUDSSPWRSTATUS_PWRSTI2S1_ON = 1
, PWRCTRL_AUDSSPWRSTATUS_PWRSTI2S1_OFF = 0
} |
| |
| enum | PWRCTRL_AUDSSPWRSTATUS_PWRSTI2S0_Enum { PWRCTRL_AUDSSPWRSTATUS_PWRSTI2S0_ON = 1
, PWRCTRL_AUDSSPWRSTATUS_PWRSTI2S0_OFF = 0
} |
| |
| enum | PWRCTRL_AUDSSPWRSTATUS_PWRSTPDM3_Enum { PWRCTRL_AUDSSPWRSTATUS_PWRSTPDM3_ON = 1
, PWRCTRL_AUDSSPWRSTATUS_PWRSTPDM3_OFF = 0
} |
| |
| enum | PWRCTRL_AUDSSPWRSTATUS_PWRSTPDM2_Enum { PWRCTRL_AUDSSPWRSTATUS_PWRSTPDM2_ON = 1
, PWRCTRL_AUDSSPWRSTATUS_PWRSTPDM2_OFF = 0
} |
| |
| enum | PWRCTRL_AUDSSPWRSTATUS_PWRSTPDM1_Enum { PWRCTRL_AUDSSPWRSTATUS_PWRSTPDM1_ON = 1
, PWRCTRL_AUDSSPWRSTATUS_PWRSTPDM1_OFF = 0
} |
| |
| enum | PWRCTRL_AUDSSPWRSTATUS_PWRSTPDM0_Enum { PWRCTRL_AUDSSPWRSTATUS_PWRSTPDM0_ON = 1
, PWRCTRL_AUDSSPWRSTATUS_PWRSTPDM0_OFF = 0
} |
| |
| enum | PWRCTRL_AUDSSPWRSTATUS_PWRSTAUDPB_Enum { PWRCTRL_AUDSSPWRSTATUS_PWRSTAUDPB_ON = 1
, PWRCTRL_AUDSSPWRSTATUS_PWRSTAUDPB_OFF = 0
} |
| |
| enum | PWRCTRL_AUDSSPWRSTATUS_PWRSTAUDREC_Enum { PWRCTRL_AUDSSPWRSTATUS_PWRSTAUDREC_ON = 1
, PWRCTRL_AUDSSPWRSTATUS_PWRSTAUDREC_OFF = 0
} |
| |
| enum | PWRCTRL_MEMPWREN_PWRENCACHEB2_Enum { PWRCTRL_MEMPWREN_PWRENCACHEB2_EN = 1
, PWRCTRL_MEMPWREN_PWRENCACHEB2_DIS = 0
} |
| |
| enum | PWRCTRL_MEMPWREN_PWRENCACHEB0_Enum { PWRCTRL_MEMPWREN_PWRENCACHEB0_EN = 1
, PWRCTRL_MEMPWREN_PWRENCACHEB0_DIS = 0
} |
| |
| enum | PWRCTRL_MEMPWREN_PWRENNVM0_Enum { PWRCTRL_MEMPWREN_PWRENNVM0_EN = 1
, PWRCTRL_MEMPWREN_PWRENNVM0_DIS = 0
} |
| |
| enum | PWRCTRL_MEMPWREN_PWRENDTCM_Enum { PWRCTRL_MEMPWREN_PWRENDTCM_NONE = 0
, PWRCTRL_MEMPWREN_PWRENDTCM_TCM8K = 1
, PWRCTRL_MEMPWREN_PWRENDTCM_TCM128K = 3
, PWRCTRL_MEMPWREN_PWRENDTCM_TCM384K = 7
} |
| |
| enum | PWRCTRL_MEMPWRSTATUS_PWRSTDTCM_Enum { PWRCTRL_MEMPWRSTATUS_PWRSTDTCM_NONE = 0
, PWRCTRL_MEMPWRSTATUS_PWRSTDTCM_TCM8K = 1
, PWRCTRL_MEMPWRSTATUS_PWRSTDTCM_TCM128K = 3
, PWRCTRL_MEMPWRSTATUS_PWRSTDTCM_TCM384K = 7
} |
| |
| enum | PWRCTRL_MEMRETCFG_CACHEPWDSLP_Enum { PWRCTRL_MEMRETCFG_CACHEPWDSLP_EN = 1
, PWRCTRL_MEMRETCFG_CACHEPWDSLP_DIS = 0
} |
| |
| enum | PWRCTRL_MEMRETCFG_NVM0PWDSLP_Enum { PWRCTRL_MEMRETCFG_NVM0PWDSLP_EN = 1
, PWRCTRL_MEMRETCFG_NVM0PWDSLP_DIS = 0
} |
| |
| enum | PWRCTRL_MEMRETCFG_DTCMPWDSLP_Enum {
PWRCTRL_MEMRETCFG_DTCMPWDSLP_NONE = 0
, PWRCTRL_MEMRETCFG_DTCMPWDSLP_GROUP0DTCM0 = 1
, PWRCTRL_MEMRETCFG_DTCMPWDSLP_GROUP0DTCM1 = 2
, PWRCTRL_MEMRETCFG_DTCMPWDSLP_GROUP0 = 3
,
PWRCTRL_MEMRETCFG_DTCMPWDSLP_ALLBUTGROUP0DTCM0 = 6
, PWRCTRL_MEMRETCFG_DTCMPWDSLP_GROUP1 = 4
, PWRCTRL_MEMRETCFG_DTCMPWDSLP_ALL = 7
} |
| |
| enum | PWRCTRL_SSRAMPWREN_PWRENSSRAM_Enum { PWRCTRL_SSRAMPWREN_PWRENSSRAM_NONE = 0
, PWRCTRL_SSRAMPWREN_PWRENSSRAM_GROUP0 = 1
, PWRCTRL_SSRAMPWREN_PWRENSSRAM_GROUP1 = 2
, PWRCTRL_SSRAMPWREN_PWRENSSRAM_ALL = 3
} |
| |
| enum | PWRCTRL_SSRAMRETCFG_SSRAMPWDSLP_Enum { PWRCTRL_SSRAMRETCFG_SSRAMPWDSLP_NONE = 0
, PWRCTRL_SSRAMRETCFG_SSRAMPWDSLP_GROUP0 = 1
, PWRCTRL_SSRAMRETCFG_SSRAMPWDSLP_GROUP1 = 2
, PWRCTRL_SSRAMRETCFG_SSRAMPWDSLP_ALL = 3
} |
| |
| enum | PWRCTRL_DEVPWREVENTEN_AUDEVEN_Enum { PWRCTRL_DEVPWREVENTEN_AUDEVEN_EN = 1
, PWRCTRL_DEVPWREVENTEN_AUDEVEN_DIS = 0
} |
| |
| enum | PWRCTRL_DEVPWREVENTEN_MSPIEVEN_Enum { PWRCTRL_DEVPWREVENTEN_MSPIEVEN_EN = 1
, PWRCTRL_DEVPWREVENTEN_MSPIEVEN_DIS = 0
} |
| |
| enum | PWRCTRL_DEVPWREVENTEN_ADCEVEN_Enum { PWRCTRL_DEVPWREVENTEN_ADCEVEN_EN = 1
, PWRCTRL_DEVPWREVENTEN_ADCEVEN_DIS = 0
} |
| |
| enum | PWRCTRL_DEVPWREVENTEN_HCPCEVEN_Enum { PWRCTRL_DEVPWREVENTEN_HCPCEVEN_EN = 1
, PWRCTRL_DEVPWREVENTEN_HCPCEVEN_DIS = 0
} |
| |
| enum | PWRCTRL_DEVPWREVENTEN_HCPBEVEN_Enum { PWRCTRL_DEVPWREVENTEN_HCPBEVEN_EN = 1
, PWRCTRL_DEVPWREVENTEN_HCPBEVEN_DIS = 0
} |
| |
| enum | PWRCTRL_DEVPWREVENTEN_HCPAEVEN_Enum { PWRCTRL_DEVPWREVENTEN_HCPAEVEN_EN = 1
, PWRCTRL_DEVPWREVENTEN_HCPAEVEN_DIS = 0
} |
| |
| enum | PWRCTRL_DEVPWREVENTEN_MCUHEVEN_Enum { PWRCTRL_DEVPWREVENTEN_MCUHEVEN_EN = 1
, PWRCTRL_DEVPWREVENTEN_MCUHEVEN_DIS = 0
} |
| |
| enum | PWRCTRL_DEVPWREVENTEN_MCULEVEN_Enum { PWRCTRL_DEVPWREVENTEN_MCULEVEN_EN = 1
, PWRCTRL_DEVPWREVENTEN_MCULEVEN_DIS = 0
} |
| |
| enum | PWRCTRL_MEMPWREVENTEN_CACHEB2EN_Enum { PWRCTRL_MEMPWREVENTEN_CACHEB2EN_EN = 1
, PWRCTRL_MEMPWREVENTEN_CACHEB2EN_DIS = 0
} |
| |
| enum | PWRCTRL_MEMPWREVENTEN_CACHEB0EN_Enum { PWRCTRL_MEMPWREVENTEN_CACHEB0EN_EN = 1
, PWRCTRL_MEMPWREVENTEN_CACHEB0EN_DIS = 0
} |
| |
| enum | PWRCTRL_MEMPWREVENTEN_NVM0EN_Enum { PWRCTRL_MEMPWREVENTEN_NVM0EN_EN = 1
, PWRCTRL_MEMPWREVENTEN_NVM0EN_DIS = 0
} |
| |
| enum | PWRCTRL_MEMPWREVENTEN_DTCMEN_Enum {
PWRCTRL_MEMPWREVENTEN_DTCMEN_NONE = 0
, PWRCTRL_MEMPWREVENTEN_DTCMEN_GROUP0DTCM0EN = 1
, PWRCTRL_MEMPWREVENTEN_DTCMEN_GROUP0DTCM1EN = 2
, PWRCTRL_MEMPWREVENTEN_DTCMEN_GROUP0EN = 3
,
PWRCTRL_MEMPWREVENTEN_DTCMEN_GROUP1EN = 4
, PWRCTRL_MEMPWREVENTEN_DTCMEN_ALL = 7
} |
| |
| enum | PWRCTRL_MMSOVERRIDE_MMSOVRSSRAMRETGFX_Enum { PWRCTRL_MMSOVERRIDE_MMSOVRSSRAMRETGFX_ALWAYSON = 1
, PWRCTRL_MMSOVERRIDE_MMSOVRSSRAMRETGFX_PGSTATE = 0
} |
| |
| enum | PWRCTRL_MMSOVERRIDE_MMSOVRSSRAMRETDISP_Enum { PWRCTRL_MMSOVERRIDE_MMSOVRSSRAMRETDISP_ALWAYSON = 1
, PWRCTRL_MMSOVERRIDE_MMSOVRSSRAMRETDISP_PGSTATE = 0
} |
| |
| enum | PWRCTRL_MMSOVERRIDE_MMSOVRDSPRAMRETGFX_Enum { PWRCTRL_MMSOVERRIDE_MMSOVRDSPRAMRETGFX_ALWAYSON = 1
, PWRCTRL_MMSOVERRIDE_MMSOVRDSPRAMRETGFX_PGSTATE = 0
} |
| |
| enum | PWRCTRL_MMSOVERRIDE_MMSOVRDSPRAMRETDISP_Enum { PWRCTRL_MMSOVERRIDE_MMSOVRDSPRAMRETDISP_ALWAYSON = 1
, PWRCTRL_MMSOVERRIDE_MMSOVRDSPRAMRETDISP_PGSTATE = 0
} |
| |
| enum | PWRCTRL_MMSOVERRIDE_MMSOVRSSRAMGFX_Enum { PWRCTRL_MMSOVERRIDE_MMSOVRSSRAMGFX_NOGFX = 1
, PWRCTRL_MMSOVERRIDE_MMSOVRSSRAMGFX_PD_GFX = 0
} |
| |
| enum | PWRCTRL_MMSOVERRIDE_MMSOVRSSRAMDISP_Enum { PWRCTRL_MMSOVERRIDE_MMSOVRSSRAMDISP_NODISP = 1
, PWRCTRL_MMSOVERRIDE_MMSOVRSSRAMDISP_PD_DISP = 0
} |
| |
| enum | PWRCTRL_MMSOVERRIDE_MMSOVRMCULGFX_Enum { PWRCTRL_MMSOVERRIDE_MMSOVRMCULGFX_MCULON = 0
, PWRCTRL_MMSOVERRIDE_MMSOVRMCULGFX_MCULOFF = 1
} |
| |
| enum | PWRCTRL_MMSOVERRIDE_MMSOVRMCULDISP_Enum { PWRCTRL_MMSOVERRIDE_MMSOVRMCULDISP_MCULON = 0
, PWRCTRL_MMSOVERRIDE_MMSOVRMCULDISP_MCULOFF = 1
} |
| |
| enum | PWRCTRL_DSP0PWRCTRL_DSP0PCMRSTOR_Enum { PWRCTRL_DSP0PWRCTRL_DSP0PCMRSTOR_EN = 1
, PWRCTRL_DSP0PWRCTRL_DSP0PCMRSTOR_DIS = 0
} |
| |
| enum | PWRCTRL_DSP0PERFREQ_DSP0PERFSTATUS_Enum { PWRCTRL_DSP0PERFREQ_DSP0PERFSTATUS_ULP = 0
, PWRCTRL_DSP0PERFREQ_DSP0PERFSTATUS_LP = 1
, PWRCTRL_DSP0PERFREQ_DSP0PERFSTATUS_HP = 2
} |
| |
| enum | PWRCTRL_DSP0PERFREQ_DSP0PERFREQ_Enum { PWRCTRL_DSP0PERFREQ_DSP0PERFREQ_ULP = 0
, PWRCTRL_DSP0PERFREQ_DSP0PERFREQ_LP = 1
, PWRCTRL_DSP0PERFREQ_DSP0PERFREQ_HP = 2
} |
| |
| enum | PWRCTRL_DSP0MEMPWREN_PWRENDSP0ICACHE_Enum { PWRCTRL_DSP0MEMPWREN_PWRENDSP0ICACHE_OFF = 0
, PWRCTRL_DSP0MEMPWREN_PWRENDSP0ICACHE_ON = 1
} |
| |
| enum | PWRCTRL_DSP0MEMPWREN_PWRENDSP0RAM_Enum { PWRCTRL_DSP0MEMPWREN_PWRENDSP0RAM_OFF = 0
, PWRCTRL_DSP0MEMPWREN_PWRENDSP0RAM_ON = 1
} |
| |
| enum | PWRCTRL_DSP0MEMRETCFG_DSP0RAMACTGFX_Enum { PWRCTRL_DSP0MEMRETCFG_DSP0RAMACTGFX_WAKEONDEMAND = 0
, PWRCTRL_DSP0MEMRETCFG_DSP0RAMACTGFX_ACT = 1
} |
| |
| enum | PWRCTRL_DSP0MEMRETCFG_DSP0RAMACTDISP_Enum { PWRCTRL_DSP0MEMRETCFG_DSP0RAMACTDISP_WAKEONDEMAND = 0
, PWRCTRL_DSP0MEMRETCFG_DSP0RAMACTDISP_ACT = 1
} |
| |
| enum | PWRCTRL_DSP0MEMRETCFG_ICACHEPWDDSP0OFF_Enum { PWRCTRL_DSP0MEMRETCFG_ICACHEPWDDSP0OFF_RET = 0
, PWRCTRL_DSP0MEMRETCFG_ICACHEPWDDSP0OFF_PWD = 1
} |
| |
| enum | PWRCTRL_DSP0MEMRETCFG_DSP0RAMACTMCU_Enum { PWRCTRL_DSP0MEMRETCFG_DSP0RAMACTMCU_WAKEONDEMAND = 0
, PWRCTRL_DSP0MEMRETCFG_DSP0RAMACTMCU_ACT = 1
} |
| |
| enum | PWRCTRL_DSP0MEMRETCFG_RAMPWDDSP0OFF_Enum { PWRCTRL_DSP0MEMRETCFG_RAMPWDDSP0OFF_RET = 0
, PWRCTRL_DSP0MEMRETCFG_RAMPWDDSP0OFF_PWD = 1
} |
| |
| enum | PWRCTRL_DSP1PWRCTRL_DSP1PCMRSTOR_Enum { PWRCTRL_DSP1PWRCTRL_DSP1PCMRSTOR_EN = 1
, PWRCTRL_DSP1PWRCTRL_DSP1PCMRSTOR_DIS = 0
} |
| |
| enum | PWRCTRL_DSP1PERFREQ_DSP1PERFSTATUS_Enum { PWRCTRL_DSP1PERFREQ_DSP1PERFSTATUS_ULP = 0
, PWRCTRL_DSP1PERFREQ_DSP1PERFSTATUS_LP = 1
, PWRCTRL_DSP1PERFREQ_DSP1PERFSTATUS_HP = 2
} |
| |
| enum | PWRCTRL_DSP1PERFREQ_DSP1PERFREQ_Enum { PWRCTRL_DSP1PERFREQ_DSP1PERFREQ_ULP = 0
, PWRCTRL_DSP1PERFREQ_DSP1PERFREQ_LP = 1
, PWRCTRL_DSP1PERFREQ_DSP1PERFREQ_HP = 2
} |
| |
| enum | PWRCTRL_DSP1MEMPWREN_PWRENDSP1ICACHE_Enum { PWRCTRL_DSP1MEMPWREN_PWRENDSP1ICACHE_OFF = 0
, PWRCTRL_DSP1MEMPWREN_PWRENDSP1ICACHE_ON = 1
} |
| |
| enum | PWRCTRL_DSP1MEMPWREN_PWRENDSP1RAM_Enum { PWRCTRL_DSP1MEMPWREN_PWRENDSP1RAM_OFF = 0
, PWRCTRL_DSP1MEMPWREN_PWRENDSP1RAM_ON = 1
} |
| |
| enum | PWRCTRL_DSP1MEMRETCFG_DSP1RAMACTGFX_Enum { PWRCTRL_DSP1MEMRETCFG_DSP1RAMACTGFX_WAKEONDEMAND = 0
, PWRCTRL_DSP1MEMRETCFG_DSP1RAMACTGFX_ACT = 1
} |
| |
| enum | PWRCTRL_DSP1MEMRETCFG_DSP1RAMACTDISP_Enum { PWRCTRL_DSP1MEMRETCFG_DSP1RAMACTDISP_WAKEONDEMAND = 0
, PWRCTRL_DSP1MEMRETCFG_DSP1RAMACTDISP_ACT = 1
} |
| |
| enum | PWRCTRL_DSP1MEMRETCFG_ICACHEPWDDSP1OFF_Enum { PWRCTRL_DSP1MEMRETCFG_ICACHEPWDDSP1OFF_RET = 0
, PWRCTRL_DSP1MEMRETCFG_ICACHEPWDDSP1OFF_PWD = 1
} |
| |
| enum | PWRCTRL_DSP1MEMRETCFG_DSP1RAMACTMCU_Enum { PWRCTRL_DSP1MEMRETCFG_DSP1RAMACTMCU_WAKEONDEMAND = 0
, PWRCTRL_DSP1MEMRETCFG_DSP1RAMACTMCU_ACT = 1
} |
| |
| enum | PWRCTRL_DSP1MEMRETCFG_RAMPWDDSP1OFF_Enum { PWRCTRL_DSP1MEMRETCFG_RAMPWDDSP1OFF_RET = 0
, PWRCTRL_DSP1MEMRETCFG_RAMPWDDSP1OFF_PWD = 1
} |
| |
| enum | PWRCTRL_PWRACKOVR_PWRACKOVERRIDEDSPA_Enum { PWRCTRL_PWRACKOVR_PWRACKOVERRIDEDSPA_DEFAULT = 0
, PWRCTRL_PWRACKOVR_PWRACKOVERRIDEDSPA_SWOVRRIDE = 1
} |
| |
| enum | PWRCTRL_PWRACKOVR_PWRACKOVERRIDEUSBPHY_Enum { PWRCTRL_PWRACKOVR_PWRACKOVERRIDEUSBPHY_DEFAULT = 0
, PWRCTRL_PWRACKOVR_PWRACKOVERRIDEUSBPHY_SWOVRRIDE = 1
} |
| |
| enum | PWRCTRL_PWRACKOVR_PWRACKOVERRIDEUSB_Enum { PWRCTRL_PWRACKOVR_PWRACKOVERRIDEUSB_DEFAULT = 0
, PWRCTRL_PWRACKOVR_PWRACKOVERRIDEUSB_SWOVRRIDE = 1
} |
| |
| enum | PWRCTRL_PWRACKOVR_PWRACKOVERRIDESDIO_Enum { PWRCTRL_PWRACKOVR_PWRACKOVERRIDESDIO_DEFAULT = 0
, PWRCTRL_PWRACKOVR_PWRACKOVERRIDESDIO_SWOVRRIDE = 1
} |
| |
| enum | PWRCTRL_PWRACKOVR_PWRACKOVERRIDEMSPI_Enum { PWRCTRL_PWRACKOVR_PWRACKOVERRIDEMSPI_DEFAULT = 0
, PWRCTRL_PWRACKOVR_PWRACKOVERRIDEMSPI_SWOVRRIDE = 1
} |
| |
| enum | PWRCTRL_PWRACKOVR_PWRACKOVERRIDEMCUL_Enum { PWRCTRL_PWRACKOVR_PWRACKOVERRIDEMCUL_DEFAULT = 0
, PWRCTRL_PWRACKOVR_PWRACKOVERRIDEMCUL_SWOVRRIDE = 1
} |
| |
| enum | PWRCTRL_PWRACKOVR_PWRACKOVERRIDEIOS_Enum { PWRCTRL_PWRACKOVR_PWRACKOVERRIDEIOS_DEFAULT = 0
, PWRCTRL_PWRACKOVR_PWRACKOVERRIDEIOS_SWOVRRIDE = 1
} |
| |
| enum | PWRCTRL_PWRACKOVR_PWRACKOVERRIDEHCPC_Enum { PWRCTRL_PWRACKOVR_PWRACKOVERRIDEHCPC_DEFAULT = 0
, PWRCTRL_PWRACKOVR_PWRACKOVERRIDEHCPC_SWOVRRIDE = 1
} |
| |
| enum | PWRCTRL_PWRACKOVR_PWRACKOVERRIDEHCPB_Enum { PWRCTRL_PWRACKOVR_PWRACKOVERRIDEHCPB_DEFAULT = 0
, PWRCTRL_PWRACKOVR_PWRACKOVERRIDEHCPB_SWOVRRIDE = 1
} |
| |
| enum | PWRCTRL_PWRACKOVR_PWRACKOVERRIDEHCPA_Enum { PWRCTRL_PWRACKOVR_PWRACKOVERRIDEHCPA_DEFAULT = 0
, PWRCTRL_PWRACKOVR_PWRACKOVERRIDEHCPA_SWOVRRIDE = 1
} |
| |
| enum | PWRCTRL_PWRACKOVR_PWRACKOVERRIDEGFX_Enum { PWRCTRL_PWRACKOVR_PWRACKOVERRIDEGFX_DEFAULT = 0
, PWRCTRL_PWRACKOVR_PWRACKOVERRIDEGFX_SWOVRRIDE = 1
} |
| |
| enum | PWRCTRL_PWRACKOVR_PWRACKOVERRIDEDISPPHY_Enum { PWRCTRL_PWRACKOVR_PWRACKOVERRIDEDISPPHY_DEFAULT = 0
, PWRCTRL_PWRACKOVR_PWRACKOVERRIDEDISPPHY_SWOVRRIDE = 1
} |
| |
| enum | PWRCTRL_PWRACKOVR_PWRACKOVERRIDEDISP_Enum { PWRCTRL_PWRACKOVR_PWRACKOVERRIDEDISP_DEFAULT = 0
, PWRCTRL_PWRACKOVR_PWRACKOVERRIDEDISP_SWOVRRIDE = 1
} |
| |
| enum | PWRCTRL_PWRACKOVR_PWRACKOVERRIDEDBG_Enum { PWRCTRL_PWRACKOVR_PWRACKOVERRIDEDBG_DEFAULT = 0
, PWRCTRL_PWRACKOVR_PWRACKOVERRIDEDBG_SWOVRRIDE = 1
} |
| |
| enum | PWRCTRL_PWRACKOVR_PWRACKOVERRIDECRYPTO_Enum { PWRCTRL_PWRACKOVR_PWRACKOVERRIDECRYPTO_DEFAULT = 0
, PWRCTRL_PWRACKOVR_PWRACKOVERRIDECRYPTO_SWOVRRIDE = 1
} |
| |
| enum | PWRCTRL_PWRACKOVR_PWRACKOVERRIDEAUDADC_Enum { PWRCTRL_PWRACKOVR_PWRACKOVERRIDEAUDADC_DEFAULT = 0
, PWRCTRL_PWRACKOVR_PWRACKOVERRIDEAUDADC_SWOVRRIDE = 1
} |
| |
| enum | PWRCTRL_PWRACKOVR_PWRACKOVERRIDEAUD_Enum { PWRCTRL_PWRACKOVR_PWRACKOVERRIDEAUD_DEFAULT = 0
, PWRCTRL_PWRACKOVR_PWRACKOVERRIDEAUD_SWOVRRIDE = 1
} |
| |
| enum | PWRCTRL_PWRACKOVR_PWRACKOVERRIDEADC_Enum { PWRCTRL_PWRACKOVR_PWRACKOVERRIDEADC_DEFAULT = 0
, PWRCTRL_PWRACKOVR_PWRACKOVERRIDEADC_SWOVRRIDE = 1
} |
| |
| enum | PWRCTRL_VRCTRL_SIMOBUCKEN_Enum { PWRCTRL_VRCTRL_SIMOBUCKEN_EN = 1
, PWRCTRL_VRCTRL_SIMOBUCKEN_DIS = 0
} |
| |
| enum | PWRCTRL_VRSTATUS_SIMOBUCKST_Enum { PWRCTRL_VRSTATUS_SIMOBUCKST_OFF = 0
, PWRCTRL_VRSTATUS_SIMOBUCKST_LP = 2
, PWRCTRL_VRSTATUS_SIMOBUCKST_ACT = 3
} |
| |
| enum | PWRCTRL_VRSTATUS_MEMLDOST_Enum { PWRCTRL_VRSTATUS_MEMLDOST_OFF = 0
, PWRCTRL_VRSTATUS_MEMLDOST_LP = 2
, PWRCTRL_VRSTATUS_MEMLDOST_ACT = 3
} |
| |
| enum | PWRCTRL_VRSTATUS_CORELDOST_Enum { PWRCTRL_VRSTATUS_CORELDOST_OFF = 0
, PWRCTRL_VRSTATUS_CORELDOST_LP = 2
, PWRCTRL_VRSTATUS_CORELDOST_ACT = 3
} |
| |
| enum | PWRCTRL_SRAMCTRL_SRAMLIGHTSLEEP_Enum { PWRCTRL_SRAMCTRL_SRAMLIGHTSLEEP_ALL = 4095
, PWRCTRL_SRAMCTRL_SRAMLIGHTSLEEP_DIS = 0
} |
| |
| enum | PWRCTRL_SRAMCTRL_SRAMMASTERCLKGATE_Enum { PWRCTRL_SRAMCTRL_SRAMMASTERCLKGATE_EN = 1
, PWRCTRL_SRAMCTRL_SRAMMASTERCLKGATE_DIS = 0
} |
| |
| enum | PWRCTRL_SRAMCTRL_SRAMCLKGATE_Enum { PWRCTRL_SRAMCTRL_SRAMCLKGATE_EN = 1
, PWRCTRL_SRAMCTRL_SRAMCLKGATE_DIS = 0
} |
| |
| enum | PWRCTRL_EMONCFG0_EMONSEL0_Enum {
PWRCTRL_EMONCFG0_EMONSEL0_NEVER = 0
, PWRCTRL_EMONCFG0_EMONSEL0_ALWAYS = 1
, PWRCTRL_EMONCFG0_EMONSEL0_MCUSLEEP = 2
, PWRCTRL_EMONCFG0_EMONSEL0_MCUDEEPSLEEP = 3
,
PWRCTRL_EMONCFG0_EMONSEL0_DSP0ON = 4
, PWRCTRL_EMONCFG0_EMONSEL0_DSP1ON = 5
, PWRCTRL_EMONCFG0_EMONSEL0_ADCON = 6
, PWRCTRL_EMONCFG0_EMONSEL0_AUDPBON = 7
,
PWRCTRL_EMONCFG0_EMONSEL0_AUDRECON = 8
, PWRCTRL_EMONCFG0_EMONSEL0_I2S0ON = 9
, PWRCTRL_EMONCFG0_EMONSEL0_I2S1ON = 10
, PWRCTRL_EMONCFG0_EMONSEL0_PDM0ON = 11
,
PWRCTRL_EMONCFG0_EMONSEL0_PDM1ON = 12
, PWRCTRL_EMONCFG0_EMONSEL0_PDM2ON = 13
, PWRCTRL_EMONCFG0_EMONSEL0_PDM3ON = 14
, PWRCTRL_EMONCFG0_EMONSEL0_AUDADCON = 15
,
PWRCTRL_EMONCFG0_EMONSEL0_CRYPTOON = 16
, PWRCTRL_EMONCFG0_EMONSEL0_DBGON = 17
, PWRCTRL_EMONCFG0_EMONSEL0_DISPON = 18
, PWRCTRL_EMONCFG0_EMONSEL0_DISPPHYON = 19
,
PWRCTRL_EMONCFG0_EMONSEL0_DSPAON = 20
, PWRCTRL_EMONCFG0_EMONSEL0_GFXON = 21
, PWRCTRL_EMONCFG0_EMONSEL0_UART0ON = 22
, PWRCTRL_EMONCFG0_EMONSEL0_UART1ON = 23
,
PWRCTRL_EMONCFG0_EMONSEL0_UART2ON = 24
, PWRCTRL_EMONCFG0_EMONSEL0_UART3ON = 25
, PWRCTRL_EMONCFG0_EMONSEL0_IOM0ON = 26
, PWRCTRL_EMONCFG0_EMONSEL0_IOM1ON = 27
,
PWRCTRL_EMONCFG0_EMONSEL0_IOM2ON = 28
, PWRCTRL_EMONCFG0_EMONSEL0_IOM3ON = 29
, PWRCTRL_EMONCFG0_EMONSEL0_I3C0ON = 30
, PWRCTRL_EMONCFG0_EMONSEL0_I3C1ON = 31
,
PWRCTRL_EMONCFG0_EMONSEL0_IOM4ON = 32
, PWRCTRL_EMONCFG0_EMONSEL0_IOM5ON = 33
, PWRCTRL_EMONCFG0_EMONSEL0_IOM6ON = 34
, PWRCTRL_EMONCFG0_EMONSEL0_IOM7ON = 35
,
PWRCTRL_EMONCFG0_EMONSEL0_IOSON = 36
, PWRCTRL_EMONCFG0_EMONSEL0_MSPI0ON = 37
, PWRCTRL_EMONCFG0_EMONSEL0_MSPI1ON = 38
, PWRCTRL_EMONCFG0_EMONSEL0_MSPI2ON = 39
,
PWRCTRL_EMONCFG0_EMONSEL0_SDIOON = 40
, PWRCTRL_EMONCFG0_EMONSEL0_USBON = 41
, PWRCTRL_EMONCFG0_EMONSEL0_USBPHYON = 42
} |
| |
| enum | PWRCTRL_EMONCFG1_EMONSEL1_Enum {
PWRCTRL_EMONCFG1_EMONSEL1_NEVER = 0
, PWRCTRL_EMONCFG1_EMONSEL1_ALWAYS = 1
, PWRCTRL_EMONCFG1_EMONSEL1_MCUSLEEP = 2
, PWRCTRL_EMONCFG1_EMONSEL1_MCUDEEPSLEEP = 3
,
PWRCTRL_EMONCFG1_EMONSEL1_DSP0ON = 4
, PWRCTRL_EMONCFG1_EMONSEL1_DSP1ON = 5
, PWRCTRL_EMONCFG1_EMONSEL1_ADCON = 6
, PWRCTRL_EMONCFG1_EMONSEL1_AUDPBON = 7
,
PWRCTRL_EMONCFG1_EMONSEL1_AUDRECON = 8
, PWRCTRL_EMONCFG1_EMONSEL1_I2S0ON = 9
, PWRCTRL_EMONCFG1_EMONSEL1_I2S1ON = 10
, PWRCTRL_EMONCFG1_EMONSEL1_PDM0ON = 11
,
PWRCTRL_EMONCFG1_EMONSEL1_PDM1ON = 12
, PWRCTRL_EMONCFG1_EMONSEL1_PDM2ON = 13
, PWRCTRL_EMONCFG1_EMONSEL1_PDM3ON = 14
, PWRCTRL_EMONCFG1_EMONSEL1_AUDADCON = 15
,
PWRCTRL_EMONCFG1_EMONSEL1_CRYPTOON = 16
, PWRCTRL_EMONCFG1_EMONSEL1_DBGON = 17
, PWRCTRL_EMONCFG1_EMONSEL1_DISPON = 18
, PWRCTRL_EMONCFG1_EMONSEL1_DISPPHYON = 19
,
PWRCTRL_EMONCFG1_EMONSEL1_DSPAON = 20
, PWRCTRL_EMONCFG1_EMONSEL1_GFXON = 21
, PWRCTRL_EMONCFG1_EMONSEL1_UART0ON = 22
, PWRCTRL_EMONCFG1_EMONSEL1_UART1ON = 23
,
PWRCTRL_EMONCFG1_EMONSEL1_UART2ON = 24
, PWRCTRL_EMONCFG1_EMONSEL1_UART3ON = 25
, PWRCTRL_EMONCFG1_EMONSEL1_IOM0ON = 26
, PWRCTRL_EMONCFG1_EMONSEL1_IOM1ON = 27
,
PWRCTRL_EMONCFG1_EMONSEL1_IOM2ON = 28
, PWRCTRL_EMONCFG1_EMONSEL1_IOM3ON = 29
, PWRCTRL_EMONCFG1_EMONSEL1_I3C0ON = 30
, PWRCTRL_EMONCFG1_EMONSEL1_I3C1ON = 31
,
PWRCTRL_EMONCFG1_EMONSEL1_IOM4ON = 32
, PWRCTRL_EMONCFG1_EMONSEL1_IOM5ON = 33
, PWRCTRL_EMONCFG1_EMONSEL1_IOM6ON = 34
, PWRCTRL_EMONCFG1_EMONSEL1_IOM7ON = 35
,
PWRCTRL_EMONCFG1_EMONSEL1_IOSON = 36
, PWRCTRL_EMONCFG1_EMONSEL1_MSPI0ON = 37
, PWRCTRL_EMONCFG1_EMONSEL1_MSPI1ON = 38
, PWRCTRL_EMONCFG1_EMONSEL1_MSPI2ON = 39
,
PWRCTRL_EMONCFG1_EMONSEL1_SDIOON = 40
, PWRCTRL_EMONCFG1_EMONSEL1_USBON = 41
, PWRCTRL_EMONCFG1_EMONSEL1_USBPHYON = 42
} |
| |
| enum | PWRCTRL_EMONCFG2_EMONSEL2_Enum {
PWRCTRL_EMONCFG2_EMONSEL2_NEVER = 0
, PWRCTRL_EMONCFG2_EMONSEL2_ALWAYS = 1
, PWRCTRL_EMONCFG2_EMONSEL2_MCUSLEEP = 2
, PWRCTRL_EMONCFG2_EMONSEL2_MCUDEEPSLEEP = 3
,
PWRCTRL_EMONCFG2_EMONSEL2_DSP0ON = 4
, PWRCTRL_EMONCFG2_EMONSEL2_DSP1ON = 5
, PWRCTRL_EMONCFG2_EMONSEL2_ADCON = 6
, PWRCTRL_EMONCFG2_EMONSEL2_AUDPBON = 7
,
PWRCTRL_EMONCFG2_EMONSEL2_AUDRECON = 8
, PWRCTRL_EMONCFG2_EMONSEL2_I2S0ON = 9
, PWRCTRL_EMONCFG2_EMONSEL2_I2S1ON = 10
, PWRCTRL_EMONCFG2_EMONSEL2_PDM0ON = 11
,
PWRCTRL_EMONCFG2_EMONSEL2_PDM1ON = 12
, PWRCTRL_EMONCFG2_EMONSEL2_PDM2ON = 13
, PWRCTRL_EMONCFG2_EMONSEL2_PDM3ON = 14
, PWRCTRL_EMONCFG2_EMONSEL2_AUDADCON = 15
,
PWRCTRL_EMONCFG2_EMONSEL2_CRYPTOON = 16
, PWRCTRL_EMONCFG2_EMONSEL2_DBGON = 17
, PWRCTRL_EMONCFG2_EMONSEL2_DISPON = 18
, PWRCTRL_EMONCFG2_EMONSEL2_DISPPHYON = 19
,
PWRCTRL_EMONCFG2_EMONSEL2_DSPAON = 20
, PWRCTRL_EMONCFG2_EMONSEL2_GFXON = 21
, PWRCTRL_EMONCFG2_EMONSEL2_UART0ON = 22
, PWRCTRL_EMONCFG2_EMONSEL2_UART1ON = 23
,
PWRCTRL_EMONCFG2_EMONSEL2_UART2ON = 24
, PWRCTRL_EMONCFG2_EMONSEL2_UART3ON = 25
, PWRCTRL_EMONCFG2_EMONSEL2_IOM0ON = 26
, PWRCTRL_EMONCFG2_EMONSEL2_IOM1ON = 27
,
PWRCTRL_EMONCFG2_EMONSEL2_IOM2ON = 28
, PWRCTRL_EMONCFG2_EMONSEL2_IOM3ON = 29
, PWRCTRL_EMONCFG2_EMONSEL2_I3C0ON = 30
, PWRCTRL_EMONCFG2_EMONSEL2_I3C1ON = 31
,
PWRCTRL_EMONCFG2_EMONSEL2_IOM4ON = 32
, PWRCTRL_EMONCFG2_EMONSEL2_IOM5ON = 33
, PWRCTRL_EMONCFG2_EMONSEL2_IOM6ON = 34
, PWRCTRL_EMONCFG2_EMONSEL2_IOM7ON = 35
,
PWRCTRL_EMONCFG2_EMONSEL2_IOSON = 36
, PWRCTRL_EMONCFG2_EMONSEL2_MSPI0ON = 37
, PWRCTRL_EMONCFG2_EMONSEL2_MSPI1ON = 38
, PWRCTRL_EMONCFG2_EMONSEL2_MSPI2ON = 39
,
PWRCTRL_EMONCFG2_EMONSEL2_SDIOON = 40
, PWRCTRL_EMONCFG2_EMONSEL2_USBON = 41
, PWRCTRL_EMONCFG2_EMONSEL2_USBPHYON = 42
} |
| |
| enum | PWRCTRL_EMONCFG3_EMONSEL3_Enum {
PWRCTRL_EMONCFG3_EMONSEL3_NEVER = 0
, PWRCTRL_EMONCFG3_EMONSEL3_ALWAYS = 1
, PWRCTRL_EMONCFG3_EMONSEL3_MCUSLEEP = 2
, PWRCTRL_EMONCFG3_EMONSEL3_MCUDEEPSLEEP = 3
,
PWRCTRL_EMONCFG3_EMONSEL3_DSP0ON = 4
, PWRCTRL_EMONCFG3_EMONSEL3_DSP1ON = 5
, PWRCTRL_EMONCFG3_EMONSEL3_ADCON = 6
, PWRCTRL_EMONCFG3_EMONSEL3_AUDPBON = 7
,
PWRCTRL_EMONCFG3_EMONSEL3_AUDRECON = 8
, PWRCTRL_EMONCFG3_EMONSEL3_I2S0ON = 9
, PWRCTRL_EMONCFG3_EMONSEL3_I2S1ON = 10
, PWRCTRL_EMONCFG3_EMONSEL3_PDM0ON = 11
,
PWRCTRL_EMONCFG3_EMONSEL3_PDM1ON = 12
, PWRCTRL_EMONCFG3_EMONSEL3_PDM2ON = 13
, PWRCTRL_EMONCFG3_EMONSEL3_PDM3ON = 14
, PWRCTRL_EMONCFG3_EMONSEL3_AUDADCON = 15
,
PWRCTRL_EMONCFG3_EMONSEL3_CRYPTOON = 16
, PWRCTRL_EMONCFG3_EMONSEL3_DBGON = 17
, PWRCTRL_EMONCFG3_EMONSEL3_DISPON = 18
, PWRCTRL_EMONCFG3_EMONSEL3_DISPPHYON = 19
,
PWRCTRL_EMONCFG3_EMONSEL3_DSPAON = 20
, PWRCTRL_EMONCFG3_EMONSEL3_GFXON = 21
, PWRCTRL_EMONCFG3_EMONSEL3_UART0ON = 22
, PWRCTRL_EMONCFG3_EMONSEL3_UART1ON = 23
,
PWRCTRL_EMONCFG3_EMONSEL3_UART2ON = 24
, PWRCTRL_EMONCFG3_EMONSEL3_UART3ON = 25
, PWRCTRL_EMONCFG3_EMONSEL3_IOM0ON = 26
, PWRCTRL_EMONCFG3_EMONSEL3_IOM1ON = 27
,
PWRCTRL_EMONCFG3_EMONSEL3_IOM2ON = 28
, PWRCTRL_EMONCFG3_EMONSEL3_IOM3ON = 29
, PWRCTRL_EMONCFG3_EMONSEL3_I3C0ON = 30
, PWRCTRL_EMONCFG3_EMONSEL3_I3C1ON = 31
,
PWRCTRL_EMONCFG3_EMONSEL3_IOM4ON = 32
, PWRCTRL_EMONCFG3_EMONSEL3_IOM5ON = 33
, PWRCTRL_EMONCFG3_EMONSEL3_IOM6ON = 34
, PWRCTRL_EMONCFG3_EMONSEL3_IOM7ON = 35
,
PWRCTRL_EMONCFG3_EMONSEL3_IOSON = 36
, PWRCTRL_EMONCFG3_EMONSEL3_MSPI0ON = 37
, PWRCTRL_EMONCFG3_EMONSEL3_MSPI1ON = 38
, PWRCTRL_EMONCFG3_EMONSEL3_MSPI2ON = 39
,
PWRCTRL_EMONCFG3_EMONSEL3_SDIOON = 40
, PWRCTRL_EMONCFG3_EMONSEL3_USBON = 41
, PWRCTRL_EMONCFG3_EMONSEL3_USBPHYON = 42
} |
| |
| enum | PWRCTRL_EMONCFG4_EMONSEL4_Enum {
PWRCTRL_EMONCFG4_EMONSEL4_NEVER = 0
, PWRCTRL_EMONCFG4_EMONSEL4_ALWAYS = 1
, PWRCTRL_EMONCFG4_EMONSEL4_MCUSLEEP = 2
, PWRCTRL_EMONCFG4_EMONSEL4_MCUDEEPSLEEP = 3
,
PWRCTRL_EMONCFG4_EMONSEL4_DSP0ON = 4
, PWRCTRL_EMONCFG4_EMONSEL4_DSP1ON = 5
, PWRCTRL_EMONCFG4_EMONSEL4_ADCON = 6
, PWRCTRL_EMONCFG4_EMONSEL4_AUDPBON = 7
,
PWRCTRL_EMONCFG4_EMONSEL4_AUDRECON = 8
, PWRCTRL_EMONCFG4_EMONSEL4_I2S0ON = 9
, PWRCTRL_EMONCFG4_EMONSEL4_I2S1ON = 10
, PWRCTRL_EMONCFG4_EMONSEL4_PDM0ON = 11
,
PWRCTRL_EMONCFG4_EMONSEL4_PDM1ON = 12
, PWRCTRL_EMONCFG4_EMONSEL4_PDM2ON = 13
, PWRCTRL_EMONCFG4_EMONSEL4_PDM3ON = 14
, PWRCTRL_EMONCFG4_EMONSEL4_AUDADCON = 15
,
PWRCTRL_EMONCFG4_EMONSEL4_CRYPTOON = 16
, PWRCTRL_EMONCFG4_EMONSEL4_DBGON = 17
, PWRCTRL_EMONCFG4_EMONSEL4_DISPON = 18
, PWRCTRL_EMONCFG4_EMONSEL4_DISPPHYON = 19
,
PWRCTRL_EMONCFG4_EMONSEL4_DSPAON = 20
, PWRCTRL_EMONCFG4_EMONSEL4_GFXON = 21
, PWRCTRL_EMONCFG4_EMONSEL4_UART0ON = 22
, PWRCTRL_EMONCFG4_EMONSEL4_UART1ON = 23
,
PWRCTRL_EMONCFG4_EMONSEL4_UART2ON = 24
, PWRCTRL_EMONCFG4_EMONSEL4_UART3ON = 25
, PWRCTRL_EMONCFG4_EMONSEL4_IOM0ON = 26
, PWRCTRL_EMONCFG4_EMONSEL4_IOM1ON = 27
,
PWRCTRL_EMONCFG4_EMONSEL4_IOM2ON = 28
, PWRCTRL_EMONCFG4_EMONSEL4_IOM3ON = 29
, PWRCTRL_EMONCFG4_EMONSEL4_I3C0ON = 30
, PWRCTRL_EMONCFG4_EMONSEL4_I3C1ON = 31
,
PWRCTRL_EMONCFG4_EMONSEL4_IOM4ON = 32
, PWRCTRL_EMONCFG4_EMONSEL4_IOM5ON = 33
, PWRCTRL_EMONCFG4_EMONSEL4_IOM6ON = 34
, PWRCTRL_EMONCFG4_EMONSEL4_IOM7ON = 35
,
PWRCTRL_EMONCFG4_EMONSEL4_IOSON = 36
, PWRCTRL_EMONCFG4_EMONSEL4_MSPI0ON = 37
, PWRCTRL_EMONCFG4_EMONSEL4_MSPI1ON = 38
, PWRCTRL_EMONCFG4_EMONSEL4_MSPI2ON = 39
,
PWRCTRL_EMONCFG4_EMONSEL4_SDIOON = 40
, PWRCTRL_EMONCFG4_EMONSEL4_USBON = 41
, PWRCTRL_EMONCFG4_EMONSEL4_USBPHYON = 42
} |
| |
| enum | PWRCTRL_EMONCFG5_EMONSEL5_Enum {
PWRCTRL_EMONCFG5_EMONSEL5_NEVER = 0
, PWRCTRL_EMONCFG5_EMONSEL5_ALWAYS = 1
, PWRCTRL_EMONCFG5_EMONSEL5_MCUSLEEP = 2
, PWRCTRL_EMONCFG5_EMONSEL5_MCUDEEPSLEEP = 3
,
PWRCTRL_EMONCFG5_EMONSEL5_DSP0ON = 4
, PWRCTRL_EMONCFG5_EMONSEL5_DSP1ON = 5
, PWRCTRL_EMONCFG5_EMONSEL5_ADCON = 6
, PWRCTRL_EMONCFG5_EMONSEL5_AUDPBON = 7
,
PWRCTRL_EMONCFG5_EMONSEL5_AUDRECON = 8
, PWRCTRL_EMONCFG5_EMONSEL5_I2S0ON = 9
, PWRCTRL_EMONCFG5_EMONSEL5_I2S1ON = 10
, PWRCTRL_EMONCFG5_EMONSEL5_PDM0ON = 11
,
PWRCTRL_EMONCFG5_EMONSEL5_PDM1ON = 12
, PWRCTRL_EMONCFG5_EMONSEL5_PDM2ON = 13
, PWRCTRL_EMONCFG5_EMONSEL5_PDM3ON = 14
, PWRCTRL_EMONCFG5_EMONSEL5_AUDADCON = 15
,
PWRCTRL_EMONCFG5_EMONSEL5_CRYPTOON = 16
, PWRCTRL_EMONCFG5_EMONSEL5_DBGON = 17
, PWRCTRL_EMONCFG5_EMONSEL5_DISPON = 18
, PWRCTRL_EMONCFG5_EMONSEL5_DISPPHYON = 19
,
PWRCTRL_EMONCFG5_EMONSEL5_DSPAON = 20
, PWRCTRL_EMONCFG5_EMONSEL5_GFXON = 21
, PWRCTRL_EMONCFG5_EMONSEL5_UART0ON = 22
, PWRCTRL_EMONCFG5_EMONSEL5_UART1ON = 23
,
PWRCTRL_EMONCFG5_EMONSEL5_UART2ON = 24
, PWRCTRL_EMONCFG5_EMONSEL5_UART3ON = 25
, PWRCTRL_EMONCFG5_EMONSEL5_IOM0ON = 26
, PWRCTRL_EMONCFG5_EMONSEL5_IOM1ON = 27
,
PWRCTRL_EMONCFG5_EMONSEL5_IOM2ON = 28
, PWRCTRL_EMONCFG5_EMONSEL5_IOM3ON = 29
, PWRCTRL_EMONCFG5_EMONSEL5_I3C0ON = 30
, PWRCTRL_EMONCFG5_EMONSEL5_I3C1ON = 31
,
PWRCTRL_EMONCFG5_EMONSEL5_IOM4ON = 32
, PWRCTRL_EMONCFG5_EMONSEL5_IOM5ON = 33
, PWRCTRL_EMONCFG5_EMONSEL5_IOM6ON = 34
, PWRCTRL_EMONCFG5_EMONSEL5_IOM7ON = 35
,
PWRCTRL_EMONCFG5_EMONSEL5_IOSON = 36
, PWRCTRL_EMONCFG5_EMONSEL5_MSPI0ON = 37
, PWRCTRL_EMONCFG5_EMONSEL5_MSPI1ON = 38
, PWRCTRL_EMONCFG5_EMONSEL5_MSPI2ON = 39
,
PWRCTRL_EMONCFG5_EMONSEL5_SDIOON = 40
, PWRCTRL_EMONCFG5_EMONSEL5_USBON = 41
, PWRCTRL_EMONCFG5_EMONSEL5_USBPHYON = 42
} |
| |
| enum | PWRCTRL_EMONCFG6_EMONSEL6_Enum {
PWRCTRL_EMONCFG6_EMONSEL6_NEVER = 0
, PWRCTRL_EMONCFG6_EMONSEL6_ALWAYS = 1
, PWRCTRL_EMONCFG6_EMONSEL6_MCUSLEEP = 2
, PWRCTRL_EMONCFG6_EMONSEL6_MCUDEEPSLEEP = 3
,
PWRCTRL_EMONCFG6_EMONSEL6_DSP0ON = 4
, PWRCTRL_EMONCFG6_EMONSEL6_DSP1ON = 5
, PWRCTRL_EMONCFG6_EMONSEL6_ADCON = 6
, PWRCTRL_EMONCFG6_EMONSEL6_AUDPBON = 7
,
PWRCTRL_EMONCFG6_EMONSEL6_AUDRECON = 8
, PWRCTRL_EMONCFG6_EMONSEL6_I2S0ON = 9
, PWRCTRL_EMONCFG6_EMONSEL6_I2S1ON = 10
, PWRCTRL_EMONCFG6_EMONSEL6_PDM0ON = 11
,
PWRCTRL_EMONCFG6_EMONSEL6_PDM1ON = 12
, PWRCTRL_EMONCFG6_EMONSEL6_PDM2ON = 13
, PWRCTRL_EMONCFG6_EMONSEL6_PDM3ON = 14
, PWRCTRL_EMONCFG6_EMONSEL6_AUDADCON = 15
,
PWRCTRL_EMONCFG6_EMONSEL6_CRYPTOON = 16
, PWRCTRL_EMONCFG6_EMONSEL6_DBGON = 17
, PWRCTRL_EMONCFG6_EMONSEL6_DISPON = 18
, PWRCTRL_EMONCFG6_EMONSEL6_DISPPHYON = 19
,
PWRCTRL_EMONCFG6_EMONSEL6_DSPAON = 20
, PWRCTRL_EMONCFG6_EMONSEL6_GFXON = 21
, PWRCTRL_EMONCFG6_EMONSEL6_UART0ON = 22
, PWRCTRL_EMONCFG6_EMONSEL6_UART1ON = 23
,
PWRCTRL_EMONCFG6_EMONSEL6_UART2ON = 24
, PWRCTRL_EMONCFG6_EMONSEL6_UART3ON = 25
, PWRCTRL_EMONCFG6_EMONSEL6_IOM0ON = 26
, PWRCTRL_EMONCFG6_EMONSEL6_IOM1ON = 27
,
PWRCTRL_EMONCFG6_EMONSEL6_IOM2ON = 28
, PWRCTRL_EMONCFG6_EMONSEL6_IOM3ON = 29
, PWRCTRL_EMONCFG6_EMONSEL6_I3C0ON = 30
, PWRCTRL_EMONCFG6_EMONSEL6_I3C1ON = 31
,
PWRCTRL_EMONCFG6_EMONSEL6_IOM4ON = 32
, PWRCTRL_EMONCFG6_EMONSEL6_IOM5ON = 33
, PWRCTRL_EMONCFG6_EMONSEL6_IOM6ON = 34
, PWRCTRL_EMONCFG6_EMONSEL6_IOM7ON = 35
,
PWRCTRL_EMONCFG6_EMONSEL6_IOSON = 36
, PWRCTRL_EMONCFG6_EMONSEL6_MSPI0ON = 37
, PWRCTRL_EMONCFG6_EMONSEL6_MSPI1ON = 38
, PWRCTRL_EMONCFG6_EMONSEL6_MSPI2ON = 39
,
PWRCTRL_EMONCFG6_EMONSEL6_SDIOON = 40
, PWRCTRL_EMONCFG6_EMONSEL6_USBON = 41
, PWRCTRL_EMONCFG6_EMONSEL6_USBPHYON = 42
} |
| |
| enum | PWRCTRL_EMONCFG7_EMONSEL7_Enum {
PWRCTRL_EMONCFG7_EMONSEL7_NEVER = 0
, PWRCTRL_EMONCFG7_EMONSEL7_ALWAYS = 1
, PWRCTRL_EMONCFG7_EMONSEL7_MCUSLEEP = 2
, PWRCTRL_EMONCFG7_EMONSEL7_MCUDEEPSLEEP = 3
,
PWRCTRL_EMONCFG7_EMONSEL7_DSP0ON = 4
, PWRCTRL_EMONCFG7_EMONSEL7_DSP1ON = 5
, PWRCTRL_EMONCFG7_EMONSEL7_ADCON = 6
, PWRCTRL_EMONCFG7_EMONSEL7_AUDPBON = 7
,
PWRCTRL_EMONCFG7_EMONSEL7_AUDRECON = 8
, PWRCTRL_EMONCFG7_EMONSEL7_I2S0ON = 9
, PWRCTRL_EMONCFG7_EMONSEL7_I2S1ON = 10
, PWRCTRL_EMONCFG7_EMONSEL7_PDM0ON = 11
,
PWRCTRL_EMONCFG7_EMONSEL7_PDM1ON = 12
, PWRCTRL_EMONCFG7_EMONSEL7_PDM2ON = 13
, PWRCTRL_EMONCFG7_EMONSEL7_PDM3ON = 14
, PWRCTRL_EMONCFG7_EMONSEL7_AUDADCON = 15
,
PWRCTRL_EMONCFG7_EMONSEL7_CRYPTOON = 16
, PWRCTRL_EMONCFG7_EMONSEL7_DBGON = 17
, PWRCTRL_EMONCFG7_EMONSEL7_DISPON = 18
, PWRCTRL_EMONCFG7_EMONSEL7_DISPPHYON = 19
,
PWRCTRL_EMONCFG7_EMONSEL7_DSPAON = 20
, PWRCTRL_EMONCFG7_EMONSEL7_GFXON = 21
, PWRCTRL_EMONCFG7_EMONSEL7_UART0ON = 22
, PWRCTRL_EMONCFG7_EMONSEL7_UART1ON = 23
,
PWRCTRL_EMONCFG7_EMONSEL7_UART2ON = 24
, PWRCTRL_EMONCFG7_EMONSEL7_UART3ON = 25
, PWRCTRL_EMONCFG7_EMONSEL7_IOM0ON = 26
, PWRCTRL_EMONCFG7_EMONSEL7_IOM1ON = 27
,
PWRCTRL_EMONCFG7_EMONSEL7_IOM2ON = 28
, PWRCTRL_EMONCFG7_EMONSEL7_IOM3ON = 29
, PWRCTRL_EMONCFG7_EMONSEL7_I3C0ON = 30
, PWRCTRL_EMONCFG7_EMONSEL7_I3C1ON = 31
,
PWRCTRL_EMONCFG7_EMONSEL7_IOM4ON = 32
, PWRCTRL_EMONCFG7_EMONSEL7_IOM5ON = 33
, PWRCTRL_EMONCFG7_EMONSEL7_IOM6ON = 34
, PWRCTRL_EMONCFG7_EMONSEL7_IOM7ON = 35
,
PWRCTRL_EMONCFG7_EMONSEL7_IOSON = 36
, PWRCTRL_EMONCFG7_EMONSEL7_MSPI0ON = 37
, PWRCTRL_EMONCFG7_EMONSEL7_MSPI1ON = 38
, PWRCTRL_EMONCFG7_EMONSEL7_MSPI2ON = 39
,
PWRCTRL_EMONCFG7_EMONSEL7_SDIOON = 40
, PWRCTRL_EMONCFG7_EMONSEL7_USBON = 41
, PWRCTRL_EMONCFG7_EMONSEL7_USBPHYON = 42
} |
| |
| enum | RSTGEN_SWPOI_SWPOIKEY_Enum { RSTGEN_SWPOI_SWPOIKEY_KEYVALUE = 27
, RSTGEN_SWPOI_SWPOIKEY_DEFAULT = 0
} |
| |
| enum | RSTGEN_SWPOR_SWPORKEY_Enum { RSTGEN_SWPOR_SWPORKEY_KEYVALUE = 212
, RSTGEN_SWPOR_SWPORKEY_DEFAULT = 0
} |
| |
| enum | RSTGEN_SIMOBODM_DIGBOECLV_Enum { RSTGEN_SIMOBODM_DIGBOECLV_BOM = 0
, RSTGEN_SIMOBODM_DIGBOECLV_BOE = 1
} |
| |
| enum | RSTGEN_SIMOBODM_DIGBOES_Enum { RSTGEN_SIMOBODM_DIGBOES_BOM = 0
, RSTGEN_SIMOBODM_DIGBOES_BOE = 1
} |
| |
| enum | RSTGEN_SIMOBODM_DIGBOEF_Enum { RSTGEN_SIMOBODM_DIGBOEF_BOM = 0
, RSTGEN_SIMOBODM_DIGBOEF_BOE = 1
} |
| |
| enum | RSTGEN_SIMOBODM_DIGBOEC_Enum { RSTGEN_SIMOBODM_DIGBOEC_BOA = 0
, RSTGEN_SIMOBODM_DIGBOEC_BOD = 1
} |
| |
| enum | RTC_RTCCTL_HR1224_Enum { RTC_RTCCTL_HR1224_24HR = 0
, RTC_RTCCTL_HR1224_DISABLED = 1
} |
| |
| enum | RTC_RTCCTL_RSTOP_Enum { RTC_RTCCTL_RSTOP_RUN = 0
, RTC_RTCCTL_RSTOP_STOP = 1
} |
| |
| enum | RTC_RTCCTL_RPT_Enum {
RTC_RTCCTL_RPT_DIS = 0
, RTC_RTCCTL_RPT_YEAR = 1
, RTC_RTCCTL_RPT_MONTH = 2
, RTC_RTCCTL_RPT_WEEK = 3
,
RTC_RTCCTL_RPT_DAY = 4
, RTC_RTCCTL_RPT_HR = 5
, RTC_RTCCTL_RPT_MIN = 6
, RTC_RTCCTL_RPT_SEC = 7
} |
| |
| enum | RTC_RTCCTL_WRTC_Enum { RTC_RTCCTL_WRTC_DIS = 0
, RTC_RTCCTL_WRTC_EN = 1
} |
| |
| enum | RTC_CTRUP_CTERR_Enum { RTC_CTRUP_CTERR_NOERR = 0
, RTC_CTRUP_CTERR_RDERR = 1
} |
| |
| enum | RTC_CTRUP_CEB_Enum { RTC_CTRUP_CEB_DIS = 0
, RTC_CTRUP_CEB_EN = 1
} |
| |
| enum | RTC_CTRUP_CB_Enum { RTC_CTRUP_CB_2000 = 0
, RTC_CTRUP_CB_1900_2100 = 1
} |
| |
| enum | SDIO_BLOCK_BLKCNT_Enum { SDIO_BLOCK_BLKCNT_STOPCNT = 0
, SDIO_BLOCK_BLKCNT_1BLOCK = 1
, SDIO_BLOCK_BLKCNT_2BLOCKS = 2
, SDIO_BLOCK_BLKCNT_65535BLOCKS = 65535
} |
| |
| enum | SDIO_BLOCK_HOSTSDMABUFSZ_Enum {
SDIO_BLOCK_HOSTSDMABUFSZ_4KB = 0
, SDIO_BLOCK_HOSTSDMABUFSZ_8KB = 1
, SDIO_BLOCK_HOSTSDMABUFSZ_16KB = 2
, SDIO_BLOCK_HOSTSDMABUFSZ_32KB = 3
,
SDIO_BLOCK_HOSTSDMABUFSZ_64KB = 4
, SDIO_BLOCK_HOSTSDMABUFSZ_128KB = 5
, SDIO_BLOCK_HOSTSDMABUFSZ_256KB = 6
, SDIO_BLOCK_HOSTSDMABUFSZ_512KB = 7
} |
| |
| enum | SDIO_BLOCK_TRANSFERBLOCKSIZE_Enum {
SDIO_BLOCK_TRANSFERBLOCKSIZE_NODATAXFER = 0
, SDIO_BLOCK_TRANSFERBLOCKSIZE_1BYTE = 1
, SDIO_BLOCK_TRANSFERBLOCKSIZE_2BYTES = 2
, SDIO_BLOCK_TRANSFERBLOCKSIZE_3BYTES = 3
,
SDIO_BLOCK_TRANSFERBLOCKSIZE_4BYTES = 4
, SDIO_BLOCK_TRANSFERBLOCKSIZE_511BYTES = 511
, SDIO_BLOCK_TRANSFERBLOCKSIZE_512BYTES = 512
, SDIO_BLOCK_TRANSFERBLOCKSIZE_2048BYTES = 2048
} |
| |
| enum | SDIO_TRANSFER_CMDTYPE_Enum { SDIO_TRANSFER_CMDTYPE_NORMAL = 0
, SDIO_TRANSFER_CMDTYPE_SUSPEND = 1
, SDIO_TRANSFER_CMDTYPE_RESUME = 2
, SDIO_TRANSFER_CMDTYPE_ABORT = 3
} |
| |
| enum | SDIO_TRANSFER_DATAPRSNTSEL_Enum { SDIO_TRANSFER_DATAPRSNTSEL_NODATAPRESENT = 0
, SDIO_TRANSFER_DATAPRSNTSEL_DATAPRESENT = 1
} |
| |
| enum | SDIO_TRANSFER_CMDIDXCHKEN_Enum { SDIO_TRANSFER_CMDIDXCHKEN_DISABLE = 0
, SDIO_TRANSFER_CMDIDXCHKEN_ENABLE = 1
} |
| |
| enum | SDIO_TRANSFER_CMDCRCCHKEN_Enum { SDIO_TRANSFER_CMDCRCCHKEN_DISABLE = 0
, SDIO_TRANSFER_CMDCRCCHKEN_ENABLE = 1
} |
| |
| enum | SDIO_TRANSFER_RESPTYPESEL_Enum { SDIO_TRANSFER_RESPTYPESEL_NORESPONSE = 0
, SDIO_TRANSFER_RESPTYPESEL_LEN136 = 1
, SDIO_TRANSFER_RESPTYPESEL_LEN48 = 2
, SDIO_TRANSFER_RESPTYPESEL_LEN48CHKBUSY = 3
} |
| |
| enum | SDIO_TRANSFER_BLKSEL_Enum { SDIO_TRANSFER_BLKSEL_SINGLEBLOCK = 0
, SDIO_TRANSFER_BLKSEL_MULTIPLEBLOCK = 1
} |
| |
| enum | SDIO_TRANSFER_DXFERDIRSEL_Enum { SDIO_TRANSFER_DXFERDIRSEL_WRITE = 0
, SDIO_TRANSFER_DXFERDIRSEL_READ = 1
} |
| |
| enum | SDIO_TRANSFER_ACMDEN_Enum { SDIO_TRANSFER_ACMDEN_DISABLED = 0
, SDIO_TRANSFER_ACMDEN_CMD12ENABLE = 1
, SDIO_TRANSFER_ACMDEN_CMD23ENABLE = 2
} |
| |
| enum | SDIO_TRANSFER_BLKCNTEN_Enum { SDIO_TRANSFER_BLKCNTEN_DISABLE = 0
, SDIO_TRANSFER_BLKCNTEN_ENABLE = 1
} |
| |
| enum | SDIO_TRANSFER_DMAEN_Enum { SDIO_TRANSFER_DMAEN_DISABLE = 0
, SDIO_TRANSFER_DMAEN_ENABLE = 1
} |
| |
| enum | SDIO_PRESENT_DAT74LINE_Enum { SDIO_PRESENT_DAT74LINE_DAT7 = 8
, SDIO_PRESENT_DAT74LINE_DAT6 = 4
, SDIO_PRESENT_DAT74LINE_DAT5 = 2
, SDIO_PRESENT_DAT74LINE_DAT4 = 1
} |
| |
| enum | SDIO_PRESENT_DAT30LINE_Enum { SDIO_PRESENT_DAT30LINE_DAT3 = 8
, SDIO_PRESENT_DAT30LINE_DAT2 = 4
, SDIO_PRESENT_DAT30LINE_DAT1 = 2
, SDIO_PRESENT_DAT30LINE_DAT0 = 1
} |
| |
| enum | SDIO_PRESENT_WRPROTSW_Enum { SDIO_PRESENT_WRPROTSW_WRITEPROTECTED = 0
, SDIO_PRESENT_WRPROTSW_WRITEENABLED = 1
} |
| |
| enum | SDIO_PRESENT_CARDDET_Enum { SDIO_PRESENT_CARDDET_NOCARDPRESENT = 0
, SDIO_PRESENT_CARDDET_CARDPRESENT = 1
} |
| |
| enum | SDIO_PRESENT_CARDSTABLE_Enum { SDIO_PRESENT_CARDSTABLE_RESET_DEBOUNCING_NOCARD = 0
, SDIO_PRESENT_CARDSTABLE_CARDINSERTED = 1
} |
| |
| enum | SDIO_PRESENT_CARDINSERTED_Enum { SDIO_PRESENT_CARDINSERTED_RESET_DEBOUNCING_NOCARD = 0
, SDIO_PRESENT_CARDINSERTED_CARDINSERTED = 1
} |
| |
| enum | SDIO_PRESENT_BUFRDEN_Enum { SDIO_PRESENT_BUFRDEN_DISABLE = 0
, SDIO_PRESENT_BUFRDEN_ENABLE = 1
} |
| |
| enum | SDIO_PRESENT_BUFWREN_Enum { SDIO_PRESENT_BUFWREN_DISABLE = 0
, SDIO_PRESENT_BUFWREN_ENABLE = 1
} |
| |
| enum | SDIO_PRESENT_RDXFERACT_Enum { SDIO_PRESENT_RDXFERACT_TRANSFERRING = 1
, SDIO_PRESENT_RDXFERACT_NOVALIDATA = 0
} |
| |
| enum | SDIO_PRESENT_WRXFERACT_Enum { SDIO_PRESENT_WRXFERACT_TRANSFERRING = 1
, SDIO_PRESENT_WRXFERACT_NOVALIDDATA = 0
} |
| |
| enum | SDIO_PRESENT_RETUNINGREQUEST_Enum { SDIO_PRESENT_RETUNINGREQUEST_RETUNENEEDED = 1
, SDIO_PRESENT_RETUNINGREQUEST_WELLTUNED = 0
} |
| |
| enum | SDIO_PRESENT_DLINEACT_Enum { SDIO_PRESENT_DLINEACT_ACTIVE = 1
, SDIO_PRESENT_DLINEACT_INACTIVE = 0
} |
| |
| enum | SDIO_PRESENT_CMDINHDAT_Enum { SDIO_PRESENT_CMDINHDAT_DONTISSUE = 1
, SDIO_PRESENT_CMDINHDAT_ISSUE = 0
} |
| |
| enum | SDIO_PRESENT_CMDINHCMD_Enum { SDIO_PRESENT_CMDINHCMD_DONTISSUE = 1
, SDIO_PRESENT_CMDINHCMD_ISSUE = 0
} |
| |
| enum | SDIO_HOSTCTRL1_WUENCARDREMOVL_Enum { SDIO_HOSTCTRL1_WUENCARDREMOVL_ENABLE = 1
, SDIO_HOSTCTRL1_WUENCARDREMOVL_DISABLE = 0
} |
| |
| enum | SDIO_HOSTCTRL1_WUENCARDINSERT_Enum { SDIO_HOSTCTRL1_WUENCARDINSERT_ENABLE = 1
, SDIO_HOSTCTRL1_WUENCARDINSERT_DISABLE = 0
} |
| |
| enum | SDIO_HOSTCTRL1_WUENCARDINT_Enum { SDIO_HOSTCTRL1_WUENCARDINT_ENABLE = 1
, SDIO_HOSTCTRL1_WUENCARDINT_DISABLE = 0
} |
| |
| enum | SDIO_HOSTCTRL1_BOOTACKCHK_Enum { SDIO_HOSTCTRL1_BOOTACKCHK_WAIT = 1
, SDIO_HOSTCTRL1_BOOTACKCHK_NOWAIT = 0
} |
| |
| enum | SDIO_HOSTCTRL1_ALTBOOTEN_Enum { SDIO_HOSTCTRL1_ALTBOOTEN_START = 1
, SDIO_HOSTCTRL1_ALTBOOTEN_STOP = 0
} |
| |
| enum | SDIO_HOSTCTRL1_BOOTEN_Enum { SDIO_HOSTCTRL1_BOOTEN_START = 1
, SDIO_HOSTCTRL1_BOOTEN_STOP = 0
} |
| |
| enum | SDIO_HOSTCTRL1_SPIMODE_Enum { SDIO_HOSTCTRL1_SPIMODE_SPI = 1
, SDIO_HOSTCTRL1_SPIMODE_SD = 0
} |
| |
| enum | SDIO_HOSTCTRL1_READWAITCTRL_Enum { SDIO_HOSTCTRL1_READWAITCTRL_ENABLE = 1
, SDIO_HOSTCTRL1_READWAITCTRL_DISABLE = 0
} |
| |
| enum | SDIO_HOSTCTRL1_CONTREQ_Enum { SDIO_HOSTCTRL1_CONTREQ_RESTART = 1
, SDIO_HOSTCTRL1_CONTREQ_IGNORED = 0
} |
| |
| enum | SDIO_HOSTCTRL1_STOPATBLOCKGAPREQUEST_Enum { SDIO_HOSTCTRL1_STOPATBLOCKGAPREQUEST_STOP = 1
, SDIO_HOSTCTRL1_STOPATBLOCKGAPREQUEST_TRANSFER = 0
} |
| |
| enum | SDIO_HOSTCTRL1_HWRESET_Enum { SDIO_HOSTCTRL1_HWRESET_ASSERT = 1
, SDIO_HOSTCTRL1_HWRESET_DEASSERT = 0
} |
| |
| enum | SDIO_HOSTCTRL1_VOLTSELECT_Enum { SDIO_HOSTCTRL1_VOLTSELECT_3_3V = 7
, SDIO_HOSTCTRL1_VOLTSELECT_3_0V = 6
, SDIO_HOSTCTRL1_VOLTSELECT_1_8V = 5
} |
| |
| enum | SDIO_HOSTCTRL1_SDBUSPOWER_Enum { SDIO_HOSTCTRL1_SDBUSPOWER_POWERON = 1
, SDIO_HOSTCTRL1_SDBUSPOWER_POWEROFF = 0
} |
| |
| enum | SDIO_HOSTCTRL1_CARDSRC_Enum { SDIO_HOSTCTRL1_CARDSRC_TEST = 1
, SDIO_HOSTCTRL1_CARDSRC_SDCD = 0
} |
| |
| enum | SDIO_HOSTCTRL1_TESTLEVEL_Enum { SDIO_HOSTCTRL1_TESTLEVEL_CARDINSERTED = 1
, SDIO_HOSTCTRL1_TESTLEVEL_NOCARD = 0
} |
| |
| enum | SDIO_HOSTCTRL1_XFERWIDTH_Enum { SDIO_HOSTCTRL1_XFERWIDTH_8BIT = 1
, SDIO_HOSTCTRL1_XFERWIDTH_XFER = 0
} |
| |
| enum | SDIO_HOSTCTRL1_DMASELECT_Enum { SDIO_HOSTCTRL1_DMASELECT_SDMA = 0
, SDIO_HOSTCTRL1_DMASELECT_ADMA132 = 1
, SDIO_HOSTCTRL1_DMASELECT_ADMA232 = 2
, SDIO_HOSTCTRL1_DMASELECT_ADMA264 = 3
} |
| |
| enum | SDIO_HOSTCTRL1_HISPEEDEN_Enum { SDIO_HOSTCTRL1_HISPEEDEN_HIGH = 1
, SDIO_HOSTCTRL1_HISPEEDEN_NORMAL = 0
} |
| |
| enum | SDIO_HOSTCTRL1_DATATRANSFERWIDTH_Enum { SDIO_HOSTCTRL1_DATATRANSFERWIDTH_SD4 = 1
, SDIO_HOSTCTRL1_DATATRANSFERWIDTH_SD1 = 0
} |
| |
| enum | SDIO_HOSTCTRL1_LEDCONTROL_Enum { SDIO_HOSTCTRL1_LEDCONTROL_ON = 1
, SDIO_HOSTCTRL1_LEDCONTROL_OFF = 0
} |
| |
| enum | SDIO_CLOCKCTRL_SWRSTDAT_Enum { SDIO_CLOCKCTRL_SWRSTDAT_RESET = 1
, SDIO_CLOCKCTRL_SWRSTDAT_WORK = 0
} |
| |
| enum | SDIO_CLOCKCTRL_SWRSTCMD_Enum { SDIO_CLOCKCTRL_SWRSTCMD_RESET = 1
, SDIO_CLOCKCTRL_SWRSTCMD_WORK = 0
} |
| |
| enum | SDIO_CLOCKCTRL_SWRSTALL_Enum { SDIO_CLOCKCTRL_SWRSTALL_RESET = 1
, SDIO_CLOCKCTRL_SWRSTALL_WORK = 0
} |
| |
| enum | SDIO_CLOCKCTRL_TIMEOUTCNT_Enum { SDIO_CLOCKCTRL_TIMEOUTCNT_27 = 14
, SDIO_CLOCKCTRL_TIMEOUTCNT_26 = 0
} |
| |
| enum | SDIO_CLOCKCTRL_FREQSEL_Enum {
SDIO_CLOCKCTRL_FREQSEL_DIV256 = 128
, SDIO_CLOCKCTRL_FREQSEL_DIV128 = 64
, SDIO_CLOCKCTRL_FREQSEL_DIV64 = 32
, SDIO_CLOCKCTRL_FREQSEL_DIV32 = 16
,
SDIO_CLOCKCTRL_FREQSEL_DIV16 = 8
, SDIO_CLOCKCTRL_FREQSEL_DIV8 = 4
, SDIO_CLOCKCTRL_FREQSEL_DIV4 = 2
, SDIO_CLOCKCTRL_FREQSEL_DIV2 = 1
,
SDIO_CLOCKCTRL_FREQSEL_BASECLK = 0
} |
| |
| enum | SDIO_CLOCKCTRL_CLKGENSEL_Enum { SDIO_CLOCKCTRL_CLKGENSEL_PROGCLK = 1
, SDIO_CLOCKCTRL_CLKGENSEL_DIVCLK = 0
} |
| |
| enum | SDIO_CLOCKCTRL_SDCLKEN_Enum { SDIO_CLOCKCTRL_SDCLKEN_ENABLE = 1
, SDIO_CLOCKCTRL_SDCLKEN_DISABLE = 0
} |
| |
| enum | SDIO_CLOCKCTRL_CLKSTABLE_Enum { SDIO_CLOCKCTRL_CLKSTABLE_READY = 1
, SDIO_CLOCKCTRL_CLKSTABLE_NOTREADY = 0
} |
| |
| enum | SDIO_CLOCKCTRL_CLKEN_Enum { SDIO_CLOCKCTRL_CLKEN_OSC = 1
, SDIO_CLOCKCTRL_CLKEN_STOP = 0
} |
| |
| enum | SDIO_INTSTAT_VNDERRSTAT_Enum { SDIO_INTSTAT_VNDERRSTAT_READY = 1
, SDIO_INTSTAT_VNDERRSTAT_NOTREADY = 0
} |
| |
| enum | SDIO_INTSTAT_TGTRESPERR_Enum { SDIO_INTSTAT_TGTRESPERR_NOERROR = 0
, SDIO_INTSTAT_TGTRESPERR_ERROR = 1
} |
| |
| enum | SDIO_INTSTAT_ADMAERROR_Enum { SDIO_INTSTAT_ADMAERROR_ERROR = 1
, SDIO_INTSTAT_ADMAERROR_NOERROR = 0
} |
| |
| enum | SDIO_INTSTAT_AUTOCMDERROR_Enum { SDIO_INTSTAT_AUTOCMDERROR_NOERROR = 0
, SDIO_INTSTAT_AUTOCMDERROR_ERROR = 1
} |
| |
| enum | SDIO_INTSTAT_CURRENTLIMITERROR_Enum { SDIO_INTSTAT_CURRENTLIMITERROR_NOERROR = 0
, SDIO_INTSTAT_CURRENTLIMITERROR_ERROR = 1
} |
| |
| enum | SDIO_INTSTAT_DATAENDBITERROR_Enum { SDIO_INTSTAT_DATAENDBITERROR_NOERROR = 0
, SDIO_INTSTAT_DATAENDBITERROR_ERROR = 1
} |
| |
| enum | SDIO_INTSTAT_DATACRCERROR_Enum { SDIO_INTSTAT_DATACRCERROR_NOERROR = 0
, SDIO_INTSTAT_DATACRCERROR_ERROR = 1
} |
| |
| enum | SDIO_INTSTAT_DATATIMEOUTERROR_Enum { SDIO_INTSTAT_DATATIMEOUTERROR_NOERROR = 0
, SDIO_INTSTAT_DATATIMEOUTERROR_ERROR = 1
} |
| |
| enum | SDIO_INTSTAT_COMMANDINDEXERROR_Enum { SDIO_INTSTAT_COMMANDINDEXERROR_NOERROR = 0
, SDIO_INTSTAT_COMMANDINDEXERROR_ERROR = 1
} |
| |
| enum | SDIO_INTSTAT_COMMANDENDBITERROR_Enum { SDIO_INTSTAT_COMMANDENDBITERROR_NOERROR = 0
, SDIO_INTSTAT_COMMANDENDBITERROR_ERROR = 1
} |
| |
| enum | SDIO_INTSTAT_COMMANDCRCERROR_Enum { SDIO_INTSTAT_COMMANDCRCERROR_NOERROR = 0
, SDIO_INTSTAT_COMMANDCRCERROR_ERROR = 1
} |
| |
| enum | SDIO_INTSTAT_COMMANDTIMEOUTERROR_Enum { SDIO_INTSTAT_COMMANDTIMEOUTERROR_NOERROR = 0
, SDIO_INTSTAT_COMMANDTIMEOUTERROR_ERROR = 1
} |
| |
| enum | SDIO_INTSTAT_ERRORINTERRUPT_Enum { SDIO_INTSTAT_ERRORINTERRUPT_NOERROR = 0
, SDIO_INTSTAT_ERRORINTERRUPT_ERROR = 1
} |
| |
| enum | SDIO_INTSTAT_BOOTTERMINATE_Enum { SDIO_INTSTAT_BOOTTERMINATE_OK = 0
, SDIO_INTSTAT_BOOTTERMINATE_BOOTTERM = 1
} |
| |
| enum | SDIO_INTSTAT_BOOTACKRCV_Enum { SDIO_INTSTAT_BOOTACKRCV_NOACK = 0
, SDIO_INTSTAT_BOOTACKRCV_ACK = 1
} |
| |
| enum | SDIO_INTSTAT_RETUNINGEVENT_Enum { SDIO_INTSTAT_RETUNINGEVENT_RETUNE = 1
, SDIO_INTSTAT_RETUNINGEVENT_NORETUNE = 0
} |
| |
| enum | SDIO_INTSTAT_CARDINTERRUPT_Enum { SDIO_INTSTAT_CARDINTERRUPT_NOINT = 0
, SDIO_INTSTAT_CARDINTERRUPT_INT = 1
} |
| |
| enum | SDIO_INTSTAT_CARDREMOVAL_Enum { SDIO_INTSTAT_CARDREMOVAL_STABLE = 0
, SDIO_INTSTAT_CARDREMOVAL_REMOVED = 1
} |
| |
| enum | SDIO_INTSTAT_CARDINSERTION_Enum { SDIO_INTSTAT_CARDINSERTION_STABLE = 0
, SDIO_INTSTAT_CARDINSERTION_INSERTED = 1
} |
| |
| enum | SDIO_INTSTAT_BUFFERREADREADY_Enum { SDIO_INTSTAT_BUFFERREADREADY_NOREADY = 0
, SDIO_INTSTAT_BUFFERREADREADY_READY = 1
} |
| |
| enum | SDIO_INTSTAT_BUFFERWRITEREADY_Enum { SDIO_INTSTAT_BUFFERWRITEREADY_NOTREADY = 0
, SDIO_INTSTAT_BUFFERWRITEREADY_READY = 1
} |
| |
| enum | SDIO_INTSTAT_DMAINTERRUPT_Enum { SDIO_INTSTAT_DMAINTERRUPT_NOINT = 0
, SDIO_INTSTAT_DMAINTERRUPT_INT = 1
} |
| |
| enum | SDIO_INTSTAT_BLOCKGAPEVENT_Enum { SDIO_INTSTAT_BLOCKGAPEVENT_NOEVENT = 0
, SDIO_INTSTAT_BLOCKGAPEVENT_STOPPED = 1
} |
| |
| enum | SDIO_INTSTAT_TRANSFERCOMPLETE_Enum { SDIO_INTSTAT_TRANSFERCOMPLETE_NODATA = 0
, SDIO_INTSTAT_TRANSFERCOMPLETE_COMPLETE = 1
} |
| |
| enum | SDIO_INTSTAT_COMMANDCOMPLETE_Enum { SDIO_INTSTAT_COMMANDCOMPLETE_NOCMP = 0
, SDIO_INTSTAT_COMMANDCOMPLETE_CMDCMP = 1
} |
| |
| enum | SDIO_INTSIG_TGTRESPEN_Enum { SDIO_INTSIG_TGTRESPEN_MASKED = 0
, SDIO_INTSIG_TGTRESPEN_ENABLED = 1
} |
| |
| enum | SDIO_INTSIG_TUNINGERREN_Enum { SDIO_INTSIG_TUNINGERREN_MASKED = 0
, SDIO_INTSIG_TUNINGERREN_ENABLED = 1
} |
| |
| enum | SDIO_INTSIG_ADMAERREN_Enum { SDIO_INTSIG_ADMAERREN_MASKED = 0
, SDIO_INTSIG_ADMAERREN_ENABLED = 1
} |
| |
| enum | SDIO_INTSIG_AUTOCMD12ERREN_Enum { SDIO_INTSIG_AUTOCMD12ERREN_MASKED = 0
, SDIO_INTSIG_AUTOCMD12ERREN_ENABLED = 1
} |
| |
| enum | SDIO_INTSIG_CURRLMTERREN_Enum { SDIO_INTSIG_CURRLMTERREN_MASKED = 0
, SDIO_INTSIG_CURRLMTERREN_ENABLED = 1
} |
| |
| enum | SDIO_INTSIG_DATAENDERREN_Enum { SDIO_INTSIG_DATAENDERREN_MASKED = 0
, SDIO_INTSIG_DATAENDERREN_ENABLED = 1
} |
| |
| enum | SDIO_INTSIG_DATACRCERREN_Enum { SDIO_INTSIG_DATACRCERREN_MASKED = 0
, SDIO_INTSIG_DATACRCERREN_ENABLED = 1
} |
| |
| enum | SDIO_INTSIG_DATATOERROREN_Enum { SDIO_INTSIG_DATATOERROREN_MASKED = 0
, SDIO_INTSIG_DATATOERROREN_ENABLED = 1
} |
| |
| enum | SDIO_INTSIG_CMDIDXERREN_Enum { SDIO_INTSIG_CMDIDXERREN_MASKED = 0
, SDIO_INTSIG_CMDIDXERREN_ENABLED = 1
} |
| |
| enum | SDIO_INTSIG_CMDENDBITERREN_Enum { SDIO_INTSIG_CMDENDBITERREN_MASKED = 0
, SDIO_INTSIG_CMDENDBITERREN_ENABLED = 1
} |
| |
| enum | SDIO_INTSIG_CMDCRCERREN_Enum { SDIO_INTSIG_CMDCRCERREN_MASKED = 0
, SDIO_INTSIG_CMDCRCERREN_ENABLED = 1
} |
| |
| enum | SDIO_INTSIG_CMDTOERREN_Enum { SDIO_INTSIG_CMDTOERREN_MASKED = 0
, SDIO_INTSIG_CMDTOERREN_ENABLED = 1
} |
| |
| enum | SDIO_INTSIG_FIXED0_Enum { SDIO_INTSIG_FIXED0_MASKED = 0
, SDIO_INTSIG_FIXED0_ENABLED = 1
} |
| |
| enum | SDIO_INTSIG_BOOTTERM_Enum { SDIO_INTSIG_BOOTTERM_MASKED = 0
, SDIO_INTSIG_BOOTTERM_ENABLED = 1
} |
| |
| enum | SDIO_INTSIG_BOOTACKEN_Enum { SDIO_INTSIG_BOOTACKEN_MASKED = 0
, SDIO_INTSIG_BOOTACKEN_ENABLED = 1
} |
| |
| enum | SDIO_INTSIG_RETUNEEVENTEN_Enum { SDIO_INTSIG_RETUNEEVENTEN_MASKED = 0
, SDIO_INTSIG_RETUNEEVENTEN_ENABLED = 1
} |
| |
| enum | SDIO_INTSIG_INTCEN_Enum { SDIO_INTSIG_INTCEN_MASKED = 0
, SDIO_INTSIG_INTCEN_ENABLED = 1
} |
| |
| enum | SDIO_INTSIG_INTBEN_Enum { SDIO_INTSIG_INTBEN_MASKED = 0
, SDIO_INTSIG_INTBEN_ENABLED = 1
} |
| |
| enum | SDIO_INTSIG_INTAEN_Enum { SDIO_INTSIG_INTAEN_MASKED = 0
, SDIO_INTSIG_INTAEN_ENABLED = 1
} |
| |
| enum | SDIO_INTSIG_CARDINTEN_Enum { SDIO_INTSIG_CARDINTEN_MASKED = 0
, SDIO_INTSIG_CARDINTEN_ENABLED = 1
} |
| |
| enum | SDIO_INTSIG_CARDREMOVALEN_Enum { SDIO_INTSIG_CARDREMOVALEN_MASKED = 0
, SDIO_INTSIG_CARDREMOVALEN_ENABLED = 1
} |
| |
| enum | SDIO_INTSIG_CARDINSERTEN_Enum { SDIO_INTSIG_CARDINSERTEN_MASKED = 0
, SDIO_INTSIG_CARDINSERTEN_ENABLED = 1
} |
| |
| enum | SDIO_INTSIG_BUFFERRDEN_Enum { SDIO_INTSIG_BUFFERRDEN_MASKED = 0
, SDIO_INTSIG_BUFFERRDEN_ENABLED = 1
} |
| |
| enum | SDIO_INTSIG_BUFFERWREN_Enum { SDIO_INTSIG_BUFFERWREN_MASKED = 0
, SDIO_INTSIG_BUFFERWREN_ENABLED = 1
} |
| |
| enum | SDIO_INTSIG_DMAINTEN_Enum { SDIO_INTSIG_DMAINTEN_MASKED = 0
, SDIO_INTSIG_DMAINTEN_ENABLED = 1
} |
| |
| enum | SDIO_INTSIG_BLOCKGAPEN_Enum { SDIO_INTSIG_BLOCKGAPEN_MASKED = 0
, SDIO_INTSIG_BLOCKGAPEN_ENABLED = 1
} |
| |
| enum | SDIO_INTSIG_XFERCMPEN_Enum { SDIO_INTSIG_XFERCMPEN_MASKED = 0
, SDIO_INTSIG_XFERCMPEN_ENABLED = 1
} |
| |
| enum | SDIO_INTSIG_CMDCMPEN_Enum { SDIO_INTSIG_CMDCMPEN_MASKED = 0
, SDIO_INTSIG_CMDCMPEN_ENABLED = 1
} |
| |
| enum | SDIO_AUTO_PRESETEN_Enum { SDIO_AUTO_PRESETEN_AUTOEN = 1
, SDIO_AUTO_PRESETEN_HOSTCTRL = 0
} |
| |
| enum | SDIO_AUTO_ASYNCINTEN_Enum { SDIO_AUTO_ASYNCINTEN_ENABLED = 1
, SDIO_AUTO_ASYNCINTEN_DISABLED = 0
} |
| |
| enum | SDIO_AUTO_SAMPLCLKSEL_Enum { SDIO_AUTO_SAMPLCLKSEL_TUNEDCLK = 1
, SDIO_AUTO_SAMPLCLKSEL_FIXEDCLK = 0
} |
| |
| enum | SDIO_AUTO_STARTTUNING_Enum { SDIO_AUTO_STARTTUNING_TUNESTART = 1
, SDIO_AUTO_STARTTUNING_TUNECMP = 0
} |
| |
| enum | SDIO_AUTO_DRVRSTRSEL_Enum { SDIO_AUTO_DRVRSTRSEL_DRVRB = 0
, SDIO_AUTO_DRVRSTRSEL_DRVRA = 1
, SDIO_AUTO_DRVRSTRSEL_DRVRC = 2
, SDIO_AUTO_DRVRSTRSEL_DRVRD = 3
} |
| |
| enum | SDIO_AUTO_SIGNALVOLT_Enum { SDIO_AUTO_SIGNALVOLT_1_8V = 1
, SDIO_AUTO_SIGNALVOLT_3_3V = 0
} |
| |
| enum | SDIO_AUTO_UHSMODESEL_Enum {
SDIO_AUTO_UHSMODESEL_SDR12 = 0
, SDIO_AUTO_UHSMODESEL_SDR25 = 1
, SDIO_AUTO_UHSMODESEL_SDR50 = 2
, SDIO_AUTO_UHSMODESEL_SDR104 = 3
,
SDIO_AUTO_UHSMODESEL_DDR50 = 4
} |
| |
| enum | SDIO_AUTO_NOTAUTOCMD12ERR_Enum { SDIO_AUTO_NOTAUTOCMD12ERR_NOERROR = 0
, SDIO_AUTO_NOTAUTOCMD12ERR_ERROR = 1
} |
| |
| enum | SDIO_AUTO_CMDIDXERR_Enum { SDIO_AUTO_CMDIDXERR_NOERROR = 0
, SDIO_AUTO_CMDIDXERR_ERROR = 1
} |
| |
| enum | SDIO_AUTO_CMDENDERR_Enum { SDIO_AUTO_CMDENDERR_NOERROR = 0
, SDIO_AUTO_CMDENDERR_ERROR = 1
} |
| |
| enum | SDIO_AUTO_CMDCRCERR_Enum { SDIO_AUTO_CMDCRCERR_NOERROR = 0
, SDIO_AUTO_CMDCRCERR_ERROR = 1
} |
| |
| enum | SDIO_AUTO_CMDTOERR_Enum { SDIO_AUTO_CMDTOERR_NOERROR = 0
, SDIO_AUTO_CMDTOERR_ERROR = 1
} |
| |
| enum | SDIO_AUTO_CMD12NOTEXEC_Enum { SDIO_AUTO_CMD12NOTEXEC_EXECUTED = 0
, SDIO_AUTO_CMD12NOTEXEC_NOTEXECUTED = 1
} |
| |
| enum | SDIO_CAPABILITIES0_SLOTTYPE_Enum { SDIO_CAPABILITIES0_SLOTTYPE_REMOVABLE = 0
, SDIO_CAPABILITIES0_SLOTTYPE_EMBEDDED = 1
, SDIO_CAPABILITIES0_SLOTTYPE_SHARED = 2
} |
| |
| enum | SDIO_CAPABILITIES0_ASYNCINT_Enum { SDIO_CAPABILITIES0_ASYNCINT_SUPPORTED = 1
, SDIO_CAPABILITIES0_ASYNCINT_NOTSUPPORTED = 0
} |
| |
| enum | SDIO_CAPABILITIES0_SYSBUS64_Enum { SDIO_CAPABILITIES0_SYSBUS64_SUPPORTED = 1
, SDIO_CAPABILITIES0_SYSBUS64_NOTSUPPORTED = 0
} |
| |
| enum | SDIO_CAPABILITIES0_VOLT18V_Enum { SDIO_CAPABILITIES0_VOLT18V_NOTSUPPORTED = 0
, SDIO_CAPABILITIES0_VOLT18V_SUPPORTED = 1
} |
| |
| enum | SDIO_CAPABILITIES0_VOLT30V_Enum { SDIO_CAPABILITIES0_VOLT30V_NOTSUPPORTED = 0
, SDIO_CAPABILITIES0_VOLT30V_SUPPORTED = 1
} |
| |
| enum | SDIO_CAPABILITIES0_VOLT33V_Enum { SDIO_CAPABILITIES0_VOLT33V_NOTSUPPORTED = 0
, SDIO_CAPABILITIES0_VOLT33V_SUPPORTED = 1
} |
| |
| enum | SDIO_CAPABILITIES0_SUSPRES_Enum { SDIO_CAPABILITIES0_SUSPRES_NOTSUPPORTED = 0
, SDIO_CAPABILITIES0_SUSPRES_SUPPORTED = 1
} |
| |
| enum | SDIO_CAPABILITIES0_SDMA_Enum { SDIO_CAPABILITIES0_SDMA_NOTSUPPORTED = 0
, SDIO_CAPABILITIES0_SDMA_SUPPORTED = 1
} |
| |
| enum | SDIO_CAPABILITIES0_HIGHSPEED_Enum { SDIO_CAPABILITIES0_HIGHSPEED_NOTSUPPORTED = 0
, SDIO_CAPABILITIES0_HIGHSPEED_SUPPORTED = 1
} |
| |
| enum | SDIO_CAPABILITIES0_ADMA2_Enum { SDIO_CAPABILITIES0_ADMA2_SUPPORTED = 1
, SDIO_CAPABILITIES0_ADMA2_NOTSUPPORTED = 0
} |
| |
| enum | SDIO_CAPABILITIES0_EXTMEDIA_Enum { SDIO_CAPABILITIES0_EXTMEDIA_SUPPORTED = 1
, SDIO_CAPABILITIES0_EXTMEDIA_NOTSUPPORTED = 0
} |
| |
| enum | SDIO_CAPABILITIES0_MAXBLKLEN_Enum { SDIO_CAPABILITIES0_MAXBLKLEN_512 = 0
, SDIO_CAPABILITIES0_MAXBLKLEN_1024 = 1
, SDIO_CAPABILITIES0_MAXBLKLEN_2048 = 2
, SDIO_CAPABILITIES0_MAXBLKLEN_4096 = 3
} |
| |
| enum | SDIO_CAPABILITIES0_SDCLKFREQ_Enum {
SDIO_CAPABILITIES0_SDCLKFREQ_255MHZ = 255
, SDIO_CAPABILITIES0_SDCLKFREQ_63MHZ = 63
, SDIO_CAPABILITIES0_SDCLKFREQ_2MHZ = 2
, SDIO_CAPABILITIES0_SDCLKFREQ_1MHZ = 1
,
SDIO_CAPABILITIES0_SDCLKFREQ_OTHER = 0
} |
| |
| enum | SDIO_CAPABILITIES0_TOCLKUNIT_Enum { SDIO_CAPABILITIES0_TOCLKUNIT_KHZ = 0
, SDIO_CAPABILITIES0_TOCLKUNIT_MHZ = 1
} |
| |
| enum | SDIO_CAPABILITIES0_TOCLKFREQ_Enum { SDIO_CAPABILITIES0_TOCLKFREQ_1 = 1
, SDIO_CAPABILITIES0_TOCLKFREQ_2 = 2
, SDIO_CAPABILITIES0_TOCLKFREQ_63 = 63
, SDIO_CAPABILITIES0_TOCLKFREQ_OTHER = 0
} |
| |
| enum | SDIO_CAPABILITIES1_SPIBLOCKMODE_Enum { SDIO_CAPABILITIES1_SPIBLOCKMODE_NOTSUPPORTED = 0
, SDIO_CAPABILITIES1_SPIBLOCKMODE_SUPPORTED = 1
} |
| |
| enum | SDIO_CAPABILITIES1_SPIMODE_Enum { SDIO_CAPABILITIES1_SPIMODE_NOTSUPPORTED = 0
, SDIO_CAPABILITIES1_SPIMODE_SUPPORTED = 1
} |
| |
| enum | SDIO_CAPABILITIES1_CLKMULT_Enum { SDIO_CAPABILITIES1_CLKMULT_MULTX256 = 255
, SDIO_CAPABILITIES1_CLKMULT_MULTX3 = 2
, SDIO_CAPABILITIES1_CLKMULT_MULTX2 = 1
, SDIO_CAPABILITIES1_CLKMULT_NOTSUPPORTED = 0
} |
| |
| enum | SDIO_CAPABILITIES1_RETUNINGMODES_Enum { SDIO_CAPABILITIES1_RETUNINGMODES_MODE1 = 0
, SDIO_CAPABILITIES1_RETUNINGMODES_MODE2 = 1
, SDIO_CAPABILITIES1_RETUNINGMODES_MODE3 = 2
, SDIO_CAPABILITIES1_RETUNINGMODES_NOTSUPPORTED = 3
} |
| |
| enum | SDIO_CAPABILITIES1_TUNINGSDR50_Enum { SDIO_CAPABILITIES1_TUNINGSDR50_TUNINGREQD = 1
, SDIO_CAPABILITIES1_TUNINGSDR50_NOTUNINGREQD = 0
} |
| |
| enum | SDIO_CAPABILITIES1_RETUNINGTMRCNT_Enum {
SDIO_CAPABILITIES1_RETUNINGTMRCNT_OTHER = 0
, SDIO_CAPABILITIES1_RETUNINGTMRCNT_1SEC = 1
, SDIO_CAPABILITIES1_RETUNINGTMRCNT_2SEC = 2
, SDIO_CAPABILITIES1_RETUNINGTMRCNT_4SEC = 3
,
SDIO_CAPABILITIES1_RETUNINGTMRCNT_8S = 4
, SDIO_CAPABILITIES1_RETUNINGTMRCNT_16S = 5
, SDIO_CAPABILITIES1_RETUNINGTMRCNT_32S = 6
, SDIO_CAPABILITIES1_RETUNINGTMRCNT_64S = 7
,
SDIO_CAPABILITIES1_RETUNINGTMRCNT_128S = 8
, SDIO_CAPABILITIES1_RETUNINGTMRCNT_256S = 9
, SDIO_CAPABILITIES1_RETUNINGTMRCNT_512S = 10
, SDIO_CAPABILITIES1_RETUNINGTMRCNT_1024S = 11
} |
| |
| enum | SDIO_CAPABILITIES1_TYPED_Enum { SDIO_CAPABILITIES1_TYPED_SUPPORTED = 1
, SDIO_CAPABILITIES1_TYPED_NOTSUPPORTED = 0
} |
| |
| enum | SDIO_CAPABILITIES1_TYPEC_Enum { SDIO_CAPABILITIES1_TYPEC_SUPPORTED = 1
, SDIO_CAPABILITIES1_TYPEC_NOTSUPPORTED = 0
} |
| |
| enum | SDIO_CAPABILITIES1_TYPEA_Enum { SDIO_CAPABILITIES1_TYPEA_SUPPORTED = 1
, SDIO_CAPABILITIES1_TYPEA_NOTSUPPORTED = 0
} |
| |
| enum | SDIO_CAPABILITIES1_DDR50_Enum { SDIO_CAPABILITIES1_DDR50_SUPPORTED = 1
, SDIO_CAPABILITIES1_DDR50_NOTSUPPORTED = 0
} |
| |
| enum | SDIO_CAPABILITIES1_SDR104_Enum { SDIO_CAPABILITIES1_SDR104_SUPPORTED = 1
, SDIO_CAPABILITIES1_SDR104_NOTSUPPORTED = 0
} |
| |
| enum | SDIO_CAPABILITIES1_SDR50_Enum { SDIO_CAPABILITIES1_SDR50_SUPPORTED = 1
, SDIO_CAPABILITIES1_SDR50_NOTSUPPORTED = 0
} |
| |
| enum | SDIO_MAXIMUM1_MAXCURR18V_Enum { SDIO_MAXIMUM1_MAXCURR18V_1020mA = 255
, SDIO_MAXIMUM1_MAXCURR18V_4mA = 1
} |
| |
| enum | SDIO_MAXIMUM1_MAXCURR30V_Enum { SDIO_MAXIMUM1_MAXCURR30V_1020mA = 255
, SDIO_MAXIMUM1_MAXCURR30V_4mA = 1
} |
| |
| enum | SDIO_MAXIMUM1_MAXCURR33V_Enum { SDIO_MAXIMUM1_MAXCURR33V_1020mA = 255
, SDIO_MAXIMUM1_MAXCURR33V_4mA = 1
} |
| |
| enum | SDIO_FORCE_FORCEADMAERR_Enum { SDIO_FORCE_FORCEADMAERR_INT = 1
, SDIO_FORCE_FORCEADMAERR_NOINT = 0
} |
| |
| enum | SDIO_FORCE_FORCEACMDERR_Enum { SDIO_FORCE_FORCEACMDERR_INT = 1
, SDIO_FORCE_FORCEACMDERR_NOINT = 0
} |
| |
| enum | SDIO_FORCE_FORCECURRLIMITERR_Enum { SDIO_FORCE_FORCECURRLIMITERR_INT = 1
, SDIO_FORCE_FORCECURRLIMITERR_NOINT = 0
} |
| |
| enum | SDIO_FORCE_FORCEDATAENDERR_Enum { SDIO_FORCE_FORCEDATAENDERR_INT = 1
, SDIO_FORCE_FORCEDATAENDERR_NOINT = 0
} |
| |
| enum | SDIO_FORCE_FORCEDATACRCERR_Enum { SDIO_FORCE_FORCEDATACRCERR_INT = 1
, SDIO_FORCE_FORCEDATACRCERR_NOINT = 0
} |
| |
| enum | SDIO_FORCE_FORCEDATATOERR_Enum { SDIO_FORCE_FORCEDATATOERR_INT = 1
, SDIO_FORCE_FORCEDATATOERR_NOINT = 0
} |
| |
| enum | SDIO_FORCE_FORCECMDIDXERR_Enum { SDIO_FORCE_FORCECMDIDXERR_INT = 1
, SDIO_FORCE_FORCECMDIDXERR_NOINT = 0
} |
| |
| enum | SDIO_FORCE_FORCECMDENDERR_Enum { SDIO_FORCE_FORCECMDENDERR_INT = 1
, SDIO_FORCE_FORCECMDENDERR_NOINT = 0
} |
| |
| enum | SDIO_FORCE_FORCECMDCRCERR_Enum { SDIO_FORCE_FORCECMDCRCERR_INT = 1
, SDIO_FORCE_FORCECMDCRCERR_NOINT = 0
} |
| |
| enum | SDIO_FORCE_FORCECMDTOERR_Enum { SDIO_FORCE_FORCECMDTOERR_INT = 1
, SDIO_FORCE_FORCECMDTOERR_NOINT = 0
} |
| |
| enum | SDIO_FORCE_FORCEACMDISSUEDERR_Enum { SDIO_FORCE_FORCEACMDISSUEDERR_INT = 1
, SDIO_FORCE_FORCEACMDISSUEDERR_NOINT = 0
} |
| |
| enum | SDIO_FORCE_FORCEACMDIDXERR_Enum { SDIO_FORCE_FORCEACMDIDXERR_INT = 1
, SDIO_FORCE_FORCEACMDIDXERR_NOINT = 0
} |
| |
| enum | SDIO_FORCE_FORCEACMDENDERR_Enum { SDIO_FORCE_FORCEACMDENDERR_INT = 1
, SDIO_FORCE_FORCEACMDENDERR_NOINT = 0
} |
| |
| enum | SDIO_FORCE_FORCEACMDCRCERR_Enum { SDIO_FORCE_FORCEACMDCRCERR_INT = 1
, SDIO_FORCE_FORCEACMDCRCERR_NOINT = 0
} |
| |
| enum | SDIO_FORCE_FORCEACMDTOERR_Enum { SDIO_FORCE_FORCEACMDTOERR_INT = 1
, SDIO_FORCE_FORCEACMDTOERR_NOINT = 0
} |
| |
| enum | SDIO_FORCE_FORCEACMD12NOT_Enum { SDIO_FORCE_FORCEACMD12NOT_INT = 1
, SDIO_FORCE_FORCEACMD12NOT_NOINT = 0
} |
| |
| enum | SDIO_ADMA_ADMALENMISMATCHERR_Enum { SDIO_ADMA_ADMALENMISMATCHERR_ERROR = 1
, SDIO_ADMA_ADMALENMISMATCHERR_NOERROR = 0
} |
| |
| enum | SDIO_ADMA_ADMAERRORSTATE_Enum { SDIO_ADMA_ADMAERRORSTATE_STDMA = 0
, SDIO_ADMA_ADMAERRORSTATE_FETCHDESC = 1
, SDIO_ADMA_ADMAERRORSTATE_INVALID = 2
, SDIO_ADMA_ADMAERRORSTATE_XFERDATA = 3
} |
| |
| enum | SDIO_PRESET0_DEFSPDRVRSTRSEL_Enum { SDIO_PRESET0_DEFSPDRVRSTRSEL_TYPED = 3
, SDIO_PRESET0_DEFSPDRVRSTRSEL_TYPEC = 2
, SDIO_PRESET0_DEFSPDRVRSTRSEL_TYPEA = 1
, SDIO_PRESET0_DEFSPDRVRSTRSEL_TYPEB = 0
} |
| |
| enum | SDIO_PRESET0_DEFSPCLKGENSEL_Enum { SDIO_PRESET0_DEFSPCLKGENSEL_PROGCLK = 1
, SDIO_PRESET0_DEFSPCLKGENSEL_HOSTCTLR = 0
} |
| |
| enum | SDIO_PRESET0_HISPDRVRSTRSEL_Enum { SDIO_PRESET0_HISPDRVRSTRSEL_TYPED = 3
, SDIO_PRESET0_HISPDRVRSTRSEL_TYPEC = 2
, SDIO_PRESET0_HISPDRVRSTRSEL_TYPEA = 1
, SDIO_PRESET0_HISPDRVRSTRSEL_TYPEB = 0
} |
| |
| enum | SDIO_PRESET0_HISPCLKGENSEL_Enum { SDIO_PRESET0_HISPCLKGENSEL_PROGCLK = 1
, SDIO_PRESET0_HISPCLKGENSEL_HOSTCTLR = 0
} |
| |
| enum | SDIO_PRESET1_SDR12DRVRSTRSEL_Enum { SDIO_PRESET1_SDR12DRVRSTRSEL_TYPED = 3
, SDIO_PRESET1_SDR12DRVRSTRSEL_TYPEC = 2
, SDIO_PRESET1_SDR12DRVRSTRSEL_TYPEA = 1
, SDIO_PRESET1_SDR12DRVRSTRSEL_TYPEB = 0
} |
| |
| enum | SDIO_PRESET1_SDR12CLKGENSEL_Enum { SDIO_PRESET1_SDR12CLKGENSEL_PROGCLK = 1
, SDIO_PRESET1_SDR12CLKGENSEL_HOSTCTLR = 0
} |
| |
| enum | SDIO_PRESET1_HSDRVRSTRSEL_Enum { SDIO_PRESET1_HSDRVRSTRSEL_TYPED = 3
, SDIO_PRESET1_HSDRVRSTRSEL_TYPEC = 2
, SDIO_PRESET1_HSDRVRSTRSEL_TYPEA = 1
, SDIO_PRESET1_HSDRVRSTRSEL_TYPEB = 0
} |
| |
| enum | SDIO_PRESET1_HSCLKGENSEL_Enum { SDIO_PRESET1_HSCLKGENSEL_PROGCLK = 1
, SDIO_PRESET1_HSCLKGENSEL_HOSTCTLR = 0
} |
| |
| enum | SDIO_PRESET2_SDR50DRVRSTRSEL_Enum { SDIO_PRESET2_SDR50DRVRSTRSEL_TYPED = 3
, SDIO_PRESET2_SDR50DRVRSTRSEL_TYPEC = 2
, SDIO_PRESET2_SDR50DRVRSTRSEL_TYPEA = 1
, SDIO_PRESET2_SDR50DRVRSTRSEL_TYPEB = 0
} |
| |
| enum | SDIO_PRESET2_SDR50CLKGENSEL_Enum { SDIO_PRESET2_SDR50CLKGENSEL_PROGCLK = 1
, SDIO_PRESET2_SDR50CLKGENSEL_HOSTCTLR = 0
} |
| |
| enum | SDIO_PRESET2_SDR25DRVRSTRSEL_Enum { SDIO_PRESET2_SDR25DRVRSTRSEL_TYPED = 3
, SDIO_PRESET2_SDR25DRVRSTRSEL_TYPEC = 2
, SDIO_PRESET2_SDR25DRVRSTRSEL_TYPEA = 1
, SDIO_PRESET2_SDR25DRVRSTRSEL_TYPEB = 0
} |
| |
| enum | SDIO_PRESET2_SDR25CLKGENSEL_Enum { SDIO_PRESET2_SDR25CLKGENSEL_PROGCLK = 1
, SDIO_PRESET2_SDR25CLKGENSEL_HOSTCTLR = 0
} |
| |
| enum | SDIO_PRESET3_DDR50DRVRSTRSEL_Enum { SDIO_PRESET3_DDR50DRVRSTRSEL_TYPED = 3
, SDIO_PRESET3_DDR50DRVRSTRSEL_TYPEC = 2
, SDIO_PRESET3_DDR50DRVRSTRSEL_TYPEA = 1
, SDIO_PRESET3_DDR50DRVRSTRSEL_TYPEB = 0
} |
| |
| enum | SDIO_PRESET3_DDR50CLKGENSEL_Enum { SDIO_PRESET3_DDR50CLKGENSEL_PROGCLK = 1
, SDIO_PRESET3_DDR50CLKGENSEL_HOSTCTLR = 0
} |
| |
| enum | SDIO_PRESET3_SDR104DRVRSTRSEL_Enum { SDIO_PRESET3_SDR104DRVRSTRSEL_TYPED = 3
, SDIO_PRESET3_SDR104DRVRSTRSEL_TYPEC = 2
, SDIO_PRESET3_SDR104DRVRSTRSEL_TYPEA = 1
, SDIO_PRESET3_SDR104DRVRSTRSEL_TYPEB = 0
} |
| |
| enum | SDIO_PRESET3_SDR104CLKGENSEL_Enum { SDIO_PRESET3_SDR104CLKGENSEL_PROGCLK = 1
, SDIO_PRESET3_SDR104CLKGENSEL_HOSTCTLR = 0
} |
| |
| enum | SDIO_VENDOR_DLYDIS_Enum { SDIO_VENDOR_DLYDIS_DISABLE = 1
, SDIO_VENDOR_DLYDIS_ENABLE = 0
} |
| |
| enum | SDIO_VENDOR_GATESDCLKEN_Enum { SDIO_VENDOR_GATESDCLKEN_GATE = 1
, SDIO_VENDOR_GATESDCLKEN_NOGATE = 0
} |
| |
| enum | SECURITY_CTRL_FUNCTION_Enum { SECURITY_CTRL_FUNCTION_CRC32 = 0
, SECURITY_CTRL_FUNCTION_RAND = 1
, SECURITY_CTRL_FUNCTION_GENADDR = 2
} |
| |
| enum | SECURITY_LOCKCTRL_SELECT_Enum {
SECURITY_LOCKCTRL_SELECT_LOCK01 = 1
, SECURITY_LOCKCTRL_SELECT_LOCK02 = 2
, SECURITY_LOCKCTRL_SELECT_LOCK11 = 17
, SECURITY_LOCKCTRL_SELECT_LOCK12 = 18
,
SECURITY_LOCKCTRL_SELECT_LOCK9D = 157
, SECURITY_LOCKCTRL_SELECT_LOCK9E = 158
, SECURITY_LOCKCTRL_SELECT_RESET = 0
} |
| |
| enum | SECURITY_LOCKSTAT_STATUS_Enum {
SECURITY_LOCKSTAT_STATUS_LOCK01 = 1
, SECURITY_LOCKSTAT_STATUS_LOCK02 = 2
, SECURITY_LOCKSTAT_STATUS_LOCK11 = 16
, SECURITY_LOCKSTAT_STATUS_LOCK12 = 32
,
SECURITY_LOCKSTAT_STATUS_LOCK9D = 1073741824
, SECURITY_LOCKSTAT_STATUS_LOCK9E = -2147483648
, SECURITY_LOCKSTAT_STATUS_RESET = 0
} |
| |
| enum | STIMER_STCFG_FREEZE_Enum { STIMER_STCFG_FREEZE_THAW = 0
, STIMER_STCFG_FREEZE_FREEZE = 1
} |
| |
| enum | STIMER_STCFG_CLEAR_Enum { STIMER_STCFG_CLEAR_RUN = 0
, STIMER_STCFG_CLEAR_CLEAR = 1
} |
| |
| enum | STIMER_STCFG_COMPAREHEN_Enum { STIMER_STCFG_COMPAREHEN_DISABLE = 0
, STIMER_STCFG_COMPAREHEN_ENABLE = 1
} |
| |
| enum | STIMER_STCFG_COMPAREGEN_Enum { STIMER_STCFG_COMPAREGEN_DISABLE = 0
, STIMER_STCFG_COMPAREGEN_ENABLE = 1
} |
| |
| enum | STIMER_STCFG_COMPAREFEN_Enum { STIMER_STCFG_COMPAREFEN_DISABLE = 0
, STIMER_STCFG_COMPAREFEN_ENABLE = 1
} |
| |
| enum | STIMER_STCFG_COMPAREEEN_Enum { STIMER_STCFG_COMPAREEEN_DISABLE = 0
, STIMER_STCFG_COMPAREEEN_ENABLE = 1
} |
| |
| enum | STIMER_STCFG_COMPAREDEN_Enum { STIMER_STCFG_COMPAREDEN_DISABLE = 0
, STIMER_STCFG_COMPAREDEN_ENABLE = 1
} |
| |
| enum | STIMER_STCFG_COMPARECEN_Enum { STIMER_STCFG_COMPARECEN_DISABLE = 0
, STIMER_STCFG_COMPARECEN_ENABLE = 1
} |
| |
| enum | STIMER_STCFG_COMPAREBEN_Enum { STIMER_STCFG_COMPAREBEN_DISABLE = 0
, STIMER_STCFG_COMPAREBEN_ENABLE = 1
} |
| |
| enum | STIMER_STCFG_COMPAREAEN_Enum { STIMER_STCFG_COMPAREAEN_DISABLE = 0
, STIMER_STCFG_COMPAREAEN_ENABLE = 1
} |
| |
| enum | STIMER_STCFG_CLKSEL_Enum {
STIMER_STCFG_CLKSEL_NOCLK = 0
, STIMER_STCFG_CLKSEL_HFRC_6MHZ = 1
, STIMER_STCFG_CLKSEL_HFRC_375KHZ = 2
, STIMER_STCFG_CLKSEL_XTAL_32KHZ = 3
,
STIMER_STCFG_CLKSEL_XTAL_16KHZ = 4
, STIMER_STCFG_CLKSEL_XTAL_1KHZ = 5
, STIMER_STCFG_CLKSEL_LFRC_1KHZ = 6
, STIMER_STCFG_CLKSEL_CTIMER0 = 7
,
STIMER_STCFG_CLKSEL_CTIMER1 = 8
} |
| |
| enum | STIMER_SCAPCTRL0_CAPTURE0_Enum { STIMER_SCAPCTRL0_CAPTURE0_DISABLE = 0
, STIMER_SCAPCTRL0_CAPTURE0_ENABLE = 1
} |
| |
| enum | STIMER_SCAPCTRL0_STPOL0_Enum { STIMER_SCAPCTRL0_STPOL0_CAPLH = 0
, STIMER_SCAPCTRL0_STPOL0_CAPHL = 1
} |
| |
| enum | STIMER_SCAPCTRL1_CAPTURE1_Enum { STIMER_SCAPCTRL1_CAPTURE1_DISABLE = 0
, STIMER_SCAPCTRL1_CAPTURE1_ENABLE = 1
} |
| |
| enum | STIMER_SCAPCTRL1_STPOL1_Enum { STIMER_SCAPCTRL1_STPOL1_CAPLH = 0
, STIMER_SCAPCTRL1_STPOL1_CAPHL = 1
} |
| |
| enum | STIMER_SCAPCTRL2_CAPTURE2_Enum { STIMER_SCAPCTRL2_CAPTURE2_DISABLE = 0
, STIMER_SCAPCTRL2_CAPTURE2_ENABLE = 1
} |
| |
| enum | STIMER_SCAPCTRL2_STPOL2_Enum { STIMER_SCAPCTRL2_STPOL2_CAPLH = 0
, STIMER_SCAPCTRL2_STPOL2_CAPHL = 1
} |
| |
| enum | STIMER_SCAPCTRL3_CAPTURE3_Enum { STIMER_SCAPCTRL3_CAPTURE3_DISABLE = 0
, STIMER_SCAPCTRL3_CAPTURE3_ENABLE = 1
} |
| |
| enum | STIMER_SCAPCTRL3_STPOL3_Enum { STIMER_SCAPCTRL3_STPOL3_CAPLH = 0
, STIMER_SCAPCTRL3_STPOL3_CAPHL = 1
} |
| |
| enum | STIMER_STMINTEN_CAPTURED_Enum { STIMER_STMINTEN_CAPTURED_CAPD_INT = 1
, STIMER_STMINTEN_CAPTURED_CAPD_DEFAULT = 0
} |
| |
| enum | STIMER_STMINTEN_CAPTUREC_Enum { STIMER_STMINTEN_CAPTUREC_CAPC_INT = 1
, STIMER_STMINTEN_CAPTUREC_CAPC_DEFAULT = 0
} |
| |
| enum | STIMER_STMINTEN_CAPTUREB_Enum { STIMER_STMINTEN_CAPTUREB_CAPB_INT = 1
, STIMER_STMINTEN_CAPTUREB_CAPB_DEFAULT = 0
} |
| |
| enum | STIMER_STMINTEN_CAPTUREA_Enum { STIMER_STMINTEN_CAPTUREA_CAPA_INT = 1
, STIMER_STMINTEN_CAPTUREA_CAPA_DEFAULT = 0
} |
| |
| enum | STIMER_STMINTEN_OVERFLOW_Enum { STIMER_STMINTEN_OVERFLOW_OFLOW_INT = 1
, STIMER_STMINTEN_OVERFLOW_OFLOW_DEFAULT = 0
} |
| |
| enum | STIMER_STMINTEN_COMPAREH_Enum { STIMER_STMINTEN_COMPAREH_COMPARED = 1
, STIMER_STMINTEN_COMPAREH_DEFAULT = 0
} |
| |
| enum | STIMER_STMINTEN_COMPAREG_Enum { STIMER_STMINTEN_COMPAREG_COMPARED = 1
, STIMER_STMINTEN_COMPAREG_DEFAULT = 0
} |
| |
| enum | STIMER_STMINTEN_COMPAREF_Enum { STIMER_STMINTEN_COMPAREF_COMPARED = 1
, STIMER_STMINTEN_COMPAREF_DEFAULT = 0
} |
| |
| enum | STIMER_STMINTEN_COMPAREE_Enum { STIMER_STMINTEN_COMPAREE_COMPARED = 1
, STIMER_STMINTEN_COMPAREE_DEFAULT = 0
} |
| |
| enum | STIMER_STMINTEN_COMPARED_Enum { STIMER_STMINTEN_COMPARED_COMPARED = 1
, STIMER_STMINTEN_COMPARED_DEFAULT = 0
} |
| |
| enum | STIMER_STMINTEN_COMPAREC_Enum { STIMER_STMINTEN_COMPAREC_COMPARED = 1
, STIMER_STMINTEN_COMPAREC_DEFAULT = 0
} |
| |
| enum | STIMER_STMINTEN_COMPAREB_Enum { STIMER_STMINTEN_COMPAREB_COMPARED = 1
, STIMER_STMINTEN_COMPAREB_DEFAULT = 0
} |
| |
| enum | STIMER_STMINTEN_COMPAREA_Enum { STIMER_STMINTEN_COMPAREA_COMPARED = 1
, STIMER_STMINTEN_COMPAREA_DEFAULT = 0
} |
| |
| enum | STIMER_STMINTSTAT_CAPTURED_Enum { STIMER_STMINTSTAT_CAPTURED_CAPD_INT = 1
, STIMER_STMINTSTAT_CAPTURED_CAPD_DEFAULT = 0
} |
| |
| enum | STIMER_STMINTSTAT_CAPTUREC_Enum { STIMER_STMINTSTAT_CAPTUREC_CAPC_INT = 1
, STIMER_STMINTSTAT_CAPTUREC_CAPC_DEFAULT = 0
} |
| |
| enum | STIMER_STMINTSTAT_CAPTUREB_Enum { STIMER_STMINTSTAT_CAPTUREB_CAPB_INT = 1
, STIMER_STMINTSTAT_CAPTUREB_CAPB_DEFAULT = 0
} |
| |
| enum | STIMER_STMINTSTAT_CAPTUREA_Enum { STIMER_STMINTSTAT_CAPTUREA_CAPA_INT = 1
, STIMER_STMINTSTAT_CAPTUREA_CAPA_DEFAULT = 0
} |
| |
| enum | STIMER_STMINTSTAT_OVERFLOW_Enum { STIMER_STMINTSTAT_OVERFLOW_OFLOW_INT = 1
, STIMER_STMINTSTAT_OVERFLOW_OFLOW_DEFAULT = 0
} |
| |
| enum | STIMER_STMINTSTAT_COMPAREH_Enum { STIMER_STMINTSTAT_COMPAREH_COMPARED = 1
, STIMER_STMINTSTAT_COMPAREH_DEFAULT = 0
} |
| |
| enum | STIMER_STMINTSTAT_COMPAREG_Enum { STIMER_STMINTSTAT_COMPAREG_COMPARED = 1
, STIMER_STMINTSTAT_COMPAREG_DEFAULT = 0
} |
| |
| enum | STIMER_STMINTSTAT_COMPAREF_Enum { STIMER_STMINTSTAT_COMPAREF_COMPARED = 1
, STIMER_STMINTSTAT_COMPAREF_DEFAULT = 0
} |
| |
| enum | STIMER_STMINTSTAT_COMPAREE_Enum { STIMER_STMINTSTAT_COMPAREE_COMPARED = 1
, STIMER_STMINTSTAT_COMPAREE_DEFAULT = 0
} |
| |
| enum | STIMER_STMINTSTAT_COMPARED_Enum { STIMER_STMINTSTAT_COMPARED_COMPARED = 1
, STIMER_STMINTSTAT_COMPARED_DEFAULT = 0
} |
| |
| enum | STIMER_STMINTSTAT_COMPAREC_Enum { STIMER_STMINTSTAT_COMPAREC_COMPARED = 1
, STIMER_STMINTSTAT_COMPAREC_DEFAULT = 0
} |
| |
| enum | STIMER_STMINTSTAT_COMPAREB_Enum { STIMER_STMINTSTAT_COMPAREB_COMPARED = 1
, STIMER_STMINTSTAT_COMPAREB_DEFAULT = 0
} |
| |
| enum | STIMER_STMINTSTAT_COMPAREA_Enum { STIMER_STMINTSTAT_COMPAREA_COMPARED = 1
, STIMER_STMINTSTAT_COMPAREA_DEFAULT = 0
} |
| |
| enum | STIMER_STMINTCLR_CAPTURED_Enum { STIMER_STMINTCLR_CAPTURED_CAPD_INT = 1
, STIMER_STMINTCLR_CAPTURED_CAPD_DEFAULT = 0
} |
| |
| enum | STIMER_STMINTCLR_CAPTUREC_Enum { STIMER_STMINTCLR_CAPTUREC_CAPC_INT = 1
, STIMER_STMINTCLR_CAPTUREC_CAPC_DEFAULT = 0
} |
| |
| enum | STIMER_STMINTCLR_CAPTUREB_Enum { STIMER_STMINTCLR_CAPTUREB_CAPB_INT = 1
, STIMER_STMINTCLR_CAPTUREB_CAPB_DEFAULT = 0
} |
| |
| enum | STIMER_STMINTCLR_CAPTUREA_Enum { STIMER_STMINTCLR_CAPTUREA_CAPA_INT = 1
, STIMER_STMINTCLR_CAPTUREA_CAPA_DEFAULT = 0
} |
| |
| enum | STIMER_STMINTCLR_OVERFLOW_Enum { STIMER_STMINTCLR_OVERFLOW_OFLOW_INT = 1
, STIMER_STMINTCLR_OVERFLOW_OFLOW_DEFAULT = 0
} |
| |
| enum | STIMER_STMINTCLR_COMPAREH_Enum { STIMER_STMINTCLR_COMPAREH_COMPARED = 1
, STIMER_STMINTCLR_COMPAREH_DEFAULT = 0
} |
| |
| enum | STIMER_STMINTCLR_COMPAREG_Enum { STIMER_STMINTCLR_COMPAREG_COMPARED = 1
, STIMER_STMINTCLR_COMPAREG_DEFAULT = 0
} |
| |
| enum | STIMER_STMINTCLR_COMPAREF_Enum { STIMER_STMINTCLR_COMPAREF_COMPARED = 1
, STIMER_STMINTCLR_COMPAREF_DEFAULT = 0
} |
| |
| enum | STIMER_STMINTCLR_COMPAREE_Enum { STIMER_STMINTCLR_COMPAREE_COMPARED = 1
, STIMER_STMINTCLR_COMPAREE_DEFAULT = 0
} |
| |
| enum | STIMER_STMINTCLR_COMPARED_Enum { STIMER_STMINTCLR_COMPARED_COMPARED = 1
, STIMER_STMINTCLR_COMPARED_DEFAULT = 0
} |
| |
| enum | STIMER_STMINTCLR_COMPAREC_Enum { STIMER_STMINTCLR_COMPAREC_COMPARED = 1
, STIMER_STMINTCLR_COMPAREC_DEFAULT = 0
} |
| |
| enum | STIMER_STMINTCLR_COMPAREB_Enum { STIMER_STMINTCLR_COMPAREB_COMPARED = 1
, STIMER_STMINTCLR_COMPAREB_DEFAULT = 0
} |
| |
| enum | STIMER_STMINTCLR_COMPAREA_Enum { STIMER_STMINTCLR_COMPAREA_COMPARED = 1
, STIMER_STMINTCLR_COMPAREA_DEFAULT = 0
} |
| |
| enum | STIMER_STMINTSET_CAPTURED_Enum { STIMER_STMINTSET_CAPTURED_CAPD_INT = 1
, STIMER_STMINTSET_CAPTURED_CAPD_DEFAULT = 0
} |
| |
| enum | STIMER_STMINTSET_CAPTUREC_Enum { STIMER_STMINTSET_CAPTUREC_CAPC_INT = 1
, STIMER_STMINTSET_CAPTUREC_CAPC_DEFAULT = 0
} |
| |
| enum | STIMER_STMINTSET_CAPTUREB_Enum { STIMER_STMINTSET_CAPTUREB_CAPB_INT = 1
, STIMER_STMINTSET_CAPTUREB_CAPB_DEFAULT = 0
} |
| |
| enum | STIMER_STMINTSET_CAPTUREA_Enum { STIMER_STMINTSET_CAPTUREA_CAPA_INT = 1
, STIMER_STMINTSET_CAPTUREA_CAPA_DEFAULT = 0
} |
| |
| enum | STIMER_STMINTSET_OVERFLOW_Enum { STIMER_STMINTSET_OVERFLOW_OFLOW_INT = 1
, STIMER_STMINTSET_OVERFLOW_OFLOW_DEFAULT = 0
} |
| |
| enum | STIMER_STMINTSET_COMPAREH_Enum { STIMER_STMINTSET_COMPAREH_COMPARED = 1
, STIMER_STMINTSET_COMPAREH_DEFAULT = 0
} |
| |
| enum | STIMER_STMINTSET_COMPAREG_Enum { STIMER_STMINTSET_COMPAREG_COMPARED = 1
, STIMER_STMINTSET_COMPAREG_DEFAULT = 0
} |
| |
| enum | STIMER_STMINTSET_COMPAREF_Enum { STIMER_STMINTSET_COMPAREF_COMPARED = 1
, STIMER_STMINTSET_COMPAREF_DEFAULT = 0
} |
| |
| enum | STIMER_STMINTSET_COMPAREE_Enum { STIMER_STMINTSET_COMPAREE_COMPARED = 1
, STIMER_STMINTSET_COMPAREE_DEFAULT = 0
} |
| |
| enum | STIMER_STMINTSET_COMPARED_Enum { STIMER_STMINTSET_COMPARED_COMPARED = 1
, STIMER_STMINTSET_COMPARED_DEFAULT = 0
} |
| |
| enum | STIMER_STMINTSET_COMPAREC_Enum { STIMER_STMINTSET_COMPAREC_COMPARED = 1
, STIMER_STMINTSET_COMPAREC_DEFAULT = 0
} |
| |
| enum | STIMER_STMINTSET_COMPAREB_Enum { STIMER_STMINTSET_COMPAREB_COMPARED = 1
, STIMER_STMINTSET_COMPAREB_DEFAULT = 0
} |
| |
| enum | STIMER_STMINTSET_COMPAREA_Enum { STIMER_STMINTSET_COMPAREA_COMPARED = 1
, STIMER_STMINTSET_COMPAREA_DEFAULT = 0
} |
| |
| enum | TIMER_GLOBEN_ADCEN_Enum { TIMER_GLOBEN_ADCEN_EN = 1
, TIMER_GLOBEN_ADCEN_DIS = 0
} |
| |
| enum | TIMER_GLOBEN_AUDADCEN_Enum { TIMER_GLOBEN_AUDADCEN_EN = 1
, TIMER_GLOBEN_AUDADCEN_DIS = 0
} |
| |
| enum | TIMER_GLOBEN_ENABLEALLINPUTS_Enum { TIMER_GLOBEN_ENABLEALLINPUTS_EN = 1
, TIMER_GLOBEN_ENABLEALLINPUTS_DIS = 0
} |
| |
| enum | TIMER_GLOBEN_ENB15_Enum { TIMER_GLOBEN_ENB15_EN = 1
, TIMER_GLOBEN_ENB15_DIS = 0
} |
| |
| enum | TIMER_GLOBEN_ENB14_Enum { TIMER_GLOBEN_ENB14_EN = 1
, TIMER_GLOBEN_ENB14_DIS = 0
} |
| |
| enum | TIMER_GLOBEN_ENB13_Enum { TIMER_GLOBEN_ENB13_EN = 1
, TIMER_GLOBEN_ENB13_DIS = 0
} |
| |
| enum | TIMER_GLOBEN_ENB12_Enum { TIMER_GLOBEN_ENB12_EN = 1
, TIMER_GLOBEN_ENB12_DIS = 0
} |
| |
| enum | TIMER_GLOBEN_ENB11_Enum { TIMER_GLOBEN_ENB11_EN = 1
, TIMER_GLOBEN_ENB11_DIS = 0
} |
| |
| enum | TIMER_GLOBEN_ENB10_Enum { TIMER_GLOBEN_ENB10_EN = 1
, TIMER_GLOBEN_ENB10_DIS = 0
} |
| |
| enum | TIMER_GLOBEN_ENB9_Enum { TIMER_GLOBEN_ENB9_EN = 1
, TIMER_GLOBEN_ENB9_DIS = 0
} |
| |
| enum | TIMER_GLOBEN_ENB8_Enum { TIMER_GLOBEN_ENB8_EN = 1
, TIMER_GLOBEN_ENB8_DIS = 0
} |
| |
| enum | TIMER_GLOBEN_ENB7_Enum { TIMER_GLOBEN_ENB7_EN = 1
, TIMER_GLOBEN_ENB7_DIS = 0
} |
| |
| enum | TIMER_GLOBEN_ENB6_Enum { TIMER_GLOBEN_ENB6_EN = 1
, TIMER_GLOBEN_ENB6_DIS = 0
} |
| |
| enum | TIMER_GLOBEN_ENB5_Enum { TIMER_GLOBEN_ENB5_EN = 1
, TIMER_GLOBEN_ENB5_DIS = 0
} |
| |
| enum | TIMER_GLOBEN_ENB4_Enum { TIMER_GLOBEN_ENB4_EN = 1
, TIMER_GLOBEN_ENB4_DIS = 0
} |
| |
| enum | TIMER_GLOBEN_ENB3_Enum { TIMER_GLOBEN_ENB3_EN = 1
, TIMER_GLOBEN_ENB3_DIS = 0
} |
| |
| enum | TIMER_GLOBEN_ENB2_Enum { TIMER_GLOBEN_ENB2_EN = 1
, TIMER_GLOBEN_ENB2_DIS = 0
} |
| |
| enum | TIMER_GLOBEN_ENB1_Enum { TIMER_GLOBEN_ENB1_EN = 1
, TIMER_GLOBEN_ENB1_DIS = 0
} |
| |
| enum | TIMER_GLOBEN_ENB0_Enum { TIMER_GLOBEN_ENB0_EN = 1
, TIMER_GLOBEN_ENB0_DIS = 0
} |
| |
| enum | TIMER_OUTCFG0_OUTCFG3_Enum {
TIMER_OUTCFG0_OUTCFG3_TIMER00 = 0
, TIMER_OUTCFG0_OUTCFG3_TIMER01 = 1
, TIMER_OUTCFG0_OUTCFG3_TIMER10 = 2
, TIMER_OUTCFG0_OUTCFG3_TIMER11 = 3
,
TIMER_OUTCFG0_OUTCFG3_TIMER20 = 4
, TIMER_OUTCFG0_OUTCFG3_TIMER21 = 5
, TIMER_OUTCFG0_OUTCFG3_TIMER30 = 6
, TIMER_OUTCFG0_OUTCFG3_TIMER31 = 7
,
TIMER_OUTCFG0_OUTCFG3_TIMER40 = 8
, TIMER_OUTCFG0_OUTCFG3_TIMER41 = 9
, TIMER_OUTCFG0_OUTCFG3_TIMER50 = 10
, TIMER_OUTCFG0_OUTCFG3_TIMER51 = 11
,
TIMER_OUTCFG0_OUTCFG3_TIMER60 = 12
, TIMER_OUTCFG0_OUTCFG3_TIMER61 = 13
, TIMER_OUTCFG0_OUTCFG3_TIMER70 = 14
, TIMER_OUTCFG0_OUTCFG3_TIMER71 = 15
,
TIMER_OUTCFG0_OUTCFG3_TIMER80 = 16
, TIMER_OUTCFG0_OUTCFG3_TIMER81 = 17
, TIMER_OUTCFG0_OUTCFG3_TIMER90 = 18
, TIMER_OUTCFG0_OUTCFG3_TIMER91 = 19
,
TIMER_OUTCFG0_OUTCFG3_TIMER100 = 20
, TIMER_OUTCFG0_OUTCFG3_TIMER101 = 21
, TIMER_OUTCFG0_OUTCFG3_TIMER110 = 22
, TIMER_OUTCFG0_OUTCFG3_TIMER111 = 23
,
TIMER_OUTCFG0_OUTCFG3_TIMER120 = 24
, TIMER_OUTCFG0_OUTCFG3_TIMER121 = 25
, TIMER_OUTCFG0_OUTCFG3_TIMER130 = 26
, TIMER_OUTCFG0_OUTCFG3_TIMER131 = 27
,
TIMER_OUTCFG0_OUTCFG3_TIMER140 = 28
, TIMER_OUTCFG0_OUTCFG3_TIMER141 = 29
, TIMER_OUTCFG0_OUTCFG3_TIMER150 = 30
, TIMER_OUTCFG0_OUTCFG3_TIMER151 = 31
,
TIMER_OUTCFG0_OUTCFG3_STIMER0 = 32
, TIMER_OUTCFG0_OUTCFG3_STIMER1 = 33
, TIMER_OUTCFG0_OUTCFG3_STIMER2 = 34
, TIMER_OUTCFG0_OUTCFG3_STIMER3 = 35
,
TIMER_OUTCFG0_OUTCFG3_STIMER4 = 36
, TIMER_OUTCFG0_OUTCFG3_STIMER5 = 37
, TIMER_OUTCFG0_OUTCFG3_STIMER6 = 38
, TIMER_OUTCFG0_OUTCFG3_STIMER7 = 39
,
TIMER_OUTCFG0_OUTCFG3_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG0_OUTCFG2_Enum {
TIMER_OUTCFG0_OUTCFG2_TIMER00 = 0
, TIMER_OUTCFG0_OUTCFG2_TIMER01 = 1
, TIMER_OUTCFG0_OUTCFG2_TIMER10 = 2
, TIMER_OUTCFG0_OUTCFG2_TIMER11 = 3
,
TIMER_OUTCFG0_OUTCFG2_TIMER20 = 4
, TIMER_OUTCFG0_OUTCFG2_TIMER21 = 5
, TIMER_OUTCFG0_OUTCFG2_TIMER30 = 6
, TIMER_OUTCFG0_OUTCFG2_TIMER31 = 7
,
TIMER_OUTCFG0_OUTCFG2_TIMER40 = 8
, TIMER_OUTCFG0_OUTCFG2_TIMER41 = 9
, TIMER_OUTCFG0_OUTCFG2_TIMER50 = 10
, TIMER_OUTCFG0_OUTCFG2_TIMER51 = 11
,
TIMER_OUTCFG0_OUTCFG2_TIMER60 = 12
, TIMER_OUTCFG0_OUTCFG2_TIMER61 = 13
, TIMER_OUTCFG0_OUTCFG2_TIMER70 = 14
, TIMER_OUTCFG0_OUTCFG2_TIMER71 = 15
,
TIMER_OUTCFG0_OUTCFG2_TIMER80 = 16
, TIMER_OUTCFG0_OUTCFG2_TIMER81 = 17
, TIMER_OUTCFG0_OUTCFG2_TIMER90 = 18
, TIMER_OUTCFG0_OUTCFG2_TIMER91 = 19
,
TIMER_OUTCFG0_OUTCFG2_TIMER100 = 20
, TIMER_OUTCFG0_OUTCFG2_TIMER101 = 21
, TIMER_OUTCFG0_OUTCFG2_TIMER110 = 22
, TIMER_OUTCFG0_OUTCFG2_TIMER111 = 23
,
TIMER_OUTCFG0_OUTCFG2_TIMER120 = 24
, TIMER_OUTCFG0_OUTCFG2_TIMER121 = 25
, TIMER_OUTCFG0_OUTCFG2_TIMER130 = 26
, TIMER_OUTCFG0_OUTCFG2_TIMER131 = 27
,
TIMER_OUTCFG0_OUTCFG2_TIMER140 = 28
, TIMER_OUTCFG0_OUTCFG2_TIMER141 = 29
, TIMER_OUTCFG0_OUTCFG2_TIMER150 = 30
, TIMER_OUTCFG0_OUTCFG2_TIMER151 = 31
,
TIMER_OUTCFG0_OUTCFG2_STIMER0 = 32
, TIMER_OUTCFG0_OUTCFG2_STIMER1 = 33
, TIMER_OUTCFG0_OUTCFG2_STIMER2 = 34
, TIMER_OUTCFG0_OUTCFG2_STIMER3 = 35
,
TIMER_OUTCFG0_OUTCFG2_STIMER4 = 36
, TIMER_OUTCFG0_OUTCFG2_STIMER5 = 37
, TIMER_OUTCFG0_OUTCFG2_STIMER6 = 38
, TIMER_OUTCFG0_OUTCFG2_STIMER7 = 39
,
TIMER_OUTCFG0_OUTCFG2_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG0_OUTCFG1_Enum {
TIMER_OUTCFG0_OUTCFG1_TIMER00 = 0
, TIMER_OUTCFG0_OUTCFG1_TIMER01 = 1
, TIMER_OUTCFG0_OUTCFG1_TIMER10 = 2
, TIMER_OUTCFG0_OUTCFG1_TIMER11 = 3
,
TIMER_OUTCFG0_OUTCFG1_TIMER20 = 4
, TIMER_OUTCFG0_OUTCFG1_TIMER21 = 5
, TIMER_OUTCFG0_OUTCFG1_TIMER30 = 6
, TIMER_OUTCFG0_OUTCFG1_TIMER31 = 7
,
TIMER_OUTCFG0_OUTCFG1_TIMER40 = 8
, TIMER_OUTCFG0_OUTCFG1_TIMER41 = 9
, TIMER_OUTCFG0_OUTCFG1_TIMER50 = 10
, TIMER_OUTCFG0_OUTCFG1_TIMER51 = 11
,
TIMER_OUTCFG0_OUTCFG1_TIMER60 = 12
, TIMER_OUTCFG0_OUTCFG1_TIMER61 = 13
, TIMER_OUTCFG0_OUTCFG1_TIMER70 = 14
, TIMER_OUTCFG0_OUTCFG1_TIMER71 = 15
,
TIMER_OUTCFG0_OUTCFG1_TIMER80 = 16
, TIMER_OUTCFG0_OUTCFG1_TIMER81 = 17
, TIMER_OUTCFG0_OUTCFG1_TIMER90 = 18
, TIMER_OUTCFG0_OUTCFG1_TIMER91 = 19
,
TIMER_OUTCFG0_OUTCFG1_TIMER100 = 20
, TIMER_OUTCFG0_OUTCFG1_TIMER101 = 21
, TIMER_OUTCFG0_OUTCFG1_TIMER110 = 22
, TIMER_OUTCFG0_OUTCFG1_TIMER111 = 23
,
TIMER_OUTCFG0_OUTCFG1_TIMER120 = 24
, TIMER_OUTCFG0_OUTCFG1_TIMER121 = 25
, TIMER_OUTCFG0_OUTCFG1_TIMER130 = 26
, TIMER_OUTCFG0_OUTCFG1_TIMER131 = 27
,
TIMER_OUTCFG0_OUTCFG1_TIMER140 = 28
, TIMER_OUTCFG0_OUTCFG1_TIMER141 = 29
, TIMER_OUTCFG0_OUTCFG1_TIMER150 = 30
, TIMER_OUTCFG0_OUTCFG1_TIMER151 = 31
,
TIMER_OUTCFG0_OUTCFG1_STIMER0 = 32
, TIMER_OUTCFG0_OUTCFG1_STIMER1 = 33
, TIMER_OUTCFG0_OUTCFG1_STIMER2 = 34
, TIMER_OUTCFG0_OUTCFG1_STIMER3 = 35
,
TIMER_OUTCFG0_OUTCFG1_STIMER4 = 36
, TIMER_OUTCFG0_OUTCFG1_STIMER5 = 37
, TIMER_OUTCFG0_OUTCFG1_STIMER6 = 38
, TIMER_OUTCFG0_OUTCFG1_STIMER7 = 39
,
TIMER_OUTCFG0_OUTCFG1_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG0_OUTCFG0_Enum {
TIMER_OUTCFG0_OUTCFG0_TIMER00 = 0
, TIMER_OUTCFG0_OUTCFG0_TIMER01 = 1
, TIMER_OUTCFG0_OUTCFG0_TIMER10 = 2
, TIMER_OUTCFG0_OUTCFG0_TIMER11 = 3
,
TIMER_OUTCFG0_OUTCFG0_TIMER20 = 4
, TIMER_OUTCFG0_OUTCFG0_TIMER21 = 5
, TIMER_OUTCFG0_OUTCFG0_TIMER30 = 6
, TIMER_OUTCFG0_OUTCFG0_TIMER31 = 7
,
TIMER_OUTCFG0_OUTCFG0_TIMER40 = 8
, TIMER_OUTCFG0_OUTCFG0_TIMER41 = 9
, TIMER_OUTCFG0_OUTCFG0_TIMER50 = 10
, TIMER_OUTCFG0_OUTCFG0_TIMER51 = 11
,
TIMER_OUTCFG0_OUTCFG0_TIMER60 = 12
, TIMER_OUTCFG0_OUTCFG0_TIMER61 = 13
, TIMER_OUTCFG0_OUTCFG0_TIMER70 = 14
, TIMER_OUTCFG0_OUTCFG0_TIMER71 = 15
,
TIMER_OUTCFG0_OUTCFG0_TIMER80 = 16
, TIMER_OUTCFG0_OUTCFG0_TIMER81 = 17
, TIMER_OUTCFG0_OUTCFG0_TIMER90 = 18
, TIMER_OUTCFG0_OUTCFG0_TIMER91 = 19
,
TIMER_OUTCFG0_OUTCFG0_TIMER100 = 20
, TIMER_OUTCFG0_OUTCFG0_TIMER101 = 21
, TIMER_OUTCFG0_OUTCFG0_TIMER110 = 22
, TIMER_OUTCFG0_OUTCFG0_TIMER111 = 23
,
TIMER_OUTCFG0_OUTCFG0_TIMER120 = 24
, TIMER_OUTCFG0_OUTCFG0_TIMER121 = 25
, TIMER_OUTCFG0_OUTCFG0_TIMER130 = 26
, TIMER_OUTCFG0_OUTCFG0_TIMER131 = 27
,
TIMER_OUTCFG0_OUTCFG0_TIMER140 = 28
, TIMER_OUTCFG0_OUTCFG0_TIMER141 = 29
, TIMER_OUTCFG0_OUTCFG0_TIMER150 = 30
, TIMER_OUTCFG0_OUTCFG0_TIMER151 = 31
,
TIMER_OUTCFG0_OUTCFG0_STIMER0 = 32
, TIMER_OUTCFG0_OUTCFG0_STIMER1 = 33
, TIMER_OUTCFG0_OUTCFG0_STIMER2 = 34
, TIMER_OUTCFG0_OUTCFG0_STIMER3 = 35
,
TIMER_OUTCFG0_OUTCFG0_STIMER4 = 36
, TIMER_OUTCFG0_OUTCFG0_STIMER5 = 37
, TIMER_OUTCFG0_OUTCFG0_STIMER6 = 38
, TIMER_OUTCFG0_OUTCFG0_STIMER7 = 39
,
TIMER_OUTCFG0_OUTCFG0_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG1_OUTCFG7_Enum {
TIMER_OUTCFG1_OUTCFG7_TIMER00 = 0
, TIMER_OUTCFG1_OUTCFG7_TIMER01 = 1
, TIMER_OUTCFG1_OUTCFG7_TIMER10 = 2
, TIMER_OUTCFG1_OUTCFG7_TIMER11 = 3
,
TIMER_OUTCFG1_OUTCFG7_TIMER20 = 4
, TIMER_OUTCFG1_OUTCFG7_TIMER21 = 5
, TIMER_OUTCFG1_OUTCFG7_TIMER30 = 6
, TIMER_OUTCFG1_OUTCFG7_TIMER31 = 7
,
TIMER_OUTCFG1_OUTCFG7_TIMER40 = 8
, TIMER_OUTCFG1_OUTCFG7_TIMER41 = 9
, TIMER_OUTCFG1_OUTCFG7_TIMER50 = 10
, TIMER_OUTCFG1_OUTCFG7_TIMER51 = 11
,
TIMER_OUTCFG1_OUTCFG7_TIMER60 = 12
, TIMER_OUTCFG1_OUTCFG7_TIMER61 = 13
, TIMER_OUTCFG1_OUTCFG7_TIMER70 = 14
, TIMER_OUTCFG1_OUTCFG7_TIMER71 = 15
,
TIMER_OUTCFG1_OUTCFG7_TIMER80 = 16
, TIMER_OUTCFG1_OUTCFG7_TIMER81 = 17
, TIMER_OUTCFG1_OUTCFG7_TIMER90 = 18
, TIMER_OUTCFG1_OUTCFG7_TIMER91 = 19
,
TIMER_OUTCFG1_OUTCFG7_TIMER100 = 20
, TIMER_OUTCFG1_OUTCFG7_TIMER101 = 21
, TIMER_OUTCFG1_OUTCFG7_TIMER110 = 22
, TIMER_OUTCFG1_OUTCFG7_TIMER111 = 23
,
TIMER_OUTCFG1_OUTCFG7_TIMER120 = 24
, TIMER_OUTCFG1_OUTCFG7_TIMER121 = 25
, TIMER_OUTCFG1_OUTCFG7_TIMER130 = 26
, TIMER_OUTCFG1_OUTCFG7_TIMER131 = 27
,
TIMER_OUTCFG1_OUTCFG7_TIMER140 = 28
, TIMER_OUTCFG1_OUTCFG7_TIMER141 = 29
, TIMER_OUTCFG1_OUTCFG7_TIMER150 = 30
, TIMER_OUTCFG1_OUTCFG7_TIMER151 = 31
,
TIMER_OUTCFG1_OUTCFG7_STIMER0 = 32
, TIMER_OUTCFG1_OUTCFG7_STIMER1 = 33
, TIMER_OUTCFG1_OUTCFG7_STIMER2 = 34
, TIMER_OUTCFG1_OUTCFG7_STIMER3 = 35
,
TIMER_OUTCFG1_OUTCFG7_STIMER4 = 36
, TIMER_OUTCFG1_OUTCFG7_STIMER5 = 37
, TIMER_OUTCFG1_OUTCFG7_STIMER6 = 38
, TIMER_OUTCFG1_OUTCFG7_STIMER7 = 39
,
TIMER_OUTCFG1_OUTCFG7_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG1_OUTCFG6_Enum {
TIMER_OUTCFG1_OUTCFG6_TIMER00 = 0
, TIMER_OUTCFG1_OUTCFG6_TIMER01 = 1
, TIMER_OUTCFG1_OUTCFG6_TIMER10 = 2
, TIMER_OUTCFG1_OUTCFG6_TIMER11 = 3
,
TIMER_OUTCFG1_OUTCFG6_TIMER20 = 4
, TIMER_OUTCFG1_OUTCFG6_TIMER21 = 5
, TIMER_OUTCFG1_OUTCFG6_TIMER30 = 6
, TIMER_OUTCFG1_OUTCFG6_TIMER31 = 7
,
TIMER_OUTCFG1_OUTCFG6_TIMER40 = 8
, TIMER_OUTCFG1_OUTCFG6_TIMER41 = 9
, TIMER_OUTCFG1_OUTCFG6_TIMER50 = 10
, TIMER_OUTCFG1_OUTCFG6_TIMER51 = 11
,
TIMER_OUTCFG1_OUTCFG6_TIMER60 = 12
, TIMER_OUTCFG1_OUTCFG6_TIMER61 = 13
, TIMER_OUTCFG1_OUTCFG6_TIMER70 = 14
, TIMER_OUTCFG1_OUTCFG6_TIMER71 = 15
,
TIMER_OUTCFG1_OUTCFG6_TIMER80 = 16
, TIMER_OUTCFG1_OUTCFG6_TIMER81 = 17
, TIMER_OUTCFG1_OUTCFG6_TIMER90 = 18
, TIMER_OUTCFG1_OUTCFG6_TIMER91 = 19
,
TIMER_OUTCFG1_OUTCFG6_TIMER100 = 20
, TIMER_OUTCFG1_OUTCFG6_TIMER101 = 21
, TIMER_OUTCFG1_OUTCFG6_TIMER110 = 22
, TIMER_OUTCFG1_OUTCFG6_TIMER111 = 23
,
TIMER_OUTCFG1_OUTCFG6_TIMER120 = 24
, TIMER_OUTCFG1_OUTCFG6_TIMER121 = 25
, TIMER_OUTCFG1_OUTCFG6_TIMER130 = 26
, TIMER_OUTCFG1_OUTCFG6_TIMER131 = 27
,
TIMER_OUTCFG1_OUTCFG6_TIMER140 = 28
, TIMER_OUTCFG1_OUTCFG6_TIMER141 = 29
, TIMER_OUTCFG1_OUTCFG6_TIMER150 = 30
, TIMER_OUTCFG1_OUTCFG6_TIMER151 = 31
,
TIMER_OUTCFG1_OUTCFG6_STIMER0 = 32
, TIMER_OUTCFG1_OUTCFG6_STIMER1 = 33
, TIMER_OUTCFG1_OUTCFG6_STIMER2 = 34
, TIMER_OUTCFG1_OUTCFG6_STIMER3 = 35
,
TIMER_OUTCFG1_OUTCFG6_STIMER4 = 36
, TIMER_OUTCFG1_OUTCFG6_STIMER5 = 37
, TIMER_OUTCFG1_OUTCFG6_STIMER6 = 38
, TIMER_OUTCFG1_OUTCFG6_STIMER7 = 39
,
TIMER_OUTCFG1_OUTCFG6_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG1_OUTCFG5_Enum {
TIMER_OUTCFG1_OUTCFG5_TIMER00 = 0
, TIMER_OUTCFG1_OUTCFG5_TIMER01 = 1
, TIMER_OUTCFG1_OUTCFG5_TIMER10 = 2
, TIMER_OUTCFG1_OUTCFG5_TIMER11 = 3
,
TIMER_OUTCFG1_OUTCFG5_TIMER20 = 4
, TIMER_OUTCFG1_OUTCFG5_TIMER21 = 5
, TIMER_OUTCFG1_OUTCFG5_TIMER30 = 6
, TIMER_OUTCFG1_OUTCFG5_TIMER31 = 7
,
TIMER_OUTCFG1_OUTCFG5_TIMER40 = 8
, TIMER_OUTCFG1_OUTCFG5_TIMER41 = 9
, TIMER_OUTCFG1_OUTCFG5_TIMER50 = 10
, TIMER_OUTCFG1_OUTCFG5_TIMER51 = 11
,
TIMER_OUTCFG1_OUTCFG5_TIMER60 = 12
, TIMER_OUTCFG1_OUTCFG5_TIMER61 = 13
, TIMER_OUTCFG1_OUTCFG5_TIMER70 = 14
, TIMER_OUTCFG1_OUTCFG5_TIMER71 = 15
,
TIMER_OUTCFG1_OUTCFG5_TIMER80 = 16
, TIMER_OUTCFG1_OUTCFG5_TIMER81 = 17
, TIMER_OUTCFG1_OUTCFG5_TIMER90 = 18
, TIMER_OUTCFG1_OUTCFG5_TIMER91 = 19
,
TIMER_OUTCFG1_OUTCFG5_TIMER100 = 20
, TIMER_OUTCFG1_OUTCFG5_TIMER101 = 21
, TIMER_OUTCFG1_OUTCFG5_TIMER110 = 22
, TIMER_OUTCFG1_OUTCFG5_TIMER111 = 23
,
TIMER_OUTCFG1_OUTCFG5_TIMER120 = 24
, TIMER_OUTCFG1_OUTCFG5_TIMER121 = 25
, TIMER_OUTCFG1_OUTCFG5_TIMER130 = 26
, TIMER_OUTCFG1_OUTCFG5_TIMER131 = 27
,
TIMER_OUTCFG1_OUTCFG5_TIMER140 = 28
, TIMER_OUTCFG1_OUTCFG5_TIMER141 = 29
, TIMER_OUTCFG1_OUTCFG5_TIMER150 = 30
, TIMER_OUTCFG1_OUTCFG5_TIMER151 = 31
,
TIMER_OUTCFG1_OUTCFG5_STIMER0 = 32
, TIMER_OUTCFG1_OUTCFG5_STIMER1 = 33
, TIMER_OUTCFG1_OUTCFG5_STIMER2 = 34
, TIMER_OUTCFG1_OUTCFG5_STIMER3 = 35
,
TIMER_OUTCFG1_OUTCFG5_STIMER4 = 36
, TIMER_OUTCFG1_OUTCFG5_STIMER5 = 37
, TIMER_OUTCFG1_OUTCFG5_STIMER6 = 38
, TIMER_OUTCFG1_OUTCFG5_STIMER7 = 39
,
TIMER_OUTCFG1_OUTCFG5_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG1_OUTCFG4_Enum {
TIMER_OUTCFG1_OUTCFG4_TIMER00 = 0
, TIMER_OUTCFG1_OUTCFG4_TIMER01 = 1
, TIMER_OUTCFG1_OUTCFG4_TIMER10 = 2
, TIMER_OUTCFG1_OUTCFG4_TIMER11 = 3
,
TIMER_OUTCFG1_OUTCFG4_TIMER20 = 4
, TIMER_OUTCFG1_OUTCFG4_TIMER21 = 5
, TIMER_OUTCFG1_OUTCFG4_TIMER30 = 6
, TIMER_OUTCFG1_OUTCFG4_TIMER31 = 7
,
TIMER_OUTCFG1_OUTCFG4_TIMER40 = 8
, TIMER_OUTCFG1_OUTCFG4_TIMER41 = 9
, TIMER_OUTCFG1_OUTCFG4_TIMER50 = 10
, TIMER_OUTCFG1_OUTCFG4_TIMER51 = 11
,
TIMER_OUTCFG1_OUTCFG4_TIMER60 = 12
, TIMER_OUTCFG1_OUTCFG4_TIMER61 = 13
, TIMER_OUTCFG1_OUTCFG4_TIMER70 = 14
, TIMER_OUTCFG1_OUTCFG4_TIMER71 = 15
,
TIMER_OUTCFG1_OUTCFG4_TIMER80 = 16
, TIMER_OUTCFG1_OUTCFG4_TIMER81 = 17
, TIMER_OUTCFG1_OUTCFG4_TIMER90 = 18
, TIMER_OUTCFG1_OUTCFG4_TIMER91 = 19
,
TIMER_OUTCFG1_OUTCFG4_TIMER100 = 20
, TIMER_OUTCFG1_OUTCFG4_TIMER101 = 21
, TIMER_OUTCFG1_OUTCFG4_TIMER110 = 22
, TIMER_OUTCFG1_OUTCFG4_TIMER111 = 23
,
TIMER_OUTCFG1_OUTCFG4_TIMER120 = 24
, TIMER_OUTCFG1_OUTCFG4_TIMER121 = 25
, TIMER_OUTCFG1_OUTCFG4_TIMER130 = 26
, TIMER_OUTCFG1_OUTCFG4_TIMER131 = 27
,
TIMER_OUTCFG1_OUTCFG4_TIMER140 = 28
, TIMER_OUTCFG1_OUTCFG4_TIMER141 = 29
, TIMER_OUTCFG1_OUTCFG4_TIMER150 = 30
, TIMER_OUTCFG1_OUTCFG4_TIMER151 = 31
,
TIMER_OUTCFG1_OUTCFG4_STIMER0 = 32
, TIMER_OUTCFG1_OUTCFG4_STIMER1 = 33
, TIMER_OUTCFG1_OUTCFG4_STIMER2 = 34
, TIMER_OUTCFG1_OUTCFG4_STIMER3 = 35
,
TIMER_OUTCFG1_OUTCFG4_STIMER4 = 36
, TIMER_OUTCFG1_OUTCFG4_STIMER5 = 37
, TIMER_OUTCFG1_OUTCFG4_STIMER6 = 38
, TIMER_OUTCFG1_OUTCFG4_STIMER7 = 39
,
TIMER_OUTCFG1_OUTCFG4_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG2_OUTCFG11_Enum {
TIMER_OUTCFG2_OUTCFG11_TIMER00 = 0
, TIMER_OUTCFG2_OUTCFG11_TIMER01 = 1
, TIMER_OUTCFG2_OUTCFG11_TIMER10 = 2
, TIMER_OUTCFG2_OUTCFG11_TIMER11 = 3
,
TIMER_OUTCFG2_OUTCFG11_TIMER20 = 4
, TIMER_OUTCFG2_OUTCFG11_TIMER21 = 5
, TIMER_OUTCFG2_OUTCFG11_TIMER30 = 6
, TIMER_OUTCFG2_OUTCFG11_TIMER31 = 7
,
TIMER_OUTCFG2_OUTCFG11_TIMER40 = 8
, TIMER_OUTCFG2_OUTCFG11_TIMER41 = 9
, TIMER_OUTCFG2_OUTCFG11_TIMER50 = 10
, TIMER_OUTCFG2_OUTCFG11_TIMER51 = 11
,
TIMER_OUTCFG2_OUTCFG11_TIMER60 = 12
, TIMER_OUTCFG2_OUTCFG11_TIMER61 = 13
, TIMER_OUTCFG2_OUTCFG11_TIMER70 = 14
, TIMER_OUTCFG2_OUTCFG11_TIMER71 = 15
,
TIMER_OUTCFG2_OUTCFG11_TIMER80 = 16
, TIMER_OUTCFG2_OUTCFG11_TIMER81 = 17
, TIMER_OUTCFG2_OUTCFG11_TIMER90 = 18
, TIMER_OUTCFG2_OUTCFG11_TIMER91 = 19
,
TIMER_OUTCFG2_OUTCFG11_TIMER100 = 20
, TIMER_OUTCFG2_OUTCFG11_TIMER101 = 21
, TIMER_OUTCFG2_OUTCFG11_TIMER110 = 22
, TIMER_OUTCFG2_OUTCFG11_TIMER111 = 23
,
TIMER_OUTCFG2_OUTCFG11_TIMER120 = 24
, TIMER_OUTCFG2_OUTCFG11_TIMER121 = 25
, TIMER_OUTCFG2_OUTCFG11_TIMER130 = 26
, TIMER_OUTCFG2_OUTCFG11_TIMER131 = 27
,
TIMER_OUTCFG2_OUTCFG11_TIMER140 = 28
, TIMER_OUTCFG2_OUTCFG11_TIMER141 = 29
, TIMER_OUTCFG2_OUTCFG11_TIMER150 = 30
, TIMER_OUTCFG2_OUTCFG11_TIMER151 = 31
,
TIMER_OUTCFG2_OUTCFG11_STIMER0 = 32
, TIMER_OUTCFG2_OUTCFG11_STIMER1 = 33
, TIMER_OUTCFG2_OUTCFG11_STIMER2 = 34
, TIMER_OUTCFG2_OUTCFG11_STIMER3 = 35
,
TIMER_OUTCFG2_OUTCFG11_STIMER4 = 36
, TIMER_OUTCFG2_OUTCFG11_STIMER5 = 37
, TIMER_OUTCFG2_OUTCFG11_STIMER6 = 38
, TIMER_OUTCFG2_OUTCFG11_STIMER7 = 39
,
TIMER_OUTCFG2_OUTCFG11_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG2_OUTCFG10_Enum {
TIMER_OUTCFG2_OUTCFG10_TIMER00 = 0
, TIMER_OUTCFG2_OUTCFG10_TIMER01 = 1
, TIMER_OUTCFG2_OUTCFG10_TIMER10 = 2
, TIMER_OUTCFG2_OUTCFG10_TIMER11 = 3
,
TIMER_OUTCFG2_OUTCFG10_TIMER20 = 4
, TIMER_OUTCFG2_OUTCFG10_TIMER21 = 5
, TIMER_OUTCFG2_OUTCFG10_TIMER30 = 6
, TIMER_OUTCFG2_OUTCFG10_TIMER31 = 7
,
TIMER_OUTCFG2_OUTCFG10_TIMER40 = 8
, TIMER_OUTCFG2_OUTCFG10_TIMER41 = 9
, TIMER_OUTCFG2_OUTCFG10_TIMER50 = 10
, TIMER_OUTCFG2_OUTCFG10_TIMER51 = 11
,
TIMER_OUTCFG2_OUTCFG10_TIMER60 = 12
, TIMER_OUTCFG2_OUTCFG10_TIMER61 = 13
, TIMER_OUTCFG2_OUTCFG10_TIMER70 = 14
, TIMER_OUTCFG2_OUTCFG10_TIMER71 = 15
,
TIMER_OUTCFG2_OUTCFG10_TIMER80 = 16
, TIMER_OUTCFG2_OUTCFG10_TIMER81 = 17
, TIMER_OUTCFG2_OUTCFG10_TIMER90 = 18
, TIMER_OUTCFG2_OUTCFG10_TIMER91 = 19
,
TIMER_OUTCFG2_OUTCFG10_TIMER100 = 20
, TIMER_OUTCFG2_OUTCFG10_TIMER101 = 21
, TIMER_OUTCFG2_OUTCFG10_TIMER110 = 22
, TIMER_OUTCFG2_OUTCFG10_TIMER111 = 23
,
TIMER_OUTCFG2_OUTCFG10_TIMER120 = 24
, TIMER_OUTCFG2_OUTCFG10_TIMER121 = 25
, TIMER_OUTCFG2_OUTCFG10_TIMER130 = 26
, TIMER_OUTCFG2_OUTCFG10_TIMER131 = 27
,
TIMER_OUTCFG2_OUTCFG10_TIMER140 = 28
, TIMER_OUTCFG2_OUTCFG10_TIMER141 = 29
, TIMER_OUTCFG2_OUTCFG10_TIMER150 = 30
, TIMER_OUTCFG2_OUTCFG10_TIMER151 = 31
,
TIMER_OUTCFG2_OUTCFG10_STIMER0 = 32
, TIMER_OUTCFG2_OUTCFG10_STIMER1 = 33
, TIMER_OUTCFG2_OUTCFG10_STIMER2 = 34
, TIMER_OUTCFG2_OUTCFG10_STIMER3 = 35
,
TIMER_OUTCFG2_OUTCFG10_STIMER4 = 36
, TIMER_OUTCFG2_OUTCFG10_STIMER5 = 37
, TIMER_OUTCFG2_OUTCFG10_STIMER6 = 38
, TIMER_OUTCFG2_OUTCFG10_STIMER7 = 39
,
TIMER_OUTCFG2_OUTCFG10_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG2_OUTCFG9_Enum {
TIMER_OUTCFG2_OUTCFG9_TIMER00 = 0
, TIMER_OUTCFG2_OUTCFG9_TIMER01 = 1
, TIMER_OUTCFG2_OUTCFG9_TIMER10 = 2
, TIMER_OUTCFG2_OUTCFG9_TIMER11 = 3
,
TIMER_OUTCFG2_OUTCFG9_TIMER20 = 4
, TIMER_OUTCFG2_OUTCFG9_TIMER21 = 5
, TIMER_OUTCFG2_OUTCFG9_TIMER30 = 6
, TIMER_OUTCFG2_OUTCFG9_TIMER31 = 7
,
TIMER_OUTCFG2_OUTCFG9_TIMER40 = 8
, TIMER_OUTCFG2_OUTCFG9_TIMER41 = 9
, TIMER_OUTCFG2_OUTCFG9_TIMER50 = 10
, TIMER_OUTCFG2_OUTCFG9_TIMER51 = 11
,
TIMER_OUTCFG2_OUTCFG9_TIMER60 = 12
, TIMER_OUTCFG2_OUTCFG9_TIMER61 = 13
, TIMER_OUTCFG2_OUTCFG9_TIMER70 = 14
, TIMER_OUTCFG2_OUTCFG9_TIMER71 = 15
,
TIMER_OUTCFG2_OUTCFG9_TIMER80 = 16
, TIMER_OUTCFG2_OUTCFG9_TIMER81 = 17
, TIMER_OUTCFG2_OUTCFG9_TIMER90 = 18
, TIMER_OUTCFG2_OUTCFG9_TIMER91 = 19
,
TIMER_OUTCFG2_OUTCFG9_TIMER100 = 20
, TIMER_OUTCFG2_OUTCFG9_TIMER101 = 21
, TIMER_OUTCFG2_OUTCFG9_TIMER110 = 22
, TIMER_OUTCFG2_OUTCFG9_TIMER111 = 23
,
TIMER_OUTCFG2_OUTCFG9_TIMER120 = 24
, TIMER_OUTCFG2_OUTCFG9_TIMER121 = 25
, TIMER_OUTCFG2_OUTCFG9_TIMER130 = 26
, TIMER_OUTCFG2_OUTCFG9_TIMER131 = 27
,
TIMER_OUTCFG2_OUTCFG9_TIMER140 = 28
, TIMER_OUTCFG2_OUTCFG9_TIMER141 = 29
, TIMER_OUTCFG2_OUTCFG9_TIMER150 = 30
, TIMER_OUTCFG2_OUTCFG9_TIMER151 = 31
,
TIMER_OUTCFG2_OUTCFG9_STIMER0 = 32
, TIMER_OUTCFG2_OUTCFG9_STIMER1 = 33
, TIMER_OUTCFG2_OUTCFG9_STIMER2 = 34
, TIMER_OUTCFG2_OUTCFG9_STIMER3 = 35
,
TIMER_OUTCFG2_OUTCFG9_STIMER4 = 36
, TIMER_OUTCFG2_OUTCFG9_STIMER5 = 37
, TIMER_OUTCFG2_OUTCFG9_STIMER6 = 38
, TIMER_OUTCFG2_OUTCFG9_STIMER7 = 39
,
TIMER_OUTCFG2_OUTCFG9_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG2_OUTCFG8_Enum {
TIMER_OUTCFG2_OUTCFG8_TIMER00 = 0
, TIMER_OUTCFG2_OUTCFG8_TIMER01 = 1
, TIMER_OUTCFG2_OUTCFG8_TIMER10 = 2
, TIMER_OUTCFG2_OUTCFG8_TIMER11 = 3
,
TIMER_OUTCFG2_OUTCFG8_TIMER20 = 4
, TIMER_OUTCFG2_OUTCFG8_TIMER21 = 5
, TIMER_OUTCFG2_OUTCFG8_TIMER30 = 6
, TIMER_OUTCFG2_OUTCFG8_TIMER31 = 7
,
TIMER_OUTCFG2_OUTCFG8_TIMER40 = 8
, TIMER_OUTCFG2_OUTCFG8_TIMER41 = 9
, TIMER_OUTCFG2_OUTCFG8_TIMER50 = 10
, TIMER_OUTCFG2_OUTCFG8_TIMER51 = 11
,
TIMER_OUTCFG2_OUTCFG8_TIMER60 = 12
, TIMER_OUTCFG2_OUTCFG8_TIMER61 = 13
, TIMER_OUTCFG2_OUTCFG8_TIMER70 = 14
, TIMER_OUTCFG2_OUTCFG8_TIMER71 = 15
,
TIMER_OUTCFG2_OUTCFG8_TIMER80 = 16
, TIMER_OUTCFG2_OUTCFG8_TIMER81 = 17
, TIMER_OUTCFG2_OUTCFG8_TIMER90 = 18
, TIMER_OUTCFG2_OUTCFG8_TIMER91 = 19
,
TIMER_OUTCFG2_OUTCFG8_TIMER100 = 20
, TIMER_OUTCFG2_OUTCFG8_TIMER101 = 21
, TIMER_OUTCFG2_OUTCFG8_TIMER110 = 22
, TIMER_OUTCFG2_OUTCFG8_TIMER111 = 23
,
TIMER_OUTCFG2_OUTCFG8_TIMER120 = 24
, TIMER_OUTCFG2_OUTCFG8_TIMER121 = 25
, TIMER_OUTCFG2_OUTCFG8_TIMER130 = 26
, TIMER_OUTCFG2_OUTCFG8_TIMER131 = 27
,
TIMER_OUTCFG2_OUTCFG8_TIMER140 = 28
, TIMER_OUTCFG2_OUTCFG8_TIMER141 = 29
, TIMER_OUTCFG2_OUTCFG8_TIMER150 = 30
, TIMER_OUTCFG2_OUTCFG8_TIMER151 = 31
,
TIMER_OUTCFG2_OUTCFG8_STIMER0 = 32
, TIMER_OUTCFG2_OUTCFG8_STIMER1 = 33
, TIMER_OUTCFG2_OUTCFG8_STIMER2 = 34
, TIMER_OUTCFG2_OUTCFG8_STIMER3 = 35
,
TIMER_OUTCFG2_OUTCFG8_STIMER4 = 36
, TIMER_OUTCFG2_OUTCFG8_STIMER5 = 37
, TIMER_OUTCFG2_OUTCFG8_STIMER6 = 38
, TIMER_OUTCFG2_OUTCFG8_STIMER7 = 39
,
TIMER_OUTCFG2_OUTCFG8_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG3_OUTCFG15_Enum {
TIMER_OUTCFG3_OUTCFG15_TIMER00 = 0
, TIMER_OUTCFG3_OUTCFG15_TIMER01 = 1
, TIMER_OUTCFG3_OUTCFG15_TIMER10 = 2
, TIMER_OUTCFG3_OUTCFG15_TIMER11 = 3
,
TIMER_OUTCFG3_OUTCFG15_TIMER20 = 4
, TIMER_OUTCFG3_OUTCFG15_TIMER21 = 5
, TIMER_OUTCFG3_OUTCFG15_TIMER30 = 6
, TIMER_OUTCFG3_OUTCFG15_TIMER31 = 7
,
TIMER_OUTCFG3_OUTCFG15_TIMER40 = 8
, TIMER_OUTCFG3_OUTCFG15_TIMER41 = 9
, TIMER_OUTCFG3_OUTCFG15_TIMER50 = 10
, TIMER_OUTCFG3_OUTCFG15_TIMER51 = 11
,
TIMER_OUTCFG3_OUTCFG15_TIMER60 = 12
, TIMER_OUTCFG3_OUTCFG15_TIMER61 = 13
, TIMER_OUTCFG3_OUTCFG15_TIMER70 = 14
, TIMER_OUTCFG3_OUTCFG15_TIMER71 = 15
,
TIMER_OUTCFG3_OUTCFG15_TIMER80 = 16
, TIMER_OUTCFG3_OUTCFG15_TIMER81 = 17
, TIMER_OUTCFG3_OUTCFG15_TIMER90 = 18
, TIMER_OUTCFG3_OUTCFG15_TIMER91 = 19
,
TIMER_OUTCFG3_OUTCFG15_TIMER100 = 20
, TIMER_OUTCFG3_OUTCFG15_TIMER101 = 21
, TIMER_OUTCFG3_OUTCFG15_TIMER110 = 22
, TIMER_OUTCFG3_OUTCFG15_TIMER111 = 23
,
TIMER_OUTCFG3_OUTCFG15_TIMER120 = 24
, TIMER_OUTCFG3_OUTCFG15_TIMER121 = 25
, TIMER_OUTCFG3_OUTCFG15_TIMER130 = 26
, TIMER_OUTCFG3_OUTCFG15_TIMER131 = 27
,
TIMER_OUTCFG3_OUTCFG15_TIMER140 = 28
, TIMER_OUTCFG3_OUTCFG15_TIMER141 = 29
, TIMER_OUTCFG3_OUTCFG15_TIMER150 = 30
, TIMER_OUTCFG3_OUTCFG15_TIMER151 = 31
,
TIMER_OUTCFG3_OUTCFG15_STIMER0 = 32
, TIMER_OUTCFG3_OUTCFG15_STIMER1 = 33
, TIMER_OUTCFG3_OUTCFG15_STIMER2 = 34
, TIMER_OUTCFG3_OUTCFG15_STIMER3 = 35
,
TIMER_OUTCFG3_OUTCFG15_STIMER4 = 36
, TIMER_OUTCFG3_OUTCFG15_STIMER5 = 37
, TIMER_OUTCFG3_OUTCFG15_STIMER6 = 38
, TIMER_OUTCFG3_OUTCFG15_STIMER7 = 39
,
TIMER_OUTCFG3_OUTCFG15_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG3_OUTCFG14_Enum {
TIMER_OUTCFG3_OUTCFG14_TIMER00 = 0
, TIMER_OUTCFG3_OUTCFG14_TIMER01 = 1
, TIMER_OUTCFG3_OUTCFG14_TIMER10 = 2
, TIMER_OUTCFG3_OUTCFG14_TIMER11 = 3
,
TIMER_OUTCFG3_OUTCFG14_TIMER20 = 4
, TIMER_OUTCFG3_OUTCFG14_TIMER21 = 5
, TIMER_OUTCFG3_OUTCFG14_TIMER30 = 6
, TIMER_OUTCFG3_OUTCFG14_TIMER31 = 7
,
TIMER_OUTCFG3_OUTCFG14_TIMER40 = 8
, TIMER_OUTCFG3_OUTCFG14_TIMER41 = 9
, TIMER_OUTCFG3_OUTCFG14_TIMER50 = 10
, TIMER_OUTCFG3_OUTCFG14_TIMER51 = 11
,
TIMER_OUTCFG3_OUTCFG14_TIMER60 = 12
, TIMER_OUTCFG3_OUTCFG14_TIMER61 = 13
, TIMER_OUTCFG3_OUTCFG14_TIMER70 = 14
, TIMER_OUTCFG3_OUTCFG14_TIMER71 = 15
,
TIMER_OUTCFG3_OUTCFG14_TIMER80 = 16
, TIMER_OUTCFG3_OUTCFG14_TIMER81 = 17
, TIMER_OUTCFG3_OUTCFG14_TIMER90 = 18
, TIMER_OUTCFG3_OUTCFG14_TIMER91 = 19
,
TIMER_OUTCFG3_OUTCFG14_TIMER100 = 20
, TIMER_OUTCFG3_OUTCFG14_TIMER101 = 21
, TIMER_OUTCFG3_OUTCFG14_TIMER110 = 22
, TIMER_OUTCFG3_OUTCFG14_TIMER111 = 23
,
TIMER_OUTCFG3_OUTCFG14_TIMER120 = 24
, TIMER_OUTCFG3_OUTCFG14_TIMER121 = 25
, TIMER_OUTCFG3_OUTCFG14_TIMER130 = 26
, TIMER_OUTCFG3_OUTCFG14_TIMER131 = 27
,
TIMER_OUTCFG3_OUTCFG14_TIMER140 = 28
, TIMER_OUTCFG3_OUTCFG14_TIMER141 = 29
, TIMER_OUTCFG3_OUTCFG14_TIMER150 = 30
, TIMER_OUTCFG3_OUTCFG14_TIMER151 = 31
,
TIMER_OUTCFG3_OUTCFG14_STIMER0 = 32
, TIMER_OUTCFG3_OUTCFG14_STIMER1 = 33
, TIMER_OUTCFG3_OUTCFG14_STIMER2 = 34
, TIMER_OUTCFG3_OUTCFG14_STIMER3 = 35
,
TIMER_OUTCFG3_OUTCFG14_STIMER4 = 36
, TIMER_OUTCFG3_OUTCFG14_STIMER5 = 37
, TIMER_OUTCFG3_OUTCFG14_STIMER6 = 38
, TIMER_OUTCFG3_OUTCFG14_STIMER7 = 39
,
TIMER_OUTCFG3_OUTCFG14_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG3_OUTCFG13_Enum {
TIMER_OUTCFG3_OUTCFG13_TIMER00 = 0
, TIMER_OUTCFG3_OUTCFG13_TIMER01 = 1
, TIMER_OUTCFG3_OUTCFG13_TIMER10 = 2
, TIMER_OUTCFG3_OUTCFG13_TIMER11 = 3
,
TIMER_OUTCFG3_OUTCFG13_TIMER20 = 4
, TIMER_OUTCFG3_OUTCFG13_TIMER21 = 5
, TIMER_OUTCFG3_OUTCFG13_TIMER30 = 6
, TIMER_OUTCFG3_OUTCFG13_TIMER31 = 7
,
TIMER_OUTCFG3_OUTCFG13_TIMER40 = 8
, TIMER_OUTCFG3_OUTCFG13_TIMER41 = 9
, TIMER_OUTCFG3_OUTCFG13_TIMER50 = 10
, TIMER_OUTCFG3_OUTCFG13_TIMER51 = 11
,
TIMER_OUTCFG3_OUTCFG13_TIMER60 = 12
, TIMER_OUTCFG3_OUTCFG13_TIMER61 = 13
, TIMER_OUTCFG3_OUTCFG13_TIMER70 = 14
, TIMER_OUTCFG3_OUTCFG13_TIMER71 = 15
,
TIMER_OUTCFG3_OUTCFG13_TIMER80 = 16
, TIMER_OUTCFG3_OUTCFG13_TIMER81 = 17
, TIMER_OUTCFG3_OUTCFG13_TIMER90 = 18
, TIMER_OUTCFG3_OUTCFG13_TIMER91 = 19
,
TIMER_OUTCFG3_OUTCFG13_TIMER100 = 20
, TIMER_OUTCFG3_OUTCFG13_TIMER101 = 21
, TIMER_OUTCFG3_OUTCFG13_TIMER110 = 22
, TIMER_OUTCFG3_OUTCFG13_TIMER111 = 23
,
TIMER_OUTCFG3_OUTCFG13_TIMER120 = 24
, TIMER_OUTCFG3_OUTCFG13_TIMER121 = 25
, TIMER_OUTCFG3_OUTCFG13_TIMER130 = 26
, TIMER_OUTCFG3_OUTCFG13_TIMER131 = 27
,
TIMER_OUTCFG3_OUTCFG13_TIMER140 = 28
, TIMER_OUTCFG3_OUTCFG13_TIMER141 = 29
, TIMER_OUTCFG3_OUTCFG13_TIMER150 = 30
, TIMER_OUTCFG3_OUTCFG13_TIMER151 = 31
,
TIMER_OUTCFG3_OUTCFG13_STIMER0 = 32
, TIMER_OUTCFG3_OUTCFG13_STIMER1 = 33
, TIMER_OUTCFG3_OUTCFG13_STIMER2 = 34
, TIMER_OUTCFG3_OUTCFG13_STIMER3 = 35
,
TIMER_OUTCFG3_OUTCFG13_STIMER4 = 36
, TIMER_OUTCFG3_OUTCFG13_STIMER5 = 37
, TIMER_OUTCFG3_OUTCFG13_STIMER6 = 38
, TIMER_OUTCFG3_OUTCFG13_STIMER7 = 39
,
TIMER_OUTCFG3_OUTCFG13_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG3_OUTCFG12_Enum {
TIMER_OUTCFG3_OUTCFG12_TIMER00 = 0
, TIMER_OUTCFG3_OUTCFG12_TIMER01 = 1
, TIMER_OUTCFG3_OUTCFG12_TIMER10 = 2
, TIMER_OUTCFG3_OUTCFG12_TIMER11 = 3
,
TIMER_OUTCFG3_OUTCFG12_TIMER20 = 4
, TIMER_OUTCFG3_OUTCFG12_TIMER21 = 5
, TIMER_OUTCFG3_OUTCFG12_TIMER30 = 6
, TIMER_OUTCFG3_OUTCFG12_TIMER31 = 7
,
TIMER_OUTCFG3_OUTCFG12_TIMER40 = 8
, TIMER_OUTCFG3_OUTCFG12_TIMER41 = 9
, TIMER_OUTCFG3_OUTCFG12_TIMER50 = 10
, TIMER_OUTCFG3_OUTCFG12_TIMER51 = 11
,
TIMER_OUTCFG3_OUTCFG12_TIMER60 = 12
, TIMER_OUTCFG3_OUTCFG12_TIMER61 = 13
, TIMER_OUTCFG3_OUTCFG12_TIMER70 = 14
, TIMER_OUTCFG3_OUTCFG12_TIMER71 = 15
,
TIMER_OUTCFG3_OUTCFG12_TIMER80 = 16
, TIMER_OUTCFG3_OUTCFG12_TIMER81 = 17
, TIMER_OUTCFG3_OUTCFG12_TIMER90 = 18
, TIMER_OUTCFG3_OUTCFG12_TIMER91 = 19
,
TIMER_OUTCFG3_OUTCFG12_TIMER100 = 20
, TIMER_OUTCFG3_OUTCFG12_TIMER101 = 21
, TIMER_OUTCFG3_OUTCFG12_TIMER110 = 22
, TIMER_OUTCFG3_OUTCFG12_TIMER111 = 23
,
TIMER_OUTCFG3_OUTCFG12_TIMER120 = 24
, TIMER_OUTCFG3_OUTCFG12_TIMER121 = 25
, TIMER_OUTCFG3_OUTCFG12_TIMER130 = 26
, TIMER_OUTCFG3_OUTCFG12_TIMER131 = 27
,
TIMER_OUTCFG3_OUTCFG12_TIMER140 = 28
, TIMER_OUTCFG3_OUTCFG12_TIMER141 = 29
, TIMER_OUTCFG3_OUTCFG12_TIMER150 = 30
, TIMER_OUTCFG3_OUTCFG12_TIMER151 = 31
,
TIMER_OUTCFG3_OUTCFG12_STIMER0 = 32
, TIMER_OUTCFG3_OUTCFG12_STIMER1 = 33
, TIMER_OUTCFG3_OUTCFG12_STIMER2 = 34
, TIMER_OUTCFG3_OUTCFG12_STIMER3 = 35
,
TIMER_OUTCFG3_OUTCFG12_STIMER4 = 36
, TIMER_OUTCFG3_OUTCFG12_STIMER5 = 37
, TIMER_OUTCFG3_OUTCFG12_STIMER6 = 38
, TIMER_OUTCFG3_OUTCFG12_STIMER7 = 39
,
TIMER_OUTCFG3_OUTCFG12_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG4_OUTCFG19_Enum {
TIMER_OUTCFG4_OUTCFG19_TIMER00 = 0
, TIMER_OUTCFG4_OUTCFG19_TIMER01 = 1
, TIMER_OUTCFG4_OUTCFG19_TIMER10 = 2
, TIMER_OUTCFG4_OUTCFG19_TIMER11 = 3
,
TIMER_OUTCFG4_OUTCFG19_TIMER20 = 4
, TIMER_OUTCFG4_OUTCFG19_TIMER21 = 5
, TIMER_OUTCFG4_OUTCFG19_TIMER30 = 6
, TIMER_OUTCFG4_OUTCFG19_TIMER31 = 7
,
TIMER_OUTCFG4_OUTCFG19_TIMER40 = 8
, TIMER_OUTCFG4_OUTCFG19_TIMER41 = 9
, TIMER_OUTCFG4_OUTCFG19_TIMER50 = 10
, TIMER_OUTCFG4_OUTCFG19_TIMER51 = 11
,
TIMER_OUTCFG4_OUTCFG19_TIMER60 = 12
, TIMER_OUTCFG4_OUTCFG19_TIMER61 = 13
, TIMER_OUTCFG4_OUTCFG19_TIMER70 = 14
, TIMER_OUTCFG4_OUTCFG19_TIMER71 = 15
,
TIMER_OUTCFG4_OUTCFG19_TIMER80 = 16
, TIMER_OUTCFG4_OUTCFG19_TIMER81 = 17
, TIMER_OUTCFG4_OUTCFG19_TIMER90 = 18
, TIMER_OUTCFG4_OUTCFG19_TIMER91 = 19
,
TIMER_OUTCFG4_OUTCFG19_TIMER100 = 20
, TIMER_OUTCFG4_OUTCFG19_TIMER101 = 21
, TIMER_OUTCFG4_OUTCFG19_TIMER110 = 22
, TIMER_OUTCFG4_OUTCFG19_TIMER111 = 23
,
TIMER_OUTCFG4_OUTCFG19_TIMER120 = 24
, TIMER_OUTCFG4_OUTCFG19_TIMER121 = 25
, TIMER_OUTCFG4_OUTCFG19_TIMER130 = 26
, TIMER_OUTCFG4_OUTCFG19_TIMER131 = 27
,
TIMER_OUTCFG4_OUTCFG19_TIMER140 = 28
, TIMER_OUTCFG4_OUTCFG19_TIMER141 = 29
, TIMER_OUTCFG4_OUTCFG19_TIMER150 = 30
, TIMER_OUTCFG4_OUTCFG19_TIMER151 = 31
,
TIMER_OUTCFG4_OUTCFG19_STIMER0 = 32
, TIMER_OUTCFG4_OUTCFG19_STIMER1 = 33
, TIMER_OUTCFG4_OUTCFG19_STIMER2 = 34
, TIMER_OUTCFG4_OUTCFG19_STIMER3 = 35
,
TIMER_OUTCFG4_OUTCFG19_STIMER4 = 36
, TIMER_OUTCFG4_OUTCFG19_STIMER5 = 37
, TIMER_OUTCFG4_OUTCFG19_STIMER6 = 38
, TIMER_OUTCFG4_OUTCFG19_STIMER7 = 39
,
TIMER_OUTCFG4_OUTCFG19_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG4_OUTCFG18_Enum {
TIMER_OUTCFG4_OUTCFG18_TIMER00 = 0
, TIMER_OUTCFG4_OUTCFG18_TIMER01 = 1
, TIMER_OUTCFG4_OUTCFG18_TIMER10 = 2
, TIMER_OUTCFG4_OUTCFG18_TIMER11 = 3
,
TIMER_OUTCFG4_OUTCFG18_TIMER20 = 4
, TIMER_OUTCFG4_OUTCFG18_TIMER21 = 5
, TIMER_OUTCFG4_OUTCFG18_TIMER30 = 6
, TIMER_OUTCFG4_OUTCFG18_TIMER31 = 7
,
TIMER_OUTCFG4_OUTCFG18_TIMER40 = 8
, TIMER_OUTCFG4_OUTCFG18_TIMER41 = 9
, TIMER_OUTCFG4_OUTCFG18_TIMER50 = 10
, TIMER_OUTCFG4_OUTCFG18_TIMER51 = 11
,
TIMER_OUTCFG4_OUTCFG18_TIMER60 = 12
, TIMER_OUTCFG4_OUTCFG18_TIMER61 = 13
, TIMER_OUTCFG4_OUTCFG18_TIMER70 = 14
, TIMER_OUTCFG4_OUTCFG18_TIMER71 = 15
,
TIMER_OUTCFG4_OUTCFG18_TIMER80 = 16
, TIMER_OUTCFG4_OUTCFG18_TIMER81 = 17
, TIMER_OUTCFG4_OUTCFG18_TIMER90 = 18
, TIMER_OUTCFG4_OUTCFG18_TIMER91 = 19
,
TIMER_OUTCFG4_OUTCFG18_TIMER100 = 20
, TIMER_OUTCFG4_OUTCFG18_TIMER101 = 21
, TIMER_OUTCFG4_OUTCFG18_TIMER110 = 22
, TIMER_OUTCFG4_OUTCFG18_TIMER111 = 23
,
TIMER_OUTCFG4_OUTCFG18_TIMER120 = 24
, TIMER_OUTCFG4_OUTCFG18_TIMER121 = 25
, TIMER_OUTCFG4_OUTCFG18_TIMER130 = 26
, TIMER_OUTCFG4_OUTCFG18_TIMER131 = 27
,
TIMER_OUTCFG4_OUTCFG18_TIMER140 = 28
, TIMER_OUTCFG4_OUTCFG18_TIMER141 = 29
, TIMER_OUTCFG4_OUTCFG18_TIMER150 = 30
, TIMER_OUTCFG4_OUTCFG18_TIMER151 = 31
,
TIMER_OUTCFG4_OUTCFG18_STIMER0 = 32
, TIMER_OUTCFG4_OUTCFG18_STIMER1 = 33
, TIMER_OUTCFG4_OUTCFG18_STIMER2 = 34
, TIMER_OUTCFG4_OUTCFG18_STIMER3 = 35
,
TIMER_OUTCFG4_OUTCFG18_STIMER4 = 36
, TIMER_OUTCFG4_OUTCFG18_STIMER5 = 37
, TIMER_OUTCFG4_OUTCFG18_STIMER6 = 38
, TIMER_OUTCFG4_OUTCFG18_STIMER7 = 39
,
TIMER_OUTCFG4_OUTCFG18_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG4_OUTCFG17_Enum {
TIMER_OUTCFG4_OUTCFG17_TIMER00 = 0
, TIMER_OUTCFG4_OUTCFG17_TIMER01 = 1
, TIMER_OUTCFG4_OUTCFG17_TIMER10 = 2
, TIMER_OUTCFG4_OUTCFG17_TIMER11 = 3
,
TIMER_OUTCFG4_OUTCFG17_TIMER20 = 4
, TIMER_OUTCFG4_OUTCFG17_TIMER21 = 5
, TIMER_OUTCFG4_OUTCFG17_TIMER30 = 6
, TIMER_OUTCFG4_OUTCFG17_TIMER31 = 7
,
TIMER_OUTCFG4_OUTCFG17_TIMER40 = 8
, TIMER_OUTCFG4_OUTCFG17_TIMER41 = 9
, TIMER_OUTCFG4_OUTCFG17_TIMER50 = 10
, TIMER_OUTCFG4_OUTCFG17_TIMER51 = 11
,
TIMER_OUTCFG4_OUTCFG17_TIMER60 = 12
, TIMER_OUTCFG4_OUTCFG17_TIMER61 = 13
, TIMER_OUTCFG4_OUTCFG17_TIMER70 = 14
, TIMER_OUTCFG4_OUTCFG17_TIMER71 = 15
,
TIMER_OUTCFG4_OUTCFG17_TIMER80 = 16
, TIMER_OUTCFG4_OUTCFG17_TIMER81 = 17
, TIMER_OUTCFG4_OUTCFG17_TIMER90 = 18
, TIMER_OUTCFG4_OUTCFG17_TIMER91 = 19
,
TIMER_OUTCFG4_OUTCFG17_TIMER100 = 20
, TIMER_OUTCFG4_OUTCFG17_TIMER101 = 21
, TIMER_OUTCFG4_OUTCFG17_TIMER110 = 22
, TIMER_OUTCFG4_OUTCFG17_TIMER111 = 23
,
TIMER_OUTCFG4_OUTCFG17_TIMER120 = 24
, TIMER_OUTCFG4_OUTCFG17_TIMER121 = 25
, TIMER_OUTCFG4_OUTCFG17_TIMER130 = 26
, TIMER_OUTCFG4_OUTCFG17_TIMER131 = 27
,
TIMER_OUTCFG4_OUTCFG17_TIMER140 = 28
, TIMER_OUTCFG4_OUTCFG17_TIMER141 = 29
, TIMER_OUTCFG4_OUTCFG17_TIMER150 = 30
, TIMER_OUTCFG4_OUTCFG17_TIMER151 = 31
,
TIMER_OUTCFG4_OUTCFG17_STIMER0 = 32
, TIMER_OUTCFG4_OUTCFG17_STIMER1 = 33
, TIMER_OUTCFG4_OUTCFG17_STIMER2 = 34
, TIMER_OUTCFG4_OUTCFG17_STIMER3 = 35
,
TIMER_OUTCFG4_OUTCFG17_STIMER4 = 36
, TIMER_OUTCFG4_OUTCFG17_STIMER5 = 37
, TIMER_OUTCFG4_OUTCFG17_STIMER6 = 38
, TIMER_OUTCFG4_OUTCFG17_STIMER7 = 39
,
TIMER_OUTCFG4_OUTCFG17_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG4_OUTCFG16_Enum {
TIMER_OUTCFG4_OUTCFG16_TIMER00 = 0
, TIMER_OUTCFG4_OUTCFG16_TIMER01 = 1
, TIMER_OUTCFG4_OUTCFG16_TIMER10 = 2
, TIMER_OUTCFG4_OUTCFG16_TIMER11 = 3
,
TIMER_OUTCFG4_OUTCFG16_TIMER20 = 4
, TIMER_OUTCFG4_OUTCFG16_TIMER21 = 5
, TIMER_OUTCFG4_OUTCFG16_TIMER30 = 6
, TIMER_OUTCFG4_OUTCFG16_TIMER31 = 7
,
TIMER_OUTCFG4_OUTCFG16_TIMER40 = 8
, TIMER_OUTCFG4_OUTCFG16_TIMER41 = 9
, TIMER_OUTCFG4_OUTCFG16_TIMER50 = 10
, TIMER_OUTCFG4_OUTCFG16_TIMER51 = 11
,
TIMER_OUTCFG4_OUTCFG16_TIMER60 = 12
, TIMER_OUTCFG4_OUTCFG16_TIMER61 = 13
, TIMER_OUTCFG4_OUTCFG16_TIMER70 = 14
, TIMER_OUTCFG4_OUTCFG16_TIMER71 = 15
,
TIMER_OUTCFG4_OUTCFG16_TIMER80 = 16
, TIMER_OUTCFG4_OUTCFG16_TIMER81 = 17
, TIMER_OUTCFG4_OUTCFG16_TIMER90 = 18
, TIMER_OUTCFG4_OUTCFG16_TIMER91 = 19
,
TIMER_OUTCFG4_OUTCFG16_TIMER100 = 20
, TIMER_OUTCFG4_OUTCFG16_TIMER101 = 21
, TIMER_OUTCFG4_OUTCFG16_TIMER110 = 22
, TIMER_OUTCFG4_OUTCFG16_TIMER111 = 23
,
TIMER_OUTCFG4_OUTCFG16_TIMER120 = 24
, TIMER_OUTCFG4_OUTCFG16_TIMER121 = 25
, TIMER_OUTCFG4_OUTCFG16_TIMER130 = 26
, TIMER_OUTCFG4_OUTCFG16_TIMER131 = 27
,
TIMER_OUTCFG4_OUTCFG16_TIMER140 = 28
, TIMER_OUTCFG4_OUTCFG16_TIMER141 = 29
, TIMER_OUTCFG4_OUTCFG16_TIMER150 = 30
, TIMER_OUTCFG4_OUTCFG16_TIMER151 = 31
,
TIMER_OUTCFG4_OUTCFG16_STIMER0 = 32
, TIMER_OUTCFG4_OUTCFG16_STIMER1 = 33
, TIMER_OUTCFG4_OUTCFG16_STIMER2 = 34
, TIMER_OUTCFG4_OUTCFG16_STIMER3 = 35
,
TIMER_OUTCFG4_OUTCFG16_STIMER4 = 36
, TIMER_OUTCFG4_OUTCFG16_STIMER5 = 37
, TIMER_OUTCFG4_OUTCFG16_STIMER6 = 38
, TIMER_OUTCFG4_OUTCFG16_STIMER7 = 39
,
TIMER_OUTCFG4_OUTCFG16_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG5_OUTCFG23_Enum {
TIMER_OUTCFG5_OUTCFG23_TIMER00 = 0
, TIMER_OUTCFG5_OUTCFG23_TIMER01 = 1
, TIMER_OUTCFG5_OUTCFG23_TIMER10 = 2
, TIMER_OUTCFG5_OUTCFG23_TIMER11 = 3
,
TIMER_OUTCFG5_OUTCFG23_TIMER20 = 4
, TIMER_OUTCFG5_OUTCFG23_TIMER21 = 5
, TIMER_OUTCFG5_OUTCFG23_TIMER30 = 6
, TIMER_OUTCFG5_OUTCFG23_TIMER31 = 7
,
TIMER_OUTCFG5_OUTCFG23_TIMER40 = 8
, TIMER_OUTCFG5_OUTCFG23_TIMER41 = 9
, TIMER_OUTCFG5_OUTCFG23_TIMER50 = 10
, TIMER_OUTCFG5_OUTCFG23_TIMER51 = 11
,
TIMER_OUTCFG5_OUTCFG23_TIMER60 = 12
, TIMER_OUTCFG5_OUTCFG23_TIMER61 = 13
, TIMER_OUTCFG5_OUTCFG23_TIMER70 = 14
, TIMER_OUTCFG5_OUTCFG23_TIMER71 = 15
,
TIMER_OUTCFG5_OUTCFG23_TIMER80 = 16
, TIMER_OUTCFG5_OUTCFG23_TIMER81 = 17
, TIMER_OUTCFG5_OUTCFG23_TIMER90 = 18
, TIMER_OUTCFG5_OUTCFG23_TIMER91 = 19
,
TIMER_OUTCFG5_OUTCFG23_TIMER100 = 20
, TIMER_OUTCFG5_OUTCFG23_TIMER101 = 21
, TIMER_OUTCFG5_OUTCFG23_TIMER110 = 22
, TIMER_OUTCFG5_OUTCFG23_TIMER111 = 23
,
TIMER_OUTCFG5_OUTCFG23_TIMER120 = 24
, TIMER_OUTCFG5_OUTCFG23_TIMER121 = 25
, TIMER_OUTCFG5_OUTCFG23_TIMER130 = 26
, TIMER_OUTCFG5_OUTCFG23_TIMER131 = 27
,
TIMER_OUTCFG5_OUTCFG23_TIMER140 = 28
, TIMER_OUTCFG5_OUTCFG23_TIMER141 = 29
, TIMER_OUTCFG5_OUTCFG23_TIMER150 = 30
, TIMER_OUTCFG5_OUTCFG23_TIMER151 = 31
,
TIMER_OUTCFG5_OUTCFG23_STIMER0 = 32
, TIMER_OUTCFG5_OUTCFG23_STIMER1 = 33
, TIMER_OUTCFG5_OUTCFG23_STIMER2 = 34
, TIMER_OUTCFG5_OUTCFG23_STIMER3 = 35
,
TIMER_OUTCFG5_OUTCFG23_STIMER4 = 36
, TIMER_OUTCFG5_OUTCFG23_STIMER5 = 37
, TIMER_OUTCFG5_OUTCFG23_STIMER6 = 38
, TIMER_OUTCFG5_OUTCFG23_STIMER7 = 39
,
TIMER_OUTCFG5_OUTCFG23_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG5_OUTCFG22_Enum {
TIMER_OUTCFG5_OUTCFG22_TIMER00 = 0
, TIMER_OUTCFG5_OUTCFG22_TIMER01 = 1
, TIMER_OUTCFG5_OUTCFG22_TIMER10 = 2
, TIMER_OUTCFG5_OUTCFG22_TIMER11 = 3
,
TIMER_OUTCFG5_OUTCFG22_TIMER20 = 4
, TIMER_OUTCFG5_OUTCFG22_TIMER21 = 5
, TIMER_OUTCFG5_OUTCFG22_TIMER30 = 6
, TIMER_OUTCFG5_OUTCFG22_TIMER31 = 7
,
TIMER_OUTCFG5_OUTCFG22_TIMER40 = 8
, TIMER_OUTCFG5_OUTCFG22_TIMER41 = 9
, TIMER_OUTCFG5_OUTCFG22_TIMER50 = 10
, TIMER_OUTCFG5_OUTCFG22_TIMER51 = 11
,
TIMER_OUTCFG5_OUTCFG22_TIMER60 = 12
, TIMER_OUTCFG5_OUTCFG22_TIMER61 = 13
, TIMER_OUTCFG5_OUTCFG22_TIMER70 = 14
, TIMER_OUTCFG5_OUTCFG22_TIMER71 = 15
,
TIMER_OUTCFG5_OUTCFG22_TIMER80 = 16
, TIMER_OUTCFG5_OUTCFG22_TIMER81 = 17
, TIMER_OUTCFG5_OUTCFG22_TIMER90 = 18
, TIMER_OUTCFG5_OUTCFG22_TIMER91 = 19
,
TIMER_OUTCFG5_OUTCFG22_TIMER100 = 20
, TIMER_OUTCFG5_OUTCFG22_TIMER101 = 21
, TIMER_OUTCFG5_OUTCFG22_TIMER110 = 22
, TIMER_OUTCFG5_OUTCFG22_TIMER111 = 23
,
TIMER_OUTCFG5_OUTCFG22_TIMER120 = 24
, TIMER_OUTCFG5_OUTCFG22_TIMER121 = 25
, TIMER_OUTCFG5_OUTCFG22_TIMER130 = 26
, TIMER_OUTCFG5_OUTCFG22_TIMER131 = 27
,
TIMER_OUTCFG5_OUTCFG22_TIMER140 = 28
, TIMER_OUTCFG5_OUTCFG22_TIMER141 = 29
, TIMER_OUTCFG5_OUTCFG22_TIMER150 = 30
, TIMER_OUTCFG5_OUTCFG22_TIMER151 = 31
,
TIMER_OUTCFG5_OUTCFG22_STIMER0 = 32
, TIMER_OUTCFG5_OUTCFG22_STIMER1 = 33
, TIMER_OUTCFG5_OUTCFG22_STIMER2 = 34
, TIMER_OUTCFG5_OUTCFG22_STIMER3 = 35
,
TIMER_OUTCFG5_OUTCFG22_STIMER4 = 36
, TIMER_OUTCFG5_OUTCFG22_STIMER5 = 37
, TIMER_OUTCFG5_OUTCFG22_STIMER6 = 38
, TIMER_OUTCFG5_OUTCFG22_STIMER7 = 39
,
TIMER_OUTCFG5_OUTCFG22_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG5_OUTCFG21_Enum {
TIMER_OUTCFG5_OUTCFG21_TIMER00 = 0
, TIMER_OUTCFG5_OUTCFG21_TIMER01 = 1
, TIMER_OUTCFG5_OUTCFG21_TIMER10 = 2
, TIMER_OUTCFG5_OUTCFG21_TIMER11 = 3
,
TIMER_OUTCFG5_OUTCFG21_TIMER20 = 4
, TIMER_OUTCFG5_OUTCFG21_TIMER21 = 5
, TIMER_OUTCFG5_OUTCFG21_TIMER30 = 6
, TIMER_OUTCFG5_OUTCFG21_TIMER31 = 7
,
TIMER_OUTCFG5_OUTCFG21_TIMER40 = 8
, TIMER_OUTCFG5_OUTCFG21_TIMER41 = 9
, TIMER_OUTCFG5_OUTCFG21_TIMER50 = 10
, TIMER_OUTCFG5_OUTCFG21_TIMER51 = 11
,
TIMER_OUTCFG5_OUTCFG21_TIMER60 = 12
, TIMER_OUTCFG5_OUTCFG21_TIMER61 = 13
, TIMER_OUTCFG5_OUTCFG21_TIMER70 = 14
, TIMER_OUTCFG5_OUTCFG21_TIMER71 = 15
,
TIMER_OUTCFG5_OUTCFG21_TIMER80 = 16
, TIMER_OUTCFG5_OUTCFG21_TIMER81 = 17
, TIMER_OUTCFG5_OUTCFG21_TIMER90 = 18
, TIMER_OUTCFG5_OUTCFG21_TIMER91 = 19
,
TIMER_OUTCFG5_OUTCFG21_TIMER100 = 20
, TIMER_OUTCFG5_OUTCFG21_TIMER101 = 21
, TIMER_OUTCFG5_OUTCFG21_TIMER110 = 22
, TIMER_OUTCFG5_OUTCFG21_TIMER111 = 23
,
TIMER_OUTCFG5_OUTCFG21_TIMER120 = 24
, TIMER_OUTCFG5_OUTCFG21_TIMER121 = 25
, TIMER_OUTCFG5_OUTCFG21_TIMER130 = 26
, TIMER_OUTCFG5_OUTCFG21_TIMER131 = 27
,
TIMER_OUTCFG5_OUTCFG21_TIMER140 = 28
, TIMER_OUTCFG5_OUTCFG21_TIMER141 = 29
, TIMER_OUTCFG5_OUTCFG21_TIMER150 = 30
, TIMER_OUTCFG5_OUTCFG21_TIMER151 = 31
,
TIMER_OUTCFG5_OUTCFG21_STIMER0 = 32
, TIMER_OUTCFG5_OUTCFG21_STIMER1 = 33
, TIMER_OUTCFG5_OUTCFG21_STIMER2 = 34
, TIMER_OUTCFG5_OUTCFG21_STIMER3 = 35
,
TIMER_OUTCFG5_OUTCFG21_STIMER4 = 36
, TIMER_OUTCFG5_OUTCFG21_STIMER5 = 37
, TIMER_OUTCFG5_OUTCFG21_STIMER6 = 38
, TIMER_OUTCFG5_OUTCFG21_STIMER7 = 39
,
TIMER_OUTCFG5_OUTCFG21_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG5_OUTCFG20_Enum {
TIMER_OUTCFG5_OUTCFG20_TIMER00 = 0
, TIMER_OUTCFG5_OUTCFG20_TIMER01 = 1
, TIMER_OUTCFG5_OUTCFG20_TIMER10 = 2
, TIMER_OUTCFG5_OUTCFG20_TIMER11 = 3
,
TIMER_OUTCFG5_OUTCFG20_TIMER20 = 4
, TIMER_OUTCFG5_OUTCFG20_TIMER21 = 5
, TIMER_OUTCFG5_OUTCFG20_TIMER30 = 6
, TIMER_OUTCFG5_OUTCFG20_TIMER31 = 7
,
TIMER_OUTCFG5_OUTCFG20_TIMER40 = 8
, TIMER_OUTCFG5_OUTCFG20_TIMER41 = 9
, TIMER_OUTCFG5_OUTCFG20_TIMER50 = 10
, TIMER_OUTCFG5_OUTCFG20_TIMER51 = 11
,
TIMER_OUTCFG5_OUTCFG20_TIMER60 = 12
, TIMER_OUTCFG5_OUTCFG20_TIMER61 = 13
, TIMER_OUTCFG5_OUTCFG20_TIMER70 = 14
, TIMER_OUTCFG5_OUTCFG20_TIMER71 = 15
,
TIMER_OUTCFG5_OUTCFG20_TIMER80 = 16
, TIMER_OUTCFG5_OUTCFG20_TIMER81 = 17
, TIMER_OUTCFG5_OUTCFG20_TIMER90 = 18
, TIMER_OUTCFG5_OUTCFG20_TIMER91 = 19
,
TIMER_OUTCFG5_OUTCFG20_TIMER100 = 20
, TIMER_OUTCFG5_OUTCFG20_TIMER101 = 21
, TIMER_OUTCFG5_OUTCFG20_TIMER110 = 22
, TIMER_OUTCFG5_OUTCFG20_TIMER111 = 23
,
TIMER_OUTCFG5_OUTCFG20_TIMER120 = 24
, TIMER_OUTCFG5_OUTCFG20_TIMER121 = 25
, TIMER_OUTCFG5_OUTCFG20_TIMER130 = 26
, TIMER_OUTCFG5_OUTCFG20_TIMER131 = 27
,
TIMER_OUTCFG5_OUTCFG20_TIMER140 = 28
, TIMER_OUTCFG5_OUTCFG20_TIMER141 = 29
, TIMER_OUTCFG5_OUTCFG20_TIMER150 = 30
, TIMER_OUTCFG5_OUTCFG20_TIMER151 = 31
,
TIMER_OUTCFG5_OUTCFG20_STIMER0 = 32
, TIMER_OUTCFG5_OUTCFG20_STIMER1 = 33
, TIMER_OUTCFG5_OUTCFG20_STIMER2 = 34
, TIMER_OUTCFG5_OUTCFG20_STIMER3 = 35
,
TIMER_OUTCFG5_OUTCFG20_STIMER4 = 36
, TIMER_OUTCFG5_OUTCFG20_STIMER5 = 37
, TIMER_OUTCFG5_OUTCFG20_STIMER6 = 38
, TIMER_OUTCFG5_OUTCFG20_STIMER7 = 39
,
TIMER_OUTCFG5_OUTCFG20_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG6_OUTCFG27_Enum {
TIMER_OUTCFG6_OUTCFG27_TIMER00 = 0
, TIMER_OUTCFG6_OUTCFG27_TIMER01 = 1
, TIMER_OUTCFG6_OUTCFG27_TIMER10 = 2
, TIMER_OUTCFG6_OUTCFG27_TIMER11 = 3
,
TIMER_OUTCFG6_OUTCFG27_TIMER20 = 4
, TIMER_OUTCFG6_OUTCFG27_TIMER21 = 5
, TIMER_OUTCFG6_OUTCFG27_TIMER30 = 6
, TIMER_OUTCFG6_OUTCFG27_TIMER31 = 7
,
TIMER_OUTCFG6_OUTCFG27_TIMER40 = 8
, TIMER_OUTCFG6_OUTCFG27_TIMER41 = 9
, TIMER_OUTCFG6_OUTCFG27_TIMER50 = 10
, TIMER_OUTCFG6_OUTCFG27_TIMER51 = 11
,
TIMER_OUTCFG6_OUTCFG27_TIMER60 = 12
, TIMER_OUTCFG6_OUTCFG27_TIMER61 = 13
, TIMER_OUTCFG6_OUTCFG27_TIMER70 = 14
, TIMER_OUTCFG6_OUTCFG27_TIMER71 = 15
,
TIMER_OUTCFG6_OUTCFG27_TIMER80 = 16
, TIMER_OUTCFG6_OUTCFG27_TIMER81 = 17
, TIMER_OUTCFG6_OUTCFG27_TIMER90 = 18
, TIMER_OUTCFG6_OUTCFG27_TIMER91 = 19
,
TIMER_OUTCFG6_OUTCFG27_TIMER100 = 20
, TIMER_OUTCFG6_OUTCFG27_TIMER101 = 21
, TIMER_OUTCFG6_OUTCFG27_TIMER110 = 22
, TIMER_OUTCFG6_OUTCFG27_TIMER111 = 23
,
TIMER_OUTCFG6_OUTCFG27_TIMER120 = 24
, TIMER_OUTCFG6_OUTCFG27_TIMER121 = 25
, TIMER_OUTCFG6_OUTCFG27_TIMER130 = 26
, TIMER_OUTCFG6_OUTCFG27_TIMER131 = 27
,
TIMER_OUTCFG6_OUTCFG27_TIMER140 = 28
, TIMER_OUTCFG6_OUTCFG27_TIMER141 = 29
, TIMER_OUTCFG6_OUTCFG27_TIMER150 = 30
, TIMER_OUTCFG6_OUTCFG27_TIMER151 = 31
,
TIMER_OUTCFG6_OUTCFG27_STIMER0 = 32
, TIMER_OUTCFG6_OUTCFG27_STIMER1 = 33
, TIMER_OUTCFG6_OUTCFG27_STIMER2 = 34
, TIMER_OUTCFG6_OUTCFG27_STIMER3 = 35
,
TIMER_OUTCFG6_OUTCFG27_STIMER4 = 36
, TIMER_OUTCFG6_OUTCFG27_STIMER5 = 37
, TIMER_OUTCFG6_OUTCFG27_STIMER6 = 38
, TIMER_OUTCFG6_OUTCFG27_STIMER7 = 39
,
TIMER_OUTCFG6_OUTCFG27_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG6_OUTCFG26_Enum {
TIMER_OUTCFG6_OUTCFG26_TIMER00 = 0
, TIMER_OUTCFG6_OUTCFG26_TIMER01 = 1
, TIMER_OUTCFG6_OUTCFG26_TIMER10 = 2
, TIMER_OUTCFG6_OUTCFG26_TIMER11 = 3
,
TIMER_OUTCFG6_OUTCFG26_TIMER20 = 4
, TIMER_OUTCFG6_OUTCFG26_TIMER21 = 5
, TIMER_OUTCFG6_OUTCFG26_TIMER30 = 6
, TIMER_OUTCFG6_OUTCFG26_TIMER31 = 7
,
TIMER_OUTCFG6_OUTCFG26_TIMER40 = 8
, TIMER_OUTCFG6_OUTCFG26_TIMER41 = 9
, TIMER_OUTCFG6_OUTCFG26_TIMER50 = 10
, TIMER_OUTCFG6_OUTCFG26_TIMER51 = 11
,
TIMER_OUTCFG6_OUTCFG26_TIMER60 = 12
, TIMER_OUTCFG6_OUTCFG26_TIMER61 = 13
, TIMER_OUTCFG6_OUTCFG26_TIMER70 = 14
, TIMER_OUTCFG6_OUTCFG26_TIMER71 = 15
,
TIMER_OUTCFG6_OUTCFG26_TIMER80 = 16
, TIMER_OUTCFG6_OUTCFG26_TIMER81 = 17
, TIMER_OUTCFG6_OUTCFG26_TIMER90 = 18
, TIMER_OUTCFG6_OUTCFG26_TIMER91 = 19
,
TIMER_OUTCFG6_OUTCFG26_TIMER100 = 20
, TIMER_OUTCFG6_OUTCFG26_TIMER101 = 21
, TIMER_OUTCFG6_OUTCFG26_TIMER110 = 22
, TIMER_OUTCFG6_OUTCFG26_TIMER111 = 23
,
TIMER_OUTCFG6_OUTCFG26_TIMER120 = 24
, TIMER_OUTCFG6_OUTCFG26_TIMER121 = 25
, TIMER_OUTCFG6_OUTCFG26_TIMER130 = 26
, TIMER_OUTCFG6_OUTCFG26_TIMER131 = 27
,
TIMER_OUTCFG6_OUTCFG26_TIMER140 = 28
, TIMER_OUTCFG6_OUTCFG26_TIMER141 = 29
, TIMER_OUTCFG6_OUTCFG26_TIMER150 = 30
, TIMER_OUTCFG6_OUTCFG26_TIMER151 = 31
,
TIMER_OUTCFG6_OUTCFG26_STIMER0 = 32
, TIMER_OUTCFG6_OUTCFG26_STIMER1 = 33
, TIMER_OUTCFG6_OUTCFG26_STIMER2 = 34
, TIMER_OUTCFG6_OUTCFG26_STIMER3 = 35
,
TIMER_OUTCFG6_OUTCFG26_STIMER4 = 36
, TIMER_OUTCFG6_OUTCFG26_STIMER5 = 37
, TIMER_OUTCFG6_OUTCFG26_STIMER6 = 38
, TIMER_OUTCFG6_OUTCFG26_STIMER7 = 39
,
TIMER_OUTCFG6_OUTCFG26_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG6_OUTCFG25_Enum {
TIMER_OUTCFG6_OUTCFG25_TIMER00 = 0
, TIMER_OUTCFG6_OUTCFG25_TIMER01 = 1
, TIMER_OUTCFG6_OUTCFG25_TIMER10 = 2
, TIMER_OUTCFG6_OUTCFG25_TIMER11 = 3
,
TIMER_OUTCFG6_OUTCFG25_TIMER20 = 4
, TIMER_OUTCFG6_OUTCFG25_TIMER21 = 5
, TIMER_OUTCFG6_OUTCFG25_TIMER30 = 6
, TIMER_OUTCFG6_OUTCFG25_TIMER31 = 7
,
TIMER_OUTCFG6_OUTCFG25_TIMER40 = 8
, TIMER_OUTCFG6_OUTCFG25_TIMER41 = 9
, TIMER_OUTCFG6_OUTCFG25_TIMER50 = 10
, TIMER_OUTCFG6_OUTCFG25_TIMER51 = 11
,
TIMER_OUTCFG6_OUTCFG25_TIMER60 = 12
, TIMER_OUTCFG6_OUTCFG25_TIMER61 = 13
, TIMER_OUTCFG6_OUTCFG25_TIMER70 = 14
, TIMER_OUTCFG6_OUTCFG25_TIMER71 = 15
,
TIMER_OUTCFG6_OUTCFG25_TIMER80 = 16
, TIMER_OUTCFG6_OUTCFG25_TIMER81 = 17
, TIMER_OUTCFG6_OUTCFG25_TIMER90 = 18
, TIMER_OUTCFG6_OUTCFG25_TIMER91 = 19
,
TIMER_OUTCFG6_OUTCFG25_TIMER100 = 20
, TIMER_OUTCFG6_OUTCFG25_TIMER101 = 21
, TIMER_OUTCFG6_OUTCFG25_TIMER110 = 22
, TIMER_OUTCFG6_OUTCFG25_TIMER111 = 23
,
TIMER_OUTCFG6_OUTCFG25_TIMER120 = 24
, TIMER_OUTCFG6_OUTCFG25_TIMER121 = 25
, TIMER_OUTCFG6_OUTCFG25_TIMER130 = 26
, TIMER_OUTCFG6_OUTCFG25_TIMER131 = 27
,
TIMER_OUTCFG6_OUTCFG25_TIMER140 = 28
, TIMER_OUTCFG6_OUTCFG25_TIMER141 = 29
, TIMER_OUTCFG6_OUTCFG25_TIMER150 = 30
, TIMER_OUTCFG6_OUTCFG25_TIMER151 = 31
,
TIMER_OUTCFG6_OUTCFG25_STIMER0 = 32
, TIMER_OUTCFG6_OUTCFG25_STIMER1 = 33
, TIMER_OUTCFG6_OUTCFG25_STIMER2 = 34
, TIMER_OUTCFG6_OUTCFG25_STIMER3 = 35
,
TIMER_OUTCFG6_OUTCFG25_STIMER4 = 36
, TIMER_OUTCFG6_OUTCFG25_STIMER5 = 37
, TIMER_OUTCFG6_OUTCFG25_STIMER6 = 38
, TIMER_OUTCFG6_OUTCFG25_STIMER7 = 39
,
TIMER_OUTCFG6_OUTCFG25_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG6_OUTCFG24_Enum {
TIMER_OUTCFG6_OUTCFG24_TIMER00 = 0
, TIMER_OUTCFG6_OUTCFG24_TIMER01 = 1
, TIMER_OUTCFG6_OUTCFG24_TIMER10 = 2
, TIMER_OUTCFG6_OUTCFG24_TIMER11 = 3
,
TIMER_OUTCFG6_OUTCFG24_TIMER20 = 4
, TIMER_OUTCFG6_OUTCFG24_TIMER21 = 5
, TIMER_OUTCFG6_OUTCFG24_TIMER30 = 6
, TIMER_OUTCFG6_OUTCFG24_TIMER31 = 7
,
TIMER_OUTCFG6_OUTCFG24_TIMER40 = 8
, TIMER_OUTCFG6_OUTCFG24_TIMER41 = 9
, TIMER_OUTCFG6_OUTCFG24_TIMER50 = 10
, TIMER_OUTCFG6_OUTCFG24_TIMER51 = 11
,
TIMER_OUTCFG6_OUTCFG24_TIMER60 = 12
, TIMER_OUTCFG6_OUTCFG24_TIMER61 = 13
, TIMER_OUTCFG6_OUTCFG24_TIMER70 = 14
, TIMER_OUTCFG6_OUTCFG24_TIMER71 = 15
,
TIMER_OUTCFG6_OUTCFG24_TIMER80 = 16
, TIMER_OUTCFG6_OUTCFG24_TIMER81 = 17
, TIMER_OUTCFG6_OUTCFG24_TIMER90 = 18
, TIMER_OUTCFG6_OUTCFG24_TIMER91 = 19
,
TIMER_OUTCFG6_OUTCFG24_TIMER100 = 20
, TIMER_OUTCFG6_OUTCFG24_TIMER101 = 21
, TIMER_OUTCFG6_OUTCFG24_TIMER110 = 22
, TIMER_OUTCFG6_OUTCFG24_TIMER111 = 23
,
TIMER_OUTCFG6_OUTCFG24_TIMER120 = 24
, TIMER_OUTCFG6_OUTCFG24_TIMER121 = 25
, TIMER_OUTCFG6_OUTCFG24_TIMER130 = 26
, TIMER_OUTCFG6_OUTCFG24_TIMER131 = 27
,
TIMER_OUTCFG6_OUTCFG24_TIMER140 = 28
, TIMER_OUTCFG6_OUTCFG24_TIMER141 = 29
, TIMER_OUTCFG6_OUTCFG24_TIMER150 = 30
, TIMER_OUTCFG6_OUTCFG24_TIMER151 = 31
,
TIMER_OUTCFG6_OUTCFG24_STIMER0 = 32
, TIMER_OUTCFG6_OUTCFG24_STIMER1 = 33
, TIMER_OUTCFG6_OUTCFG24_STIMER2 = 34
, TIMER_OUTCFG6_OUTCFG24_STIMER3 = 35
,
TIMER_OUTCFG6_OUTCFG24_STIMER4 = 36
, TIMER_OUTCFG6_OUTCFG24_STIMER5 = 37
, TIMER_OUTCFG6_OUTCFG24_STIMER6 = 38
, TIMER_OUTCFG6_OUTCFG24_STIMER7 = 39
,
TIMER_OUTCFG6_OUTCFG24_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG7_OUTCFG31_Enum {
TIMER_OUTCFG7_OUTCFG31_TIMER00 = 0
, TIMER_OUTCFG7_OUTCFG31_TIMER01 = 1
, TIMER_OUTCFG7_OUTCFG31_TIMER10 = 2
, TIMER_OUTCFG7_OUTCFG31_TIMER11 = 3
,
TIMER_OUTCFG7_OUTCFG31_TIMER20 = 4
, TIMER_OUTCFG7_OUTCFG31_TIMER21 = 5
, TIMER_OUTCFG7_OUTCFG31_TIMER30 = 6
, TIMER_OUTCFG7_OUTCFG31_TIMER31 = 7
,
TIMER_OUTCFG7_OUTCFG31_TIMER40 = 8
, TIMER_OUTCFG7_OUTCFG31_TIMER41 = 9
, TIMER_OUTCFG7_OUTCFG31_TIMER50 = 10
, TIMER_OUTCFG7_OUTCFG31_TIMER51 = 11
,
TIMER_OUTCFG7_OUTCFG31_TIMER60 = 12
, TIMER_OUTCFG7_OUTCFG31_TIMER61 = 13
, TIMER_OUTCFG7_OUTCFG31_TIMER70 = 14
, TIMER_OUTCFG7_OUTCFG31_TIMER71 = 15
,
TIMER_OUTCFG7_OUTCFG31_TIMER80 = 16
, TIMER_OUTCFG7_OUTCFG31_TIMER81 = 17
, TIMER_OUTCFG7_OUTCFG31_TIMER90 = 18
, TIMER_OUTCFG7_OUTCFG31_TIMER91 = 19
,
TIMER_OUTCFG7_OUTCFG31_TIMER100 = 20
, TIMER_OUTCFG7_OUTCFG31_TIMER101 = 21
, TIMER_OUTCFG7_OUTCFG31_TIMER110 = 22
, TIMER_OUTCFG7_OUTCFG31_TIMER111 = 23
,
TIMER_OUTCFG7_OUTCFG31_TIMER120 = 24
, TIMER_OUTCFG7_OUTCFG31_TIMER121 = 25
, TIMER_OUTCFG7_OUTCFG31_TIMER130 = 26
, TIMER_OUTCFG7_OUTCFG31_TIMER131 = 27
,
TIMER_OUTCFG7_OUTCFG31_TIMER140 = 28
, TIMER_OUTCFG7_OUTCFG31_TIMER141 = 29
, TIMER_OUTCFG7_OUTCFG31_TIMER150 = 30
, TIMER_OUTCFG7_OUTCFG31_TIMER151 = 31
,
TIMER_OUTCFG7_OUTCFG31_STIMER0 = 32
, TIMER_OUTCFG7_OUTCFG31_STIMER1 = 33
, TIMER_OUTCFG7_OUTCFG31_STIMER2 = 34
, TIMER_OUTCFG7_OUTCFG31_STIMER3 = 35
,
TIMER_OUTCFG7_OUTCFG31_STIMER4 = 36
, TIMER_OUTCFG7_OUTCFG31_STIMER5 = 37
, TIMER_OUTCFG7_OUTCFG31_STIMER6 = 38
, TIMER_OUTCFG7_OUTCFG31_STIMER7 = 39
,
TIMER_OUTCFG7_OUTCFG31_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG7_OUTCFG30_Enum {
TIMER_OUTCFG7_OUTCFG30_TIMER00 = 0
, TIMER_OUTCFG7_OUTCFG30_TIMER01 = 1
, TIMER_OUTCFG7_OUTCFG30_TIMER10 = 2
, TIMER_OUTCFG7_OUTCFG30_TIMER11 = 3
,
TIMER_OUTCFG7_OUTCFG30_TIMER20 = 4
, TIMER_OUTCFG7_OUTCFG30_TIMER21 = 5
, TIMER_OUTCFG7_OUTCFG30_TIMER30 = 6
, TIMER_OUTCFG7_OUTCFG30_TIMER31 = 7
,
TIMER_OUTCFG7_OUTCFG30_TIMER40 = 8
, TIMER_OUTCFG7_OUTCFG30_TIMER41 = 9
, TIMER_OUTCFG7_OUTCFG30_TIMER50 = 10
, TIMER_OUTCFG7_OUTCFG30_TIMER51 = 11
,
TIMER_OUTCFG7_OUTCFG30_TIMER60 = 12
, TIMER_OUTCFG7_OUTCFG30_TIMER61 = 13
, TIMER_OUTCFG7_OUTCFG30_TIMER70 = 14
, TIMER_OUTCFG7_OUTCFG30_TIMER71 = 15
,
TIMER_OUTCFG7_OUTCFG30_TIMER80 = 16
, TIMER_OUTCFG7_OUTCFG30_TIMER81 = 17
, TIMER_OUTCFG7_OUTCFG30_TIMER90 = 18
, TIMER_OUTCFG7_OUTCFG30_TIMER91 = 19
,
TIMER_OUTCFG7_OUTCFG30_TIMER100 = 20
, TIMER_OUTCFG7_OUTCFG30_TIMER101 = 21
, TIMER_OUTCFG7_OUTCFG30_TIMER110 = 22
, TIMER_OUTCFG7_OUTCFG30_TIMER111 = 23
,
TIMER_OUTCFG7_OUTCFG30_TIMER120 = 24
, TIMER_OUTCFG7_OUTCFG30_TIMER121 = 25
, TIMER_OUTCFG7_OUTCFG30_TIMER130 = 26
, TIMER_OUTCFG7_OUTCFG30_TIMER131 = 27
,
TIMER_OUTCFG7_OUTCFG30_TIMER140 = 28
, TIMER_OUTCFG7_OUTCFG30_TIMER141 = 29
, TIMER_OUTCFG7_OUTCFG30_TIMER150 = 30
, TIMER_OUTCFG7_OUTCFG30_TIMER151 = 31
,
TIMER_OUTCFG7_OUTCFG30_STIMER0 = 32
, TIMER_OUTCFG7_OUTCFG30_STIMER1 = 33
, TIMER_OUTCFG7_OUTCFG30_STIMER2 = 34
, TIMER_OUTCFG7_OUTCFG30_STIMER3 = 35
,
TIMER_OUTCFG7_OUTCFG30_STIMER4 = 36
, TIMER_OUTCFG7_OUTCFG30_STIMER5 = 37
, TIMER_OUTCFG7_OUTCFG30_STIMER6 = 38
, TIMER_OUTCFG7_OUTCFG30_STIMER7 = 39
,
TIMER_OUTCFG7_OUTCFG30_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG7_OUTCFG29_Enum {
TIMER_OUTCFG7_OUTCFG29_TIMER00 = 0
, TIMER_OUTCFG7_OUTCFG29_TIMER01 = 1
, TIMER_OUTCFG7_OUTCFG29_TIMER10 = 2
, TIMER_OUTCFG7_OUTCFG29_TIMER11 = 3
,
TIMER_OUTCFG7_OUTCFG29_TIMER20 = 4
, TIMER_OUTCFG7_OUTCFG29_TIMER21 = 5
, TIMER_OUTCFG7_OUTCFG29_TIMER30 = 6
, TIMER_OUTCFG7_OUTCFG29_TIMER31 = 7
,
TIMER_OUTCFG7_OUTCFG29_TIMER40 = 8
, TIMER_OUTCFG7_OUTCFG29_TIMER41 = 9
, TIMER_OUTCFG7_OUTCFG29_TIMER50 = 10
, TIMER_OUTCFG7_OUTCFG29_TIMER51 = 11
,
TIMER_OUTCFG7_OUTCFG29_TIMER60 = 12
, TIMER_OUTCFG7_OUTCFG29_TIMER61 = 13
, TIMER_OUTCFG7_OUTCFG29_TIMER70 = 14
, TIMER_OUTCFG7_OUTCFG29_TIMER71 = 15
,
TIMER_OUTCFG7_OUTCFG29_TIMER80 = 16
, TIMER_OUTCFG7_OUTCFG29_TIMER81 = 17
, TIMER_OUTCFG7_OUTCFG29_TIMER90 = 18
, TIMER_OUTCFG7_OUTCFG29_TIMER91 = 19
,
TIMER_OUTCFG7_OUTCFG29_TIMER100 = 20
, TIMER_OUTCFG7_OUTCFG29_TIMER101 = 21
, TIMER_OUTCFG7_OUTCFG29_TIMER110 = 22
, TIMER_OUTCFG7_OUTCFG29_TIMER111 = 23
,
TIMER_OUTCFG7_OUTCFG29_TIMER120 = 24
, TIMER_OUTCFG7_OUTCFG29_TIMER121 = 25
, TIMER_OUTCFG7_OUTCFG29_TIMER130 = 26
, TIMER_OUTCFG7_OUTCFG29_TIMER131 = 27
,
TIMER_OUTCFG7_OUTCFG29_TIMER140 = 28
, TIMER_OUTCFG7_OUTCFG29_TIMER141 = 29
, TIMER_OUTCFG7_OUTCFG29_TIMER150 = 30
, TIMER_OUTCFG7_OUTCFG29_TIMER151 = 31
,
TIMER_OUTCFG7_OUTCFG29_STIMER0 = 32
, TIMER_OUTCFG7_OUTCFG29_STIMER1 = 33
, TIMER_OUTCFG7_OUTCFG29_STIMER2 = 34
, TIMER_OUTCFG7_OUTCFG29_STIMER3 = 35
,
TIMER_OUTCFG7_OUTCFG29_STIMER4 = 36
, TIMER_OUTCFG7_OUTCFG29_STIMER5 = 37
, TIMER_OUTCFG7_OUTCFG29_STIMER6 = 38
, TIMER_OUTCFG7_OUTCFG29_STIMER7 = 39
,
TIMER_OUTCFG7_OUTCFG29_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG7_OUTCFG28_Enum {
TIMER_OUTCFG7_OUTCFG28_TIMER00 = 0
, TIMER_OUTCFG7_OUTCFG28_TIMER01 = 1
, TIMER_OUTCFG7_OUTCFG28_TIMER10 = 2
, TIMER_OUTCFG7_OUTCFG28_TIMER11 = 3
,
TIMER_OUTCFG7_OUTCFG28_TIMER20 = 4
, TIMER_OUTCFG7_OUTCFG28_TIMER21 = 5
, TIMER_OUTCFG7_OUTCFG28_TIMER30 = 6
, TIMER_OUTCFG7_OUTCFG28_TIMER31 = 7
,
TIMER_OUTCFG7_OUTCFG28_TIMER40 = 8
, TIMER_OUTCFG7_OUTCFG28_TIMER41 = 9
, TIMER_OUTCFG7_OUTCFG28_TIMER50 = 10
, TIMER_OUTCFG7_OUTCFG28_TIMER51 = 11
,
TIMER_OUTCFG7_OUTCFG28_TIMER60 = 12
, TIMER_OUTCFG7_OUTCFG28_TIMER61 = 13
, TIMER_OUTCFG7_OUTCFG28_TIMER70 = 14
, TIMER_OUTCFG7_OUTCFG28_TIMER71 = 15
,
TIMER_OUTCFG7_OUTCFG28_TIMER80 = 16
, TIMER_OUTCFG7_OUTCFG28_TIMER81 = 17
, TIMER_OUTCFG7_OUTCFG28_TIMER90 = 18
, TIMER_OUTCFG7_OUTCFG28_TIMER91 = 19
,
TIMER_OUTCFG7_OUTCFG28_TIMER100 = 20
, TIMER_OUTCFG7_OUTCFG28_TIMER101 = 21
, TIMER_OUTCFG7_OUTCFG28_TIMER110 = 22
, TIMER_OUTCFG7_OUTCFG28_TIMER111 = 23
,
TIMER_OUTCFG7_OUTCFG28_TIMER120 = 24
, TIMER_OUTCFG7_OUTCFG28_TIMER121 = 25
, TIMER_OUTCFG7_OUTCFG28_TIMER130 = 26
, TIMER_OUTCFG7_OUTCFG28_TIMER131 = 27
,
TIMER_OUTCFG7_OUTCFG28_TIMER140 = 28
, TIMER_OUTCFG7_OUTCFG28_TIMER141 = 29
, TIMER_OUTCFG7_OUTCFG28_TIMER150 = 30
, TIMER_OUTCFG7_OUTCFG28_TIMER151 = 31
,
TIMER_OUTCFG7_OUTCFG28_STIMER0 = 32
, TIMER_OUTCFG7_OUTCFG28_STIMER1 = 33
, TIMER_OUTCFG7_OUTCFG28_STIMER2 = 34
, TIMER_OUTCFG7_OUTCFG28_STIMER3 = 35
,
TIMER_OUTCFG7_OUTCFG28_STIMER4 = 36
, TIMER_OUTCFG7_OUTCFG28_STIMER5 = 37
, TIMER_OUTCFG7_OUTCFG28_STIMER6 = 38
, TIMER_OUTCFG7_OUTCFG28_STIMER7 = 39
,
TIMER_OUTCFG7_OUTCFG28_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG8_OUTCFG35_Enum {
TIMER_OUTCFG8_OUTCFG35_TIMER00 = 0
, TIMER_OUTCFG8_OUTCFG35_TIMER01 = 1
, TIMER_OUTCFG8_OUTCFG35_TIMER10 = 2
, TIMER_OUTCFG8_OUTCFG35_TIMER11 = 3
,
TIMER_OUTCFG8_OUTCFG35_TIMER20 = 4
, TIMER_OUTCFG8_OUTCFG35_TIMER21 = 5
, TIMER_OUTCFG8_OUTCFG35_TIMER30 = 6
, TIMER_OUTCFG8_OUTCFG35_TIMER31 = 7
,
TIMER_OUTCFG8_OUTCFG35_TIMER40 = 8
, TIMER_OUTCFG8_OUTCFG35_TIMER41 = 9
, TIMER_OUTCFG8_OUTCFG35_TIMER50 = 10
, TIMER_OUTCFG8_OUTCFG35_TIMER51 = 11
,
TIMER_OUTCFG8_OUTCFG35_TIMER60 = 12
, TIMER_OUTCFG8_OUTCFG35_TIMER61 = 13
, TIMER_OUTCFG8_OUTCFG35_TIMER70 = 14
, TIMER_OUTCFG8_OUTCFG35_TIMER71 = 15
,
TIMER_OUTCFG8_OUTCFG35_TIMER80 = 16
, TIMER_OUTCFG8_OUTCFG35_TIMER81 = 17
, TIMER_OUTCFG8_OUTCFG35_TIMER90 = 18
, TIMER_OUTCFG8_OUTCFG35_TIMER91 = 19
,
TIMER_OUTCFG8_OUTCFG35_TIMER100 = 20
, TIMER_OUTCFG8_OUTCFG35_TIMER101 = 21
, TIMER_OUTCFG8_OUTCFG35_TIMER110 = 22
, TIMER_OUTCFG8_OUTCFG35_TIMER111 = 23
,
TIMER_OUTCFG8_OUTCFG35_TIMER120 = 24
, TIMER_OUTCFG8_OUTCFG35_TIMER121 = 25
, TIMER_OUTCFG8_OUTCFG35_TIMER130 = 26
, TIMER_OUTCFG8_OUTCFG35_TIMER131 = 27
,
TIMER_OUTCFG8_OUTCFG35_TIMER140 = 28
, TIMER_OUTCFG8_OUTCFG35_TIMER141 = 29
, TIMER_OUTCFG8_OUTCFG35_TIMER150 = 30
, TIMER_OUTCFG8_OUTCFG35_TIMER151 = 31
,
TIMER_OUTCFG8_OUTCFG35_STIMER0 = 32
, TIMER_OUTCFG8_OUTCFG35_STIMER1 = 33
, TIMER_OUTCFG8_OUTCFG35_STIMER2 = 34
, TIMER_OUTCFG8_OUTCFG35_STIMER3 = 35
,
TIMER_OUTCFG8_OUTCFG35_STIMER4 = 36
, TIMER_OUTCFG8_OUTCFG35_STIMER5 = 37
, TIMER_OUTCFG8_OUTCFG35_STIMER6 = 38
, TIMER_OUTCFG8_OUTCFG35_STIMER7 = 39
,
TIMER_OUTCFG8_OUTCFG35_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG8_OUTCFG34_Enum {
TIMER_OUTCFG8_OUTCFG34_TIMER00 = 0
, TIMER_OUTCFG8_OUTCFG34_TIMER01 = 1
, TIMER_OUTCFG8_OUTCFG34_TIMER10 = 2
, TIMER_OUTCFG8_OUTCFG34_TIMER11 = 3
,
TIMER_OUTCFG8_OUTCFG34_TIMER20 = 4
, TIMER_OUTCFG8_OUTCFG34_TIMER21 = 5
, TIMER_OUTCFG8_OUTCFG34_TIMER30 = 6
, TIMER_OUTCFG8_OUTCFG34_TIMER31 = 7
,
TIMER_OUTCFG8_OUTCFG34_TIMER40 = 8
, TIMER_OUTCFG8_OUTCFG34_TIMER41 = 9
, TIMER_OUTCFG8_OUTCFG34_TIMER50 = 10
, TIMER_OUTCFG8_OUTCFG34_TIMER51 = 11
,
TIMER_OUTCFG8_OUTCFG34_TIMER60 = 12
, TIMER_OUTCFG8_OUTCFG34_TIMER61 = 13
, TIMER_OUTCFG8_OUTCFG34_TIMER70 = 14
, TIMER_OUTCFG8_OUTCFG34_TIMER71 = 15
,
TIMER_OUTCFG8_OUTCFG34_TIMER80 = 16
, TIMER_OUTCFG8_OUTCFG34_TIMER81 = 17
, TIMER_OUTCFG8_OUTCFG34_TIMER90 = 18
, TIMER_OUTCFG8_OUTCFG34_TIMER91 = 19
,
TIMER_OUTCFG8_OUTCFG34_TIMER100 = 20
, TIMER_OUTCFG8_OUTCFG34_TIMER101 = 21
, TIMER_OUTCFG8_OUTCFG34_TIMER110 = 22
, TIMER_OUTCFG8_OUTCFG34_TIMER111 = 23
,
TIMER_OUTCFG8_OUTCFG34_TIMER120 = 24
, TIMER_OUTCFG8_OUTCFG34_TIMER121 = 25
, TIMER_OUTCFG8_OUTCFG34_TIMER130 = 26
, TIMER_OUTCFG8_OUTCFG34_TIMER131 = 27
,
TIMER_OUTCFG8_OUTCFG34_TIMER140 = 28
, TIMER_OUTCFG8_OUTCFG34_TIMER141 = 29
, TIMER_OUTCFG8_OUTCFG34_TIMER150 = 30
, TIMER_OUTCFG8_OUTCFG34_TIMER151 = 31
,
TIMER_OUTCFG8_OUTCFG34_STIMER0 = 32
, TIMER_OUTCFG8_OUTCFG34_STIMER1 = 33
, TIMER_OUTCFG8_OUTCFG34_STIMER2 = 34
, TIMER_OUTCFG8_OUTCFG34_STIMER3 = 35
,
TIMER_OUTCFG8_OUTCFG34_STIMER4 = 36
, TIMER_OUTCFG8_OUTCFG34_STIMER5 = 37
, TIMER_OUTCFG8_OUTCFG34_STIMER6 = 38
, TIMER_OUTCFG8_OUTCFG34_STIMER7 = 39
,
TIMER_OUTCFG8_OUTCFG34_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG8_OUTCFG33_Enum {
TIMER_OUTCFG8_OUTCFG33_TIMER00 = 0
, TIMER_OUTCFG8_OUTCFG33_TIMER01 = 1
, TIMER_OUTCFG8_OUTCFG33_TIMER10 = 2
, TIMER_OUTCFG8_OUTCFG33_TIMER11 = 3
,
TIMER_OUTCFG8_OUTCFG33_TIMER20 = 4
, TIMER_OUTCFG8_OUTCFG33_TIMER21 = 5
, TIMER_OUTCFG8_OUTCFG33_TIMER30 = 6
, TIMER_OUTCFG8_OUTCFG33_TIMER31 = 7
,
TIMER_OUTCFG8_OUTCFG33_TIMER40 = 8
, TIMER_OUTCFG8_OUTCFG33_TIMER41 = 9
, TIMER_OUTCFG8_OUTCFG33_TIMER50 = 10
, TIMER_OUTCFG8_OUTCFG33_TIMER51 = 11
,
TIMER_OUTCFG8_OUTCFG33_TIMER60 = 12
, TIMER_OUTCFG8_OUTCFG33_TIMER61 = 13
, TIMER_OUTCFG8_OUTCFG33_TIMER70 = 14
, TIMER_OUTCFG8_OUTCFG33_TIMER71 = 15
,
TIMER_OUTCFG8_OUTCFG33_TIMER80 = 16
, TIMER_OUTCFG8_OUTCFG33_TIMER81 = 17
, TIMER_OUTCFG8_OUTCFG33_TIMER90 = 18
, TIMER_OUTCFG8_OUTCFG33_TIMER91 = 19
,
TIMER_OUTCFG8_OUTCFG33_TIMER100 = 20
, TIMER_OUTCFG8_OUTCFG33_TIMER101 = 21
, TIMER_OUTCFG8_OUTCFG33_TIMER110 = 22
, TIMER_OUTCFG8_OUTCFG33_TIMER111 = 23
,
TIMER_OUTCFG8_OUTCFG33_TIMER120 = 24
, TIMER_OUTCFG8_OUTCFG33_TIMER121 = 25
, TIMER_OUTCFG8_OUTCFG33_TIMER130 = 26
, TIMER_OUTCFG8_OUTCFG33_TIMER131 = 27
,
TIMER_OUTCFG8_OUTCFG33_TIMER140 = 28
, TIMER_OUTCFG8_OUTCFG33_TIMER141 = 29
, TIMER_OUTCFG8_OUTCFG33_TIMER150 = 30
, TIMER_OUTCFG8_OUTCFG33_TIMER151 = 31
,
TIMER_OUTCFG8_OUTCFG33_STIMER0 = 32
, TIMER_OUTCFG8_OUTCFG33_STIMER1 = 33
, TIMER_OUTCFG8_OUTCFG33_STIMER2 = 34
, TIMER_OUTCFG8_OUTCFG33_STIMER3 = 35
,
TIMER_OUTCFG8_OUTCFG33_STIMER4 = 36
, TIMER_OUTCFG8_OUTCFG33_STIMER5 = 37
, TIMER_OUTCFG8_OUTCFG33_STIMER6 = 38
, TIMER_OUTCFG8_OUTCFG33_STIMER7 = 39
,
TIMER_OUTCFG8_OUTCFG33_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG8_OUTCFG32_Enum {
TIMER_OUTCFG8_OUTCFG32_TIMER00 = 0
, TIMER_OUTCFG8_OUTCFG32_TIMER01 = 1
, TIMER_OUTCFG8_OUTCFG32_TIMER10 = 2
, TIMER_OUTCFG8_OUTCFG32_TIMER11 = 3
,
TIMER_OUTCFG8_OUTCFG32_TIMER20 = 4
, TIMER_OUTCFG8_OUTCFG32_TIMER21 = 5
, TIMER_OUTCFG8_OUTCFG32_TIMER30 = 6
, TIMER_OUTCFG8_OUTCFG32_TIMER31 = 7
,
TIMER_OUTCFG8_OUTCFG32_TIMER40 = 8
, TIMER_OUTCFG8_OUTCFG32_TIMER41 = 9
, TIMER_OUTCFG8_OUTCFG32_TIMER50 = 10
, TIMER_OUTCFG8_OUTCFG32_TIMER51 = 11
,
TIMER_OUTCFG8_OUTCFG32_TIMER60 = 12
, TIMER_OUTCFG8_OUTCFG32_TIMER61 = 13
, TIMER_OUTCFG8_OUTCFG32_TIMER70 = 14
, TIMER_OUTCFG8_OUTCFG32_TIMER71 = 15
,
TIMER_OUTCFG8_OUTCFG32_TIMER80 = 16
, TIMER_OUTCFG8_OUTCFG32_TIMER81 = 17
, TIMER_OUTCFG8_OUTCFG32_TIMER90 = 18
, TIMER_OUTCFG8_OUTCFG32_TIMER91 = 19
,
TIMER_OUTCFG8_OUTCFG32_TIMER100 = 20
, TIMER_OUTCFG8_OUTCFG32_TIMER101 = 21
, TIMER_OUTCFG8_OUTCFG32_TIMER110 = 22
, TIMER_OUTCFG8_OUTCFG32_TIMER111 = 23
,
TIMER_OUTCFG8_OUTCFG32_TIMER120 = 24
, TIMER_OUTCFG8_OUTCFG32_TIMER121 = 25
, TIMER_OUTCFG8_OUTCFG32_TIMER130 = 26
, TIMER_OUTCFG8_OUTCFG32_TIMER131 = 27
,
TIMER_OUTCFG8_OUTCFG32_TIMER140 = 28
, TIMER_OUTCFG8_OUTCFG32_TIMER141 = 29
, TIMER_OUTCFG8_OUTCFG32_TIMER150 = 30
, TIMER_OUTCFG8_OUTCFG32_TIMER151 = 31
,
TIMER_OUTCFG8_OUTCFG32_STIMER0 = 32
, TIMER_OUTCFG8_OUTCFG32_STIMER1 = 33
, TIMER_OUTCFG8_OUTCFG32_STIMER2 = 34
, TIMER_OUTCFG8_OUTCFG32_STIMER3 = 35
,
TIMER_OUTCFG8_OUTCFG32_STIMER4 = 36
, TIMER_OUTCFG8_OUTCFG32_STIMER5 = 37
, TIMER_OUTCFG8_OUTCFG32_STIMER6 = 38
, TIMER_OUTCFG8_OUTCFG32_STIMER7 = 39
,
TIMER_OUTCFG8_OUTCFG32_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG9_OUTCFG39_Enum {
TIMER_OUTCFG9_OUTCFG39_TIMER00 = 0
, TIMER_OUTCFG9_OUTCFG39_TIMER01 = 1
, TIMER_OUTCFG9_OUTCFG39_TIMER10 = 2
, TIMER_OUTCFG9_OUTCFG39_TIMER11 = 3
,
TIMER_OUTCFG9_OUTCFG39_TIMER20 = 4
, TIMER_OUTCFG9_OUTCFG39_TIMER21 = 5
, TIMER_OUTCFG9_OUTCFG39_TIMER30 = 6
, TIMER_OUTCFG9_OUTCFG39_TIMER31 = 7
,
TIMER_OUTCFG9_OUTCFG39_TIMER40 = 8
, TIMER_OUTCFG9_OUTCFG39_TIMER41 = 9
, TIMER_OUTCFG9_OUTCFG39_TIMER50 = 10
, TIMER_OUTCFG9_OUTCFG39_TIMER51 = 11
,
TIMER_OUTCFG9_OUTCFG39_TIMER60 = 12
, TIMER_OUTCFG9_OUTCFG39_TIMER61 = 13
, TIMER_OUTCFG9_OUTCFG39_TIMER70 = 14
, TIMER_OUTCFG9_OUTCFG39_TIMER71 = 15
,
TIMER_OUTCFG9_OUTCFG39_TIMER80 = 16
, TIMER_OUTCFG9_OUTCFG39_TIMER81 = 17
, TIMER_OUTCFG9_OUTCFG39_TIMER90 = 18
, TIMER_OUTCFG9_OUTCFG39_TIMER91 = 19
,
TIMER_OUTCFG9_OUTCFG39_TIMER100 = 20
, TIMER_OUTCFG9_OUTCFG39_TIMER101 = 21
, TIMER_OUTCFG9_OUTCFG39_TIMER110 = 22
, TIMER_OUTCFG9_OUTCFG39_TIMER111 = 23
,
TIMER_OUTCFG9_OUTCFG39_TIMER120 = 24
, TIMER_OUTCFG9_OUTCFG39_TIMER121 = 25
, TIMER_OUTCFG9_OUTCFG39_TIMER130 = 26
, TIMER_OUTCFG9_OUTCFG39_TIMER131 = 27
,
TIMER_OUTCFG9_OUTCFG39_TIMER140 = 28
, TIMER_OUTCFG9_OUTCFG39_TIMER141 = 29
, TIMER_OUTCFG9_OUTCFG39_TIMER150 = 30
, TIMER_OUTCFG9_OUTCFG39_TIMER151 = 31
,
TIMER_OUTCFG9_OUTCFG39_STIMER0 = 32
, TIMER_OUTCFG9_OUTCFG39_STIMER1 = 33
, TIMER_OUTCFG9_OUTCFG39_STIMER2 = 34
, TIMER_OUTCFG9_OUTCFG39_STIMER3 = 35
,
TIMER_OUTCFG9_OUTCFG39_STIMER4 = 36
, TIMER_OUTCFG9_OUTCFG39_STIMER5 = 37
, TIMER_OUTCFG9_OUTCFG39_STIMER6 = 38
, TIMER_OUTCFG9_OUTCFG39_STIMER7 = 39
,
TIMER_OUTCFG9_OUTCFG39_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG9_OUTCFG38_Enum {
TIMER_OUTCFG9_OUTCFG38_TIMER00 = 0
, TIMER_OUTCFG9_OUTCFG38_TIMER01 = 1
, TIMER_OUTCFG9_OUTCFG38_TIMER10 = 2
, TIMER_OUTCFG9_OUTCFG38_TIMER11 = 3
,
TIMER_OUTCFG9_OUTCFG38_TIMER20 = 4
, TIMER_OUTCFG9_OUTCFG38_TIMER21 = 5
, TIMER_OUTCFG9_OUTCFG38_TIMER30 = 6
, TIMER_OUTCFG9_OUTCFG38_TIMER31 = 7
,
TIMER_OUTCFG9_OUTCFG38_TIMER40 = 8
, TIMER_OUTCFG9_OUTCFG38_TIMER41 = 9
, TIMER_OUTCFG9_OUTCFG38_TIMER50 = 10
, TIMER_OUTCFG9_OUTCFG38_TIMER51 = 11
,
TIMER_OUTCFG9_OUTCFG38_TIMER60 = 12
, TIMER_OUTCFG9_OUTCFG38_TIMER61 = 13
, TIMER_OUTCFG9_OUTCFG38_TIMER70 = 14
, TIMER_OUTCFG9_OUTCFG38_TIMER71 = 15
,
TIMER_OUTCFG9_OUTCFG38_TIMER80 = 16
, TIMER_OUTCFG9_OUTCFG38_TIMER81 = 17
, TIMER_OUTCFG9_OUTCFG38_TIMER90 = 18
, TIMER_OUTCFG9_OUTCFG38_TIMER91 = 19
,
TIMER_OUTCFG9_OUTCFG38_TIMER100 = 20
, TIMER_OUTCFG9_OUTCFG38_TIMER101 = 21
, TIMER_OUTCFG9_OUTCFG38_TIMER110 = 22
, TIMER_OUTCFG9_OUTCFG38_TIMER111 = 23
,
TIMER_OUTCFG9_OUTCFG38_TIMER120 = 24
, TIMER_OUTCFG9_OUTCFG38_TIMER121 = 25
, TIMER_OUTCFG9_OUTCFG38_TIMER130 = 26
, TIMER_OUTCFG9_OUTCFG38_TIMER131 = 27
,
TIMER_OUTCFG9_OUTCFG38_TIMER140 = 28
, TIMER_OUTCFG9_OUTCFG38_TIMER141 = 29
, TIMER_OUTCFG9_OUTCFG38_TIMER150 = 30
, TIMER_OUTCFG9_OUTCFG38_TIMER151 = 31
,
TIMER_OUTCFG9_OUTCFG38_STIMER0 = 32
, TIMER_OUTCFG9_OUTCFG38_STIMER1 = 33
, TIMER_OUTCFG9_OUTCFG38_STIMER2 = 34
, TIMER_OUTCFG9_OUTCFG38_STIMER3 = 35
,
TIMER_OUTCFG9_OUTCFG38_STIMER4 = 36
, TIMER_OUTCFG9_OUTCFG38_STIMER5 = 37
, TIMER_OUTCFG9_OUTCFG38_STIMER6 = 38
, TIMER_OUTCFG9_OUTCFG38_STIMER7 = 39
,
TIMER_OUTCFG9_OUTCFG38_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG9_OUTCFG37_Enum {
TIMER_OUTCFG9_OUTCFG37_TIMER00 = 0
, TIMER_OUTCFG9_OUTCFG37_TIMER01 = 1
, TIMER_OUTCFG9_OUTCFG37_TIMER10 = 2
, TIMER_OUTCFG9_OUTCFG37_TIMER11 = 3
,
TIMER_OUTCFG9_OUTCFG37_TIMER20 = 4
, TIMER_OUTCFG9_OUTCFG37_TIMER21 = 5
, TIMER_OUTCFG9_OUTCFG37_TIMER30 = 6
, TIMER_OUTCFG9_OUTCFG37_TIMER31 = 7
,
TIMER_OUTCFG9_OUTCFG37_TIMER40 = 8
, TIMER_OUTCFG9_OUTCFG37_TIMER41 = 9
, TIMER_OUTCFG9_OUTCFG37_TIMER50 = 10
, TIMER_OUTCFG9_OUTCFG37_TIMER51 = 11
,
TIMER_OUTCFG9_OUTCFG37_TIMER60 = 12
, TIMER_OUTCFG9_OUTCFG37_TIMER61 = 13
, TIMER_OUTCFG9_OUTCFG37_TIMER70 = 14
, TIMER_OUTCFG9_OUTCFG37_TIMER71 = 15
,
TIMER_OUTCFG9_OUTCFG37_TIMER80 = 16
, TIMER_OUTCFG9_OUTCFG37_TIMER81 = 17
, TIMER_OUTCFG9_OUTCFG37_TIMER90 = 18
, TIMER_OUTCFG9_OUTCFG37_TIMER91 = 19
,
TIMER_OUTCFG9_OUTCFG37_TIMER100 = 20
, TIMER_OUTCFG9_OUTCFG37_TIMER101 = 21
, TIMER_OUTCFG9_OUTCFG37_TIMER110 = 22
, TIMER_OUTCFG9_OUTCFG37_TIMER111 = 23
,
TIMER_OUTCFG9_OUTCFG37_TIMER120 = 24
, TIMER_OUTCFG9_OUTCFG37_TIMER121 = 25
, TIMER_OUTCFG9_OUTCFG37_TIMER130 = 26
, TIMER_OUTCFG9_OUTCFG37_TIMER131 = 27
,
TIMER_OUTCFG9_OUTCFG37_TIMER140 = 28
, TIMER_OUTCFG9_OUTCFG37_TIMER141 = 29
, TIMER_OUTCFG9_OUTCFG37_TIMER150 = 30
, TIMER_OUTCFG9_OUTCFG37_TIMER151 = 31
,
TIMER_OUTCFG9_OUTCFG37_STIMER0 = 32
, TIMER_OUTCFG9_OUTCFG37_STIMER1 = 33
, TIMER_OUTCFG9_OUTCFG37_STIMER2 = 34
, TIMER_OUTCFG9_OUTCFG37_STIMER3 = 35
,
TIMER_OUTCFG9_OUTCFG37_STIMER4 = 36
, TIMER_OUTCFG9_OUTCFG37_STIMER5 = 37
, TIMER_OUTCFG9_OUTCFG37_STIMER6 = 38
, TIMER_OUTCFG9_OUTCFG37_STIMER7 = 39
,
TIMER_OUTCFG9_OUTCFG37_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG9_OUTCFG36_Enum {
TIMER_OUTCFG9_OUTCFG36_TIMER00 = 0
, TIMER_OUTCFG9_OUTCFG36_TIMER01 = 1
, TIMER_OUTCFG9_OUTCFG36_TIMER10 = 2
, TIMER_OUTCFG9_OUTCFG36_TIMER11 = 3
,
TIMER_OUTCFG9_OUTCFG36_TIMER20 = 4
, TIMER_OUTCFG9_OUTCFG36_TIMER21 = 5
, TIMER_OUTCFG9_OUTCFG36_TIMER30 = 6
, TIMER_OUTCFG9_OUTCFG36_TIMER31 = 7
,
TIMER_OUTCFG9_OUTCFG36_TIMER40 = 8
, TIMER_OUTCFG9_OUTCFG36_TIMER41 = 9
, TIMER_OUTCFG9_OUTCFG36_TIMER50 = 10
, TIMER_OUTCFG9_OUTCFG36_TIMER51 = 11
,
TIMER_OUTCFG9_OUTCFG36_TIMER60 = 12
, TIMER_OUTCFG9_OUTCFG36_TIMER61 = 13
, TIMER_OUTCFG9_OUTCFG36_TIMER70 = 14
, TIMER_OUTCFG9_OUTCFG36_TIMER71 = 15
,
TIMER_OUTCFG9_OUTCFG36_TIMER80 = 16
, TIMER_OUTCFG9_OUTCFG36_TIMER81 = 17
, TIMER_OUTCFG9_OUTCFG36_TIMER90 = 18
, TIMER_OUTCFG9_OUTCFG36_TIMER91 = 19
,
TIMER_OUTCFG9_OUTCFG36_TIMER100 = 20
, TIMER_OUTCFG9_OUTCFG36_TIMER101 = 21
, TIMER_OUTCFG9_OUTCFG36_TIMER110 = 22
, TIMER_OUTCFG9_OUTCFG36_TIMER111 = 23
,
TIMER_OUTCFG9_OUTCFG36_TIMER120 = 24
, TIMER_OUTCFG9_OUTCFG36_TIMER121 = 25
, TIMER_OUTCFG9_OUTCFG36_TIMER130 = 26
, TIMER_OUTCFG9_OUTCFG36_TIMER131 = 27
,
TIMER_OUTCFG9_OUTCFG36_TIMER140 = 28
, TIMER_OUTCFG9_OUTCFG36_TIMER141 = 29
, TIMER_OUTCFG9_OUTCFG36_TIMER150 = 30
, TIMER_OUTCFG9_OUTCFG36_TIMER151 = 31
,
TIMER_OUTCFG9_OUTCFG36_STIMER0 = 32
, TIMER_OUTCFG9_OUTCFG36_STIMER1 = 33
, TIMER_OUTCFG9_OUTCFG36_STIMER2 = 34
, TIMER_OUTCFG9_OUTCFG36_STIMER3 = 35
,
TIMER_OUTCFG9_OUTCFG36_STIMER4 = 36
, TIMER_OUTCFG9_OUTCFG36_STIMER5 = 37
, TIMER_OUTCFG9_OUTCFG36_STIMER6 = 38
, TIMER_OUTCFG9_OUTCFG36_STIMER7 = 39
,
TIMER_OUTCFG9_OUTCFG36_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG10_OUTCFG43_Enum {
TIMER_OUTCFG10_OUTCFG43_TIMER00 = 0
, TIMER_OUTCFG10_OUTCFG43_TIMER01 = 1
, TIMER_OUTCFG10_OUTCFG43_TIMER10 = 2
, TIMER_OUTCFG10_OUTCFG43_TIMER11 = 3
,
TIMER_OUTCFG10_OUTCFG43_TIMER20 = 4
, TIMER_OUTCFG10_OUTCFG43_TIMER21 = 5
, TIMER_OUTCFG10_OUTCFG43_TIMER30 = 6
, TIMER_OUTCFG10_OUTCFG43_TIMER31 = 7
,
TIMER_OUTCFG10_OUTCFG43_TIMER40 = 8
, TIMER_OUTCFG10_OUTCFG43_TIMER41 = 9
, TIMER_OUTCFG10_OUTCFG43_TIMER50 = 10
, TIMER_OUTCFG10_OUTCFG43_TIMER51 = 11
,
TIMER_OUTCFG10_OUTCFG43_TIMER60 = 12
, TIMER_OUTCFG10_OUTCFG43_TIMER61 = 13
, TIMER_OUTCFG10_OUTCFG43_TIMER70 = 14
, TIMER_OUTCFG10_OUTCFG43_TIMER71 = 15
,
TIMER_OUTCFG10_OUTCFG43_TIMER80 = 16
, TIMER_OUTCFG10_OUTCFG43_TIMER81 = 17
, TIMER_OUTCFG10_OUTCFG43_TIMER90 = 18
, TIMER_OUTCFG10_OUTCFG43_TIMER91 = 19
,
TIMER_OUTCFG10_OUTCFG43_TIMER100 = 20
, TIMER_OUTCFG10_OUTCFG43_TIMER101 = 21
, TIMER_OUTCFG10_OUTCFG43_TIMER110 = 22
, TIMER_OUTCFG10_OUTCFG43_TIMER111 = 23
,
TIMER_OUTCFG10_OUTCFG43_TIMER120 = 24
, TIMER_OUTCFG10_OUTCFG43_TIMER121 = 25
, TIMER_OUTCFG10_OUTCFG43_TIMER130 = 26
, TIMER_OUTCFG10_OUTCFG43_TIMER131 = 27
,
TIMER_OUTCFG10_OUTCFG43_TIMER140 = 28
, TIMER_OUTCFG10_OUTCFG43_TIMER141 = 29
, TIMER_OUTCFG10_OUTCFG43_TIMER150 = 30
, TIMER_OUTCFG10_OUTCFG43_TIMER151 = 31
,
TIMER_OUTCFG10_OUTCFG43_STIMER0 = 32
, TIMER_OUTCFG10_OUTCFG43_STIMER1 = 33
, TIMER_OUTCFG10_OUTCFG43_STIMER2 = 34
, TIMER_OUTCFG10_OUTCFG43_STIMER3 = 35
,
TIMER_OUTCFG10_OUTCFG43_STIMER4 = 36
, TIMER_OUTCFG10_OUTCFG43_STIMER5 = 37
, TIMER_OUTCFG10_OUTCFG43_STIMER6 = 38
, TIMER_OUTCFG10_OUTCFG43_STIMER7 = 39
,
TIMER_OUTCFG10_OUTCFG43_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG10_OUTCFG42_Enum {
TIMER_OUTCFG10_OUTCFG42_TIMER00 = 0
, TIMER_OUTCFG10_OUTCFG42_TIMER01 = 1
, TIMER_OUTCFG10_OUTCFG42_TIMER10 = 2
, TIMER_OUTCFG10_OUTCFG42_TIMER11 = 3
,
TIMER_OUTCFG10_OUTCFG42_TIMER20 = 4
, TIMER_OUTCFG10_OUTCFG42_TIMER21 = 5
, TIMER_OUTCFG10_OUTCFG42_TIMER30 = 6
, TIMER_OUTCFG10_OUTCFG42_TIMER31 = 7
,
TIMER_OUTCFG10_OUTCFG42_TIMER40 = 8
, TIMER_OUTCFG10_OUTCFG42_TIMER41 = 9
, TIMER_OUTCFG10_OUTCFG42_TIMER50 = 10
, TIMER_OUTCFG10_OUTCFG42_TIMER51 = 11
,
TIMER_OUTCFG10_OUTCFG42_TIMER60 = 12
, TIMER_OUTCFG10_OUTCFG42_TIMER61 = 13
, TIMER_OUTCFG10_OUTCFG42_TIMER70 = 14
, TIMER_OUTCFG10_OUTCFG42_TIMER71 = 15
,
TIMER_OUTCFG10_OUTCFG42_TIMER80 = 16
, TIMER_OUTCFG10_OUTCFG42_TIMER81 = 17
, TIMER_OUTCFG10_OUTCFG42_TIMER90 = 18
, TIMER_OUTCFG10_OUTCFG42_TIMER91 = 19
,
TIMER_OUTCFG10_OUTCFG42_TIMER100 = 20
, TIMER_OUTCFG10_OUTCFG42_TIMER101 = 21
, TIMER_OUTCFG10_OUTCFG42_TIMER110 = 22
, TIMER_OUTCFG10_OUTCFG42_TIMER111 = 23
,
TIMER_OUTCFG10_OUTCFG42_TIMER120 = 24
, TIMER_OUTCFG10_OUTCFG42_TIMER121 = 25
, TIMER_OUTCFG10_OUTCFG42_TIMER130 = 26
, TIMER_OUTCFG10_OUTCFG42_TIMER131 = 27
,
TIMER_OUTCFG10_OUTCFG42_TIMER140 = 28
, TIMER_OUTCFG10_OUTCFG42_TIMER141 = 29
, TIMER_OUTCFG10_OUTCFG42_TIMER150 = 30
, TIMER_OUTCFG10_OUTCFG42_TIMER151 = 31
,
TIMER_OUTCFG10_OUTCFG42_STIMER0 = 32
, TIMER_OUTCFG10_OUTCFG42_STIMER1 = 33
, TIMER_OUTCFG10_OUTCFG42_STIMER2 = 34
, TIMER_OUTCFG10_OUTCFG42_STIMER3 = 35
,
TIMER_OUTCFG10_OUTCFG42_STIMER4 = 36
, TIMER_OUTCFG10_OUTCFG42_STIMER5 = 37
, TIMER_OUTCFG10_OUTCFG42_STIMER6 = 38
, TIMER_OUTCFG10_OUTCFG42_STIMER7 = 39
,
TIMER_OUTCFG10_OUTCFG42_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG10_OUTCFG41_Enum {
TIMER_OUTCFG10_OUTCFG41_TIMER00 = 0
, TIMER_OUTCFG10_OUTCFG41_TIMER01 = 1
, TIMER_OUTCFG10_OUTCFG41_TIMER10 = 2
, TIMER_OUTCFG10_OUTCFG41_TIMER11 = 3
,
TIMER_OUTCFG10_OUTCFG41_TIMER20 = 4
, TIMER_OUTCFG10_OUTCFG41_TIMER21 = 5
, TIMER_OUTCFG10_OUTCFG41_TIMER30 = 6
, TIMER_OUTCFG10_OUTCFG41_TIMER31 = 7
,
TIMER_OUTCFG10_OUTCFG41_TIMER40 = 8
, TIMER_OUTCFG10_OUTCFG41_TIMER41 = 9
, TIMER_OUTCFG10_OUTCFG41_TIMER50 = 10
, TIMER_OUTCFG10_OUTCFG41_TIMER51 = 11
,
TIMER_OUTCFG10_OUTCFG41_TIMER60 = 12
, TIMER_OUTCFG10_OUTCFG41_TIMER61 = 13
, TIMER_OUTCFG10_OUTCFG41_TIMER70 = 14
, TIMER_OUTCFG10_OUTCFG41_TIMER71 = 15
,
TIMER_OUTCFG10_OUTCFG41_TIMER80 = 16
, TIMER_OUTCFG10_OUTCFG41_TIMER81 = 17
, TIMER_OUTCFG10_OUTCFG41_TIMER90 = 18
, TIMER_OUTCFG10_OUTCFG41_TIMER91 = 19
,
TIMER_OUTCFG10_OUTCFG41_TIMER100 = 20
, TIMER_OUTCFG10_OUTCFG41_TIMER101 = 21
, TIMER_OUTCFG10_OUTCFG41_TIMER110 = 22
, TIMER_OUTCFG10_OUTCFG41_TIMER111 = 23
,
TIMER_OUTCFG10_OUTCFG41_TIMER120 = 24
, TIMER_OUTCFG10_OUTCFG41_TIMER121 = 25
, TIMER_OUTCFG10_OUTCFG41_TIMER130 = 26
, TIMER_OUTCFG10_OUTCFG41_TIMER131 = 27
,
TIMER_OUTCFG10_OUTCFG41_TIMER140 = 28
, TIMER_OUTCFG10_OUTCFG41_TIMER141 = 29
, TIMER_OUTCFG10_OUTCFG41_TIMER150 = 30
, TIMER_OUTCFG10_OUTCFG41_TIMER151 = 31
,
TIMER_OUTCFG10_OUTCFG41_STIMER0 = 32
, TIMER_OUTCFG10_OUTCFG41_STIMER1 = 33
, TIMER_OUTCFG10_OUTCFG41_STIMER2 = 34
, TIMER_OUTCFG10_OUTCFG41_STIMER3 = 35
,
TIMER_OUTCFG10_OUTCFG41_STIMER4 = 36
, TIMER_OUTCFG10_OUTCFG41_STIMER5 = 37
, TIMER_OUTCFG10_OUTCFG41_STIMER6 = 38
, TIMER_OUTCFG10_OUTCFG41_STIMER7 = 39
,
TIMER_OUTCFG10_OUTCFG41_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG10_OUTCFG40_Enum {
TIMER_OUTCFG10_OUTCFG40_TIMER00 = 0
, TIMER_OUTCFG10_OUTCFG40_TIMER01 = 1
, TIMER_OUTCFG10_OUTCFG40_TIMER10 = 2
, TIMER_OUTCFG10_OUTCFG40_TIMER11 = 3
,
TIMER_OUTCFG10_OUTCFG40_TIMER20 = 4
, TIMER_OUTCFG10_OUTCFG40_TIMER21 = 5
, TIMER_OUTCFG10_OUTCFG40_TIMER30 = 6
, TIMER_OUTCFG10_OUTCFG40_TIMER31 = 7
,
TIMER_OUTCFG10_OUTCFG40_TIMER40 = 8
, TIMER_OUTCFG10_OUTCFG40_TIMER41 = 9
, TIMER_OUTCFG10_OUTCFG40_TIMER50 = 10
, TIMER_OUTCFG10_OUTCFG40_TIMER51 = 11
,
TIMER_OUTCFG10_OUTCFG40_TIMER60 = 12
, TIMER_OUTCFG10_OUTCFG40_TIMER61 = 13
, TIMER_OUTCFG10_OUTCFG40_TIMER70 = 14
, TIMER_OUTCFG10_OUTCFG40_TIMER71 = 15
,
TIMER_OUTCFG10_OUTCFG40_TIMER80 = 16
, TIMER_OUTCFG10_OUTCFG40_TIMER81 = 17
, TIMER_OUTCFG10_OUTCFG40_TIMER90 = 18
, TIMER_OUTCFG10_OUTCFG40_TIMER91 = 19
,
TIMER_OUTCFG10_OUTCFG40_TIMER100 = 20
, TIMER_OUTCFG10_OUTCFG40_TIMER101 = 21
, TIMER_OUTCFG10_OUTCFG40_TIMER110 = 22
, TIMER_OUTCFG10_OUTCFG40_TIMER111 = 23
,
TIMER_OUTCFG10_OUTCFG40_TIMER120 = 24
, TIMER_OUTCFG10_OUTCFG40_TIMER121 = 25
, TIMER_OUTCFG10_OUTCFG40_TIMER130 = 26
, TIMER_OUTCFG10_OUTCFG40_TIMER131 = 27
,
TIMER_OUTCFG10_OUTCFG40_TIMER140 = 28
, TIMER_OUTCFG10_OUTCFG40_TIMER141 = 29
, TIMER_OUTCFG10_OUTCFG40_TIMER150 = 30
, TIMER_OUTCFG10_OUTCFG40_TIMER151 = 31
,
TIMER_OUTCFG10_OUTCFG40_STIMER0 = 32
, TIMER_OUTCFG10_OUTCFG40_STIMER1 = 33
, TIMER_OUTCFG10_OUTCFG40_STIMER2 = 34
, TIMER_OUTCFG10_OUTCFG40_STIMER3 = 35
,
TIMER_OUTCFG10_OUTCFG40_STIMER4 = 36
, TIMER_OUTCFG10_OUTCFG40_STIMER5 = 37
, TIMER_OUTCFG10_OUTCFG40_STIMER6 = 38
, TIMER_OUTCFG10_OUTCFG40_STIMER7 = 39
,
TIMER_OUTCFG10_OUTCFG40_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG11_OUTCFG47_Enum {
TIMER_OUTCFG11_OUTCFG47_TIMER00 = 0
, TIMER_OUTCFG11_OUTCFG47_TIMER01 = 1
, TIMER_OUTCFG11_OUTCFG47_TIMER10 = 2
, TIMER_OUTCFG11_OUTCFG47_TIMER11 = 3
,
TIMER_OUTCFG11_OUTCFG47_TIMER20 = 4
, TIMER_OUTCFG11_OUTCFG47_TIMER21 = 5
, TIMER_OUTCFG11_OUTCFG47_TIMER30 = 6
, TIMER_OUTCFG11_OUTCFG47_TIMER31 = 7
,
TIMER_OUTCFG11_OUTCFG47_TIMER40 = 8
, TIMER_OUTCFG11_OUTCFG47_TIMER41 = 9
, TIMER_OUTCFG11_OUTCFG47_TIMER50 = 10
, TIMER_OUTCFG11_OUTCFG47_TIMER51 = 11
,
TIMER_OUTCFG11_OUTCFG47_TIMER60 = 12
, TIMER_OUTCFG11_OUTCFG47_TIMER61 = 13
, TIMER_OUTCFG11_OUTCFG47_TIMER70 = 14
, TIMER_OUTCFG11_OUTCFG47_TIMER71 = 15
,
TIMER_OUTCFG11_OUTCFG47_TIMER80 = 16
, TIMER_OUTCFG11_OUTCFG47_TIMER81 = 17
, TIMER_OUTCFG11_OUTCFG47_TIMER90 = 18
, TIMER_OUTCFG11_OUTCFG47_TIMER91 = 19
,
TIMER_OUTCFG11_OUTCFG47_TIMER100 = 20
, TIMER_OUTCFG11_OUTCFG47_TIMER101 = 21
, TIMER_OUTCFG11_OUTCFG47_TIMER110 = 22
, TIMER_OUTCFG11_OUTCFG47_TIMER111 = 23
,
TIMER_OUTCFG11_OUTCFG47_TIMER120 = 24
, TIMER_OUTCFG11_OUTCFG47_TIMER121 = 25
, TIMER_OUTCFG11_OUTCFG47_TIMER130 = 26
, TIMER_OUTCFG11_OUTCFG47_TIMER131 = 27
,
TIMER_OUTCFG11_OUTCFG47_TIMER140 = 28
, TIMER_OUTCFG11_OUTCFG47_TIMER141 = 29
, TIMER_OUTCFG11_OUTCFG47_TIMER150 = 30
, TIMER_OUTCFG11_OUTCFG47_TIMER151 = 31
,
TIMER_OUTCFG11_OUTCFG47_STIMER0 = 32
, TIMER_OUTCFG11_OUTCFG47_STIMER1 = 33
, TIMER_OUTCFG11_OUTCFG47_STIMER2 = 34
, TIMER_OUTCFG11_OUTCFG47_STIMER3 = 35
,
TIMER_OUTCFG11_OUTCFG47_STIMER4 = 36
, TIMER_OUTCFG11_OUTCFG47_STIMER5 = 37
, TIMER_OUTCFG11_OUTCFG47_STIMER6 = 38
, TIMER_OUTCFG11_OUTCFG47_STIMER7 = 39
,
TIMER_OUTCFG11_OUTCFG47_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG11_OUTCFG46_Enum {
TIMER_OUTCFG11_OUTCFG46_TIMER00 = 0
, TIMER_OUTCFG11_OUTCFG46_TIMER01 = 1
, TIMER_OUTCFG11_OUTCFG46_TIMER10 = 2
, TIMER_OUTCFG11_OUTCFG46_TIMER11 = 3
,
TIMER_OUTCFG11_OUTCFG46_TIMER20 = 4
, TIMER_OUTCFG11_OUTCFG46_TIMER21 = 5
, TIMER_OUTCFG11_OUTCFG46_TIMER30 = 6
, TIMER_OUTCFG11_OUTCFG46_TIMER31 = 7
,
TIMER_OUTCFG11_OUTCFG46_TIMER40 = 8
, TIMER_OUTCFG11_OUTCFG46_TIMER41 = 9
, TIMER_OUTCFG11_OUTCFG46_TIMER50 = 10
, TIMER_OUTCFG11_OUTCFG46_TIMER51 = 11
,
TIMER_OUTCFG11_OUTCFG46_TIMER60 = 12
, TIMER_OUTCFG11_OUTCFG46_TIMER61 = 13
, TIMER_OUTCFG11_OUTCFG46_TIMER70 = 14
, TIMER_OUTCFG11_OUTCFG46_TIMER71 = 15
,
TIMER_OUTCFG11_OUTCFG46_TIMER80 = 16
, TIMER_OUTCFG11_OUTCFG46_TIMER81 = 17
, TIMER_OUTCFG11_OUTCFG46_TIMER90 = 18
, TIMER_OUTCFG11_OUTCFG46_TIMER91 = 19
,
TIMER_OUTCFG11_OUTCFG46_TIMER100 = 20
, TIMER_OUTCFG11_OUTCFG46_TIMER101 = 21
, TIMER_OUTCFG11_OUTCFG46_TIMER110 = 22
, TIMER_OUTCFG11_OUTCFG46_TIMER111 = 23
,
TIMER_OUTCFG11_OUTCFG46_TIMER120 = 24
, TIMER_OUTCFG11_OUTCFG46_TIMER121 = 25
, TIMER_OUTCFG11_OUTCFG46_TIMER130 = 26
, TIMER_OUTCFG11_OUTCFG46_TIMER131 = 27
,
TIMER_OUTCFG11_OUTCFG46_TIMER140 = 28
, TIMER_OUTCFG11_OUTCFG46_TIMER141 = 29
, TIMER_OUTCFG11_OUTCFG46_TIMER150 = 30
, TIMER_OUTCFG11_OUTCFG46_TIMER151 = 31
,
TIMER_OUTCFG11_OUTCFG46_STIMER0 = 32
, TIMER_OUTCFG11_OUTCFG46_STIMER1 = 33
, TIMER_OUTCFG11_OUTCFG46_STIMER2 = 34
, TIMER_OUTCFG11_OUTCFG46_STIMER3 = 35
,
TIMER_OUTCFG11_OUTCFG46_STIMER4 = 36
, TIMER_OUTCFG11_OUTCFG46_STIMER5 = 37
, TIMER_OUTCFG11_OUTCFG46_STIMER6 = 38
, TIMER_OUTCFG11_OUTCFG46_STIMER7 = 39
,
TIMER_OUTCFG11_OUTCFG46_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG11_OUTCFG45_Enum {
TIMER_OUTCFG11_OUTCFG45_TIMER00 = 0
, TIMER_OUTCFG11_OUTCFG45_TIMER01 = 1
, TIMER_OUTCFG11_OUTCFG45_TIMER10 = 2
, TIMER_OUTCFG11_OUTCFG45_TIMER11 = 3
,
TIMER_OUTCFG11_OUTCFG45_TIMER20 = 4
, TIMER_OUTCFG11_OUTCFG45_TIMER21 = 5
, TIMER_OUTCFG11_OUTCFG45_TIMER30 = 6
, TIMER_OUTCFG11_OUTCFG45_TIMER31 = 7
,
TIMER_OUTCFG11_OUTCFG45_TIMER40 = 8
, TIMER_OUTCFG11_OUTCFG45_TIMER41 = 9
, TIMER_OUTCFG11_OUTCFG45_TIMER50 = 10
, TIMER_OUTCFG11_OUTCFG45_TIMER51 = 11
,
TIMER_OUTCFG11_OUTCFG45_TIMER60 = 12
, TIMER_OUTCFG11_OUTCFG45_TIMER61 = 13
, TIMER_OUTCFG11_OUTCFG45_TIMER70 = 14
, TIMER_OUTCFG11_OUTCFG45_TIMER71 = 15
,
TIMER_OUTCFG11_OUTCFG45_TIMER80 = 16
, TIMER_OUTCFG11_OUTCFG45_TIMER81 = 17
, TIMER_OUTCFG11_OUTCFG45_TIMER90 = 18
, TIMER_OUTCFG11_OUTCFG45_TIMER91 = 19
,
TIMER_OUTCFG11_OUTCFG45_TIMER100 = 20
, TIMER_OUTCFG11_OUTCFG45_TIMER101 = 21
, TIMER_OUTCFG11_OUTCFG45_TIMER110 = 22
, TIMER_OUTCFG11_OUTCFG45_TIMER111 = 23
,
TIMER_OUTCFG11_OUTCFG45_TIMER120 = 24
, TIMER_OUTCFG11_OUTCFG45_TIMER121 = 25
, TIMER_OUTCFG11_OUTCFG45_TIMER130 = 26
, TIMER_OUTCFG11_OUTCFG45_TIMER131 = 27
,
TIMER_OUTCFG11_OUTCFG45_TIMER140 = 28
, TIMER_OUTCFG11_OUTCFG45_TIMER141 = 29
, TIMER_OUTCFG11_OUTCFG45_TIMER150 = 30
, TIMER_OUTCFG11_OUTCFG45_TIMER151 = 31
,
TIMER_OUTCFG11_OUTCFG45_STIMER0 = 32
, TIMER_OUTCFG11_OUTCFG45_STIMER1 = 33
, TIMER_OUTCFG11_OUTCFG45_STIMER2 = 34
, TIMER_OUTCFG11_OUTCFG45_STIMER3 = 35
,
TIMER_OUTCFG11_OUTCFG45_STIMER4 = 36
, TIMER_OUTCFG11_OUTCFG45_STIMER5 = 37
, TIMER_OUTCFG11_OUTCFG45_STIMER6 = 38
, TIMER_OUTCFG11_OUTCFG45_STIMER7 = 39
,
TIMER_OUTCFG11_OUTCFG45_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG11_OUTCFG44_Enum {
TIMER_OUTCFG11_OUTCFG44_TIMER00 = 0
, TIMER_OUTCFG11_OUTCFG44_TIMER01 = 1
, TIMER_OUTCFG11_OUTCFG44_TIMER10 = 2
, TIMER_OUTCFG11_OUTCFG44_TIMER11 = 3
,
TIMER_OUTCFG11_OUTCFG44_TIMER20 = 4
, TIMER_OUTCFG11_OUTCFG44_TIMER21 = 5
, TIMER_OUTCFG11_OUTCFG44_TIMER30 = 6
, TIMER_OUTCFG11_OUTCFG44_TIMER31 = 7
,
TIMER_OUTCFG11_OUTCFG44_TIMER40 = 8
, TIMER_OUTCFG11_OUTCFG44_TIMER41 = 9
, TIMER_OUTCFG11_OUTCFG44_TIMER50 = 10
, TIMER_OUTCFG11_OUTCFG44_TIMER51 = 11
,
TIMER_OUTCFG11_OUTCFG44_TIMER60 = 12
, TIMER_OUTCFG11_OUTCFG44_TIMER61 = 13
, TIMER_OUTCFG11_OUTCFG44_TIMER70 = 14
, TIMER_OUTCFG11_OUTCFG44_TIMER71 = 15
,
TIMER_OUTCFG11_OUTCFG44_TIMER80 = 16
, TIMER_OUTCFG11_OUTCFG44_TIMER81 = 17
, TIMER_OUTCFG11_OUTCFG44_TIMER90 = 18
, TIMER_OUTCFG11_OUTCFG44_TIMER91 = 19
,
TIMER_OUTCFG11_OUTCFG44_TIMER100 = 20
, TIMER_OUTCFG11_OUTCFG44_TIMER101 = 21
, TIMER_OUTCFG11_OUTCFG44_TIMER110 = 22
, TIMER_OUTCFG11_OUTCFG44_TIMER111 = 23
,
TIMER_OUTCFG11_OUTCFG44_TIMER120 = 24
, TIMER_OUTCFG11_OUTCFG44_TIMER121 = 25
, TIMER_OUTCFG11_OUTCFG44_TIMER130 = 26
, TIMER_OUTCFG11_OUTCFG44_TIMER131 = 27
,
TIMER_OUTCFG11_OUTCFG44_TIMER140 = 28
, TIMER_OUTCFG11_OUTCFG44_TIMER141 = 29
, TIMER_OUTCFG11_OUTCFG44_TIMER150 = 30
, TIMER_OUTCFG11_OUTCFG44_TIMER151 = 31
,
TIMER_OUTCFG11_OUTCFG44_STIMER0 = 32
, TIMER_OUTCFG11_OUTCFG44_STIMER1 = 33
, TIMER_OUTCFG11_OUTCFG44_STIMER2 = 34
, TIMER_OUTCFG11_OUTCFG44_STIMER3 = 35
,
TIMER_OUTCFG11_OUTCFG44_STIMER4 = 36
, TIMER_OUTCFG11_OUTCFG44_STIMER5 = 37
, TIMER_OUTCFG11_OUTCFG44_STIMER6 = 38
, TIMER_OUTCFG11_OUTCFG44_STIMER7 = 39
,
TIMER_OUTCFG11_OUTCFG44_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG12_OUTCFG51_Enum {
TIMER_OUTCFG12_OUTCFG51_TIMER00 = 0
, TIMER_OUTCFG12_OUTCFG51_TIMER01 = 1
, TIMER_OUTCFG12_OUTCFG51_TIMER10 = 2
, TIMER_OUTCFG12_OUTCFG51_TIMER11 = 3
,
TIMER_OUTCFG12_OUTCFG51_TIMER20 = 4
, TIMER_OUTCFG12_OUTCFG51_TIMER21 = 5
, TIMER_OUTCFG12_OUTCFG51_TIMER30 = 6
, TIMER_OUTCFG12_OUTCFG51_TIMER31 = 7
,
TIMER_OUTCFG12_OUTCFG51_TIMER40 = 8
, TIMER_OUTCFG12_OUTCFG51_TIMER41 = 9
, TIMER_OUTCFG12_OUTCFG51_TIMER50 = 10
, TIMER_OUTCFG12_OUTCFG51_TIMER51 = 11
,
TIMER_OUTCFG12_OUTCFG51_TIMER60 = 12
, TIMER_OUTCFG12_OUTCFG51_TIMER61 = 13
, TIMER_OUTCFG12_OUTCFG51_TIMER70 = 14
, TIMER_OUTCFG12_OUTCFG51_TIMER71 = 15
,
TIMER_OUTCFG12_OUTCFG51_TIMER80 = 16
, TIMER_OUTCFG12_OUTCFG51_TIMER81 = 17
, TIMER_OUTCFG12_OUTCFG51_TIMER90 = 18
, TIMER_OUTCFG12_OUTCFG51_TIMER91 = 19
,
TIMER_OUTCFG12_OUTCFG51_TIMER100 = 20
, TIMER_OUTCFG12_OUTCFG51_TIMER101 = 21
, TIMER_OUTCFG12_OUTCFG51_TIMER110 = 22
, TIMER_OUTCFG12_OUTCFG51_TIMER111 = 23
,
TIMER_OUTCFG12_OUTCFG51_TIMER120 = 24
, TIMER_OUTCFG12_OUTCFG51_TIMER121 = 25
, TIMER_OUTCFG12_OUTCFG51_TIMER130 = 26
, TIMER_OUTCFG12_OUTCFG51_TIMER131 = 27
,
TIMER_OUTCFG12_OUTCFG51_TIMER140 = 28
, TIMER_OUTCFG12_OUTCFG51_TIMER141 = 29
, TIMER_OUTCFG12_OUTCFG51_TIMER150 = 30
, TIMER_OUTCFG12_OUTCFG51_TIMER151 = 31
,
TIMER_OUTCFG12_OUTCFG51_STIMER0 = 32
, TIMER_OUTCFG12_OUTCFG51_STIMER1 = 33
, TIMER_OUTCFG12_OUTCFG51_STIMER2 = 34
, TIMER_OUTCFG12_OUTCFG51_STIMER3 = 35
,
TIMER_OUTCFG12_OUTCFG51_STIMER4 = 36
, TIMER_OUTCFG12_OUTCFG51_STIMER5 = 37
, TIMER_OUTCFG12_OUTCFG51_STIMER6 = 38
, TIMER_OUTCFG12_OUTCFG51_STIMER7 = 39
,
TIMER_OUTCFG12_OUTCFG51_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG12_OUTCFG50_Enum {
TIMER_OUTCFG12_OUTCFG50_TIMER00 = 0
, TIMER_OUTCFG12_OUTCFG50_TIMER01 = 1
, TIMER_OUTCFG12_OUTCFG50_TIMER10 = 2
, TIMER_OUTCFG12_OUTCFG50_TIMER11 = 3
,
TIMER_OUTCFG12_OUTCFG50_TIMER20 = 4
, TIMER_OUTCFG12_OUTCFG50_TIMER21 = 5
, TIMER_OUTCFG12_OUTCFG50_TIMER30 = 6
, TIMER_OUTCFG12_OUTCFG50_TIMER31 = 7
,
TIMER_OUTCFG12_OUTCFG50_TIMER40 = 8
, TIMER_OUTCFG12_OUTCFG50_TIMER41 = 9
, TIMER_OUTCFG12_OUTCFG50_TIMER50 = 10
, TIMER_OUTCFG12_OUTCFG50_TIMER51 = 11
,
TIMER_OUTCFG12_OUTCFG50_TIMER60 = 12
, TIMER_OUTCFG12_OUTCFG50_TIMER61 = 13
, TIMER_OUTCFG12_OUTCFG50_TIMER70 = 14
, TIMER_OUTCFG12_OUTCFG50_TIMER71 = 15
,
TIMER_OUTCFG12_OUTCFG50_TIMER80 = 16
, TIMER_OUTCFG12_OUTCFG50_TIMER81 = 17
, TIMER_OUTCFG12_OUTCFG50_TIMER90 = 18
, TIMER_OUTCFG12_OUTCFG50_TIMER91 = 19
,
TIMER_OUTCFG12_OUTCFG50_TIMER100 = 20
, TIMER_OUTCFG12_OUTCFG50_TIMER101 = 21
, TIMER_OUTCFG12_OUTCFG50_TIMER110 = 22
, TIMER_OUTCFG12_OUTCFG50_TIMER111 = 23
,
TIMER_OUTCFG12_OUTCFG50_TIMER120 = 24
, TIMER_OUTCFG12_OUTCFG50_TIMER121 = 25
, TIMER_OUTCFG12_OUTCFG50_TIMER130 = 26
, TIMER_OUTCFG12_OUTCFG50_TIMER131 = 27
,
TIMER_OUTCFG12_OUTCFG50_TIMER140 = 28
, TIMER_OUTCFG12_OUTCFG50_TIMER141 = 29
, TIMER_OUTCFG12_OUTCFG50_TIMER150 = 30
, TIMER_OUTCFG12_OUTCFG50_TIMER151 = 31
,
TIMER_OUTCFG12_OUTCFG50_STIMER0 = 32
, TIMER_OUTCFG12_OUTCFG50_STIMER1 = 33
, TIMER_OUTCFG12_OUTCFG50_STIMER2 = 34
, TIMER_OUTCFG12_OUTCFG50_STIMER3 = 35
,
TIMER_OUTCFG12_OUTCFG50_STIMER4 = 36
, TIMER_OUTCFG12_OUTCFG50_STIMER5 = 37
, TIMER_OUTCFG12_OUTCFG50_STIMER6 = 38
, TIMER_OUTCFG12_OUTCFG50_STIMER7 = 39
,
TIMER_OUTCFG12_OUTCFG50_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG12_OUTCFG49_Enum {
TIMER_OUTCFG12_OUTCFG49_TIMER00 = 0
, TIMER_OUTCFG12_OUTCFG49_TIMER01 = 1
, TIMER_OUTCFG12_OUTCFG49_TIMER10 = 2
, TIMER_OUTCFG12_OUTCFG49_TIMER11 = 3
,
TIMER_OUTCFG12_OUTCFG49_TIMER20 = 4
, TIMER_OUTCFG12_OUTCFG49_TIMER21 = 5
, TIMER_OUTCFG12_OUTCFG49_TIMER30 = 6
, TIMER_OUTCFG12_OUTCFG49_TIMER31 = 7
,
TIMER_OUTCFG12_OUTCFG49_TIMER40 = 8
, TIMER_OUTCFG12_OUTCFG49_TIMER41 = 9
, TIMER_OUTCFG12_OUTCFG49_TIMER50 = 10
, TIMER_OUTCFG12_OUTCFG49_TIMER51 = 11
,
TIMER_OUTCFG12_OUTCFG49_TIMER60 = 12
, TIMER_OUTCFG12_OUTCFG49_TIMER61 = 13
, TIMER_OUTCFG12_OUTCFG49_TIMER70 = 14
, TIMER_OUTCFG12_OUTCFG49_TIMER71 = 15
,
TIMER_OUTCFG12_OUTCFG49_TIMER80 = 16
, TIMER_OUTCFG12_OUTCFG49_TIMER81 = 17
, TIMER_OUTCFG12_OUTCFG49_TIMER90 = 18
, TIMER_OUTCFG12_OUTCFG49_TIMER91 = 19
,
TIMER_OUTCFG12_OUTCFG49_TIMER100 = 20
, TIMER_OUTCFG12_OUTCFG49_TIMER101 = 21
, TIMER_OUTCFG12_OUTCFG49_TIMER110 = 22
, TIMER_OUTCFG12_OUTCFG49_TIMER111 = 23
,
TIMER_OUTCFG12_OUTCFG49_TIMER120 = 24
, TIMER_OUTCFG12_OUTCFG49_TIMER121 = 25
, TIMER_OUTCFG12_OUTCFG49_TIMER130 = 26
, TIMER_OUTCFG12_OUTCFG49_TIMER131 = 27
,
TIMER_OUTCFG12_OUTCFG49_TIMER140 = 28
, TIMER_OUTCFG12_OUTCFG49_TIMER141 = 29
, TIMER_OUTCFG12_OUTCFG49_TIMER150 = 30
, TIMER_OUTCFG12_OUTCFG49_TIMER151 = 31
,
TIMER_OUTCFG12_OUTCFG49_STIMER0 = 32
, TIMER_OUTCFG12_OUTCFG49_STIMER1 = 33
, TIMER_OUTCFG12_OUTCFG49_STIMER2 = 34
, TIMER_OUTCFG12_OUTCFG49_STIMER3 = 35
,
TIMER_OUTCFG12_OUTCFG49_STIMER4 = 36
, TIMER_OUTCFG12_OUTCFG49_STIMER5 = 37
, TIMER_OUTCFG12_OUTCFG49_STIMER6 = 38
, TIMER_OUTCFG12_OUTCFG49_STIMER7 = 39
,
TIMER_OUTCFG12_OUTCFG49_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG12_OUTCFG48_Enum {
TIMER_OUTCFG12_OUTCFG48_TIMER00 = 0
, TIMER_OUTCFG12_OUTCFG48_TIMER01 = 1
, TIMER_OUTCFG12_OUTCFG48_TIMER10 = 2
, TIMER_OUTCFG12_OUTCFG48_TIMER11 = 3
,
TIMER_OUTCFG12_OUTCFG48_TIMER20 = 4
, TIMER_OUTCFG12_OUTCFG48_TIMER21 = 5
, TIMER_OUTCFG12_OUTCFG48_TIMER30 = 6
, TIMER_OUTCFG12_OUTCFG48_TIMER31 = 7
,
TIMER_OUTCFG12_OUTCFG48_TIMER40 = 8
, TIMER_OUTCFG12_OUTCFG48_TIMER41 = 9
, TIMER_OUTCFG12_OUTCFG48_TIMER50 = 10
, TIMER_OUTCFG12_OUTCFG48_TIMER51 = 11
,
TIMER_OUTCFG12_OUTCFG48_TIMER60 = 12
, TIMER_OUTCFG12_OUTCFG48_TIMER61 = 13
, TIMER_OUTCFG12_OUTCFG48_TIMER70 = 14
, TIMER_OUTCFG12_OUTCFG48_TIMER71 = 15
,
TIMER_OUTCFG12_OUTCFG48_TIMER80 = 16
, TIMER_OUTCFG12_OUTCFG48_TIMER81 = 17
, TIMER_OUTCFG12_OUTCFG48_TIMER90 = 18
, TIMER_OUTCFG12_OUTCFG48_TIMER91 = 19
,
TIMER_OUTCFG12_OUTCFG48_TIMER100 = 20
, TIMER_OUTCFG12_OUTCFG48_TIMER101 = 21
, TIMER_OUTCFG12_OUTCFG48_TIMER110 = 22
, TIMER_OUTCFG12_OUTCFG48_TIMER111 = 23
,
TIMER_OUTCFG12_OUTCFG48_TIMER120 = 24
, TIMER_OUTCFG12_OUTCFG48_TIMER121 = 25
, TIMER_OUTCFG12_OUTCFG48_TIMER130 = 26
, TIMER_OUTCFG12_OUTCFG48_TIMER131 = 27
,
TIMER_OUTCFG12_OUTCFG48_TIMER140 = 28
, TIMER_OUTCFG12_OUTCFG48_TIMER141 = 29
, TIMER_OUTCFG12_OUTCFG48_TIMER150 = 30
, TIMER_OUTCFG12_OUTCFG48_TIMER151 = 31
,
TIMER_OUTCFG12_OUTCFG48_STIMER0 = 32
, TIMER_OUTCFG12_OUTCFG48_STIMER1 = 33
, TIMER_OUTCFG12_OUTCFG48_STIMER2 = 34
, TIMER_OUTCFG12_OUTCFG48_STIMER3 = 35
,
TIMER_OUTCFG12_OUTCFG48_STIMER4 = 36
, TIMER_OUTCFG12_OUTCFG48_STIMER5 = 37
, TIMER_OUTCFG12_OUTCFG48_STIMER6 = 38
, TIMER_OUTCFG12_OUTCFG48_STIMER7 = 39
,
TIMER_OUTCFG12_OUTCFG48_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG13_OUTCFG55_Enum {
TIMER_OUTCFG13_OUTCFG55_TIMER00 = 0
, TIMER_OUTCFG13_OUTCFG55_TIMER01 = 1
, TIMER_OUTCFG13_OUTCFG55_TIMER10 = 2
, TIMER_OUTCFG13_OUTCFG55_TIMER11 = 3
,
TIMER_OUTCFG13_OUTCFG55_TIMER20 = 4
, TIMER_OUTCFG13_OUTCFG55_TIMER21 = 5
, TIMER_OUTCFG13_OUTCFG55_TIMER30 = 6
, TIMER_OUTCFG13_OUTCFG55_TIMER31 = 7
,
TIMER_OUTCFG13_OUTCFG55_TIMER40 = 8
, TIMER_OUTCFG13_OUTCFG55_TIMER41 = 9
, TIMER_OUTCFG13_OUTCFG55_TIMER50 = 10
, TIMER_OUTCFG13_OUTCFG55_TIMER51 = 11
,
TIMER_OUTCFG13_OUTCFG55_TIMER60 = 12
, TIMER_OUTCFG13_OUTCFG55_TIMER61 = 13
, TIMER_OUTCFG13_OUTCFG55_TIMER70 = 14
, TIMER_OUTCFG13_OUTCFG55_TIMER71 = 15
,
TIMER_OUTCFG13_OUTCFG55_TIMER80 = 16
, TIMER_OUTCFG13_OUTCFG55_TIMER81 = 17
, TIMER_OUTCFG13_OUTCFG55_TIMER90 = 18
, TIMER_OUTCFG13_OUTCFG55_TIMER91 = 19
,
TIMER_OUTCFG13_OUTCFG55_TIMER100 = 20
, TIMER_OUTCFG13_OUTCFG55_TIMER101 = 21
, TIMER_OUTCFG13_OUTCFG55_TIMER110 = 22
, TIMER_OUTCFG13_OUTCFG55_TIMER111 = 23
,
TIMER_OUTCFG13_OUTCFG55_TIMER120 = 24
, TIMER_OUTCFG13_OUTCFG55_TIMER121 = 25
, TIMER_OUTCFG13_OUTCFG55_TIMER130 = 26
, TIMER_OUTCFG13_OUTCFG55_TIMER131 = 27
,
TIMER_OUTCFG13_OUTCFG55_TIMER140 = 28
, TIMER_OUTCFG13_OUTCFG55_TIMER141 = 29
, TIMER_OUTCFG13_OUTCFG55_TIMER150 = 30
, TIMER_OUTCFG13_OUTCFG55_TIMER151 = 31
,
TIMER_OUTCFG13_OUTCFG55_STIMER0 = 32
, TIMER_OUTCFG13_OUTCFG55_STIMER1 = 33
, TIMER_OUTCFG13_OUTCFG55_STIMER2 = 34
, TIMER_OUTCFG13_OUTCFG55_STIMER3 = 35
,
TIMER_OUTCFG13_OUTCFG55_STIMER4 = 36
, TIMER_OUTCFG13_OUTCFG55_STIMER5 = 37
, TIMER_OUTCFG13_OUTCFG55_STIMER6 = 38
, TIMER_OUTCFG13_OUTCFG55_STIMER7 = 39
,
TIMER_OUTCFG13_OUTCFG55_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG13_OUTCFG54_Enum {
TIMER_OUTCFG13_OUTCFG54_TIMER00 = 0
, TIMER_OUTCFG13_OUTCFG54_TIMER01 = 1
, TIMER_OUTCFG13_OUTCFG54_TIMER10 = 2
, TIMER_OUTCFG13_OUTCFG54_TIMER11 = 3
,
TIMER_OUTCFG13_OUTCFG54_TIMER20 = 4
, TIMER_OUTCFG13_OUTCFG54_TIMER21 = 5
, TIMER_OUTCFG13_OUTCFG54_TIMER30 = 6
, TIMER_OUTCFG13_OUTCFG54_TIMER31 = 7
,
TIMER_OUTCFG13_OUTCFG54_TIMER40 = 8
, TIMER_OUTCFG13_OUTCFG54_TIMER41 = 9
, TIMER_OUTCFG13_OUTCFG54_TIMER50 = 10
, TIMER_OUTCFG13_OUTCFG54_TIMER51 = 11
,
TIMER_OUTCFG13_OUTCFG54_TIMER60 = 12
, TIMER_OUTCFG13_OUTCFG54_TIMER61 = 13
, TIMER_OUTCFG13_OUTCFG54_TIMER70 = 14
, TIMER_OUTCFG13_OUTCFG54_TIMER71 = 15
,
TIMER_OUTCFG13_OUTCFG54_TIMER80 = 16
, TIMER_OUTCFG13_OUTCFG54_TIMER81 = 17
, TIMER_OUTCFG13_OUTCFG54_TIMER90 = 18
, TIMER_OUTCFG13_OUTCFG54_TIMER91 = 19
,
TIMER_OUTCFG13_OUTCFG54_TIMER100 = 20
, TIMER_OUTCFG13_OUTCFG54_TIMER101 = 21
, TIMER_OUTCFG13_OUTCFG54_TIMER110 = 22
, TIMER_OUTCFG13_OUTCFG54_TIMER111 = 23
,
TIMER_OUTCFG13_OUTCFG54_TIMER120 = 24
, TIMER_OUTCFG13_OUTCFG54_TIMER121 = 25
, TIMER_OUTCFG13_OUTCFG54_TIMER130 = 26
, TIMER_OUTCFG13_OUTCFG54_TIMER131 = 27
,
TIMER_OUTCFG13_OUTCFG54_TIMER140 = 28
, TIMER_OUTCFG13_OUTCFG54_TIMER141 = 29
, TIMER_OUTCFG13_OUTCFG54_TIMER150 = 30
, TIMER_OUTCFG13_OUTCFG54_TIMER151 = 31
,
TIMER_OUTCFG13_OUTCFG54_STIMER0 = 32
, TIMER_OUTCFG13_OUTCFG54_STIMER1 = 33
, TIMER_OUTCFG13_OUTCFG54_STIMER2 = 34
, TIMER_OUTCFG13_OUTCFG54_STIMER3 = 35
,
TIMER_OUTCFG13_OUTCFG54_STIMER4 = 36
, TIMER_OUTCFG13_OUTCFG54_STIMER5 = 37
, TIMER_OUTCFG13_OUTCFG54_STIMER6 = 38
, TIMER_OUTCFG13_OUTCFG54_STIMER7 = 39
,
TIMER_OUTCFG13_OUTCFG54_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG13_OUTCFG53_Enum {
TIMER_OUTCFG13_OUTCFG53_TIMER00 = 0
, TIMER_OUTCFG13_OUTCFG53_TIMER01 = 1
, TIMER_OUTCFG13_OUTCFG53_TIMER10 = 2
, TIMER_OUTCFG13_OUTCFG53_TIMER11 = 3
,
TIMER_OUTCFG13_OUTCFG53_TIMER20 = 4
, TIMER_OUTCFG13_OUTCFG53_TIMER21 = 5
, TIMER_OUTCFG13_OUTCFG53_TIMER30 = 6
, TIMER_OUTCFG13_OUTCFG53_TIMER31 = 7
,
TIMER_OUTCFG13_OUTCFG53_TIMER40 = 8
, TIMER_OUTCFG13_OUTCFG53_TIMER41 = 9
, TIMER_OUTCFG13_OUTCFG53_TIMER50 = 10
, TIMER_OUTCFG13_OUTCFG53_TIMER51 = 11
,
TIMER_OUTCFG13_OUTCFG53_TIMER60 = 12
, TIMER_OUTCFG13_OUTCFG53_TIMER61 = 13
, TIMER_OUTCFG13_OUTCFG53_TIMER70 = 14
, TIMER_OUTCFG13_OUTCFG53_TIMER71 = 15
,
TIMER_OUTCFG13_OUTCFG53_TIMER80 = 16
, TIMER_OUTCFG13_OUTCFG53_TIMER81 = 17
, TIMER_OUTCFG13_OUTCFG53_TIMER90 = 18
, TIMER_OUTCFG13_OUTCFG53_TIMER91 = 19
,
TIMER_OUTCFG13_OUTCFG53_TIMER100 = 20
, TIMER_OUTCFG13_OUTCFG53_TIMER101 = 21
, TIMER_OUTCFG13_OUTCFG53_TIMER110 = 22
, TIMER_OUTCFG13_OUTCFG53_TIMER111 = 23
,
TIMER_OUTCFG13_OUTCFG53_TIMER120 = 24
, TIMER_OUTCFG13_OUTCFG53_TIMER121 = 25
, TIMER_OUTCFG13_OUTCFG53_TIMER130 = 26
, TIMER_OUTCFG13_OUTCFG53_TIMER131 = 27
,
TIMER_OUTCFG13_OUTCFG53_TIMER140 = 28
, TIMER_OUTCFG13_OUTCFG53_TIMER141 = 29
, TIMER_OUTCFG13_OUTCFG53_TIMER150 = 30
, TIMER_OUTCFG13_OUTCFG53_TIMER151 = 31
,
TIMER_OUTCFG13_OUTCFG53_STIMER0 = 32
, TIMER_OUTCFG13_OUTCFG53_STIMER1 = 33
, TIMER_OUTCFG13_OUTCFG53_STIMER2 = 34
, TIMER_OUTCFG13_OUTCFG53_STIMER3 = 35
,
TIMER_OUTCFG13_OUTCFG53_STIMER4 = 36
, TIMER_OUTCFG13_OUTCFG53_STIMER5 = 37
, TIMER_OUTCFG13_OUTCFG53_STIMER6 = 38
, TIMER_OUTCFG13_OUTCFG53_STIMER7 = 39
,
TIMER_OUTCFG13_OUTCFG53_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG13_OUTCFG52_Enum {
TIMER_OUTCFG13_OUTCFG52_TIMER00 = 0
, TIMER_OUTCFG13_OUTCFG52_TIMER01 = 1
, TIMER_OUTCFG13_OUTCFG52_TIMER10 = 2
, TIMER_OUTCFG13_OUTCFG52_TIMER11 = 3
,
TIMER_OUTCFG13_OUTCFG52_TIMER20 = 4
, TIMER_OUTCFG13_OUTCFG52_TIMER21 = 5
, TIMER_OUTCFG13_OUTCFG52_TIMER30 = 6
, TIMER_OUTCFG13_OUTCFG52_TIMER31 = 7
,
TIMER_OUTCFG13_OUTCFG52_TIMER40 = 8
, TIMER_OUTCFG13_OUTCFG52_TIMER41 = 9
, TIMER_OUTCFG13_OUTCFG52_TIMER50 = 10
, TIMER_OUTCFG13_OUTCFG52_TIMER51 = 11
,
TIMER_OUTCFG13_OUTCFG52_TIMER60 = 12
, TIMER_OUTCFG13_OUTCFG52_TIMER61 = 13
, TIMER_OUTCFG13_OUTCFG52_TIMER70 = 14
, TIMER_OUTCFG13_OUTCFG52_TIMER71 = 15
,
TIMER_OUTCFG13_OUTCFG52_TIMER80 = 16
, TIMER_OUTCFG13_OUTCFG52_TIMER81 = 17
, TIMER_OUTCFG13_OUTCFG52_TIMER90 = 18
, TIMER_OUTCFG13_OUTCFG52_TIMER91 = 19
,
TIMER_OUTCFG13_OUTCFG52_TIMER100 = 20
, TIMER_OUTCFG13_OUTCFG52_TIMER101 = 21
, TIMER_OUTCFG13_OUTCFG52_TIMER110 = 22
, TIMER_OUTCFG13_OUTCFG52_TIMER111 = 23
,
TIMER_OUTCFG13_OUTCFG52_TIMER120 = 24
, TIMER_OUTCFG13_OUTCFG52_TIMER121 = 25
, TIMER_OUTCFG13_OUTCFG52_TIMER130 = 26
, TIMER_OUTCFG13_OUTCFG52_TIMER131 = 27
,
TIMER_OUTCFG13_OUTCFG52_TIMER140 = 28
, TIMER_OUTCFG13_OUTCFG52_TIMER141 = 29
, TIMER_OUTCFG13_OUTCFG52_TIMER150 = 30
, TIMER_OUTCFG13_OUTCFG52_TIMER151 = 31
,
TIMER_OUTCFG13_OUTCFG52_STIMER0 = 32
, TIMER_OUTCFG13_OUTCFG52_STIMER1 = 33
, TIMER_OUTCFG13_OUTCFG52_STIMER2 = 34
, TIMER_OUTCFG13_OUTCFG52_STIMER3 = 35
,
TIMER_OUTCFG13_OUTCFG52_STIMER4 = 36
, TIMER_OUTCFG13_OUTCFG52_STIMER5 = 37
, TIMER_OUTCFG13_OUTCFG52_STIMER6 = 38
, TIMER_OUTCFG13_OUTCFG52_STIMER7 = 39
,
TIMER_OUTCFG13_OUTCFG52_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG14_OUTCFG59_Enum {
TIMER_OUTCFG14_OUTCFG59_TIMER00 = 0
, TIMER_OUTCFG14_OUTCFG59_TIMER01 = 1
, TIMER_OUTCFG14_OUTCFG59_TIMER10 = 2
, TIMER_OUTCFG14_OUTCFG59_TIMER11 = 3
,
TIMER_OUTCFG14_OUTCFG59_TIMER20 = 4
, TIMER_OUTCFG14_OUTCFG59_TIMER21 = 5
, TIMER_OUTCFG14_OUTCFG59_TIMER30 = 6
, TIMER_OUTCFG14_OUTCFG59_TIMER31 = 7
,
TIMER_OUTCFG14_OUTCFG59_TIMER40 = 8
, TIMER_OUTCFG14_OUTCFG59_TIMER41 = 9
, TIMER_OUTCFG14_OUTCFG59_TIMER50 = 10
, TIMER_OUTCFG14_OUTCFG59_TIMER51 = 11
,
TIMER_OUTCFG14_OUTCFG59_TIMER60 = 12
, TIMER_OUTCFG14_OUTCFG59_TIMER61 = 13
, TIMER_OUTCFG14_OUTCFG59_TIMER70 = 14
, TIMER_OUTCFG14_OUTCFG59_TIMER71 = 15
,
TIMER_OUTCFG14_OUTCFG59_TIMER80 = 16
, TIMER_OUTCFG14_OUTCFG59_TIMER81 = 17
, TIMER_OUTCFG14_OUTCFG59_TIMER90 = 18
, TIMER_OUTCFG14_OUTCFG59_TIMER91 = 19
,
TIMER_OUTCFG14_OUTCFG59_TIMER100 = 20
, TIMER_OUTCFG14_OUTCFG59_TIMER101 = 21
, TIMER_OUTCFG14_OUTCFG59_TIMER110 = 22
, TIMER_OUTCFG14_OUTCFG59_TIMER111 = 23
,
TIMER_OUTCFG14_OUTCFG59_TIMER120 = 24
, TIMER_OUTCFG14_OUTCFG59_TIMER121 = 25
, TIMER_OUTCFG14_OUTCFG59_TIMER130 = 26
, TIMER_OUTCFG14_OUTCFG59_TIMER131 = 27
,
TIMER_OUTCFG14_OUTCFG59_TIMER140 = 28
, TIMER_OUTCFG14_OUTCFG59_TIMER141 = 29
, TIMER_OUTCFG14_OUTCFG59_TIMER150 = 30
, TIMER_OUTCFG14_OUTCFG59_TIMER151 = 31
,
TIMER_OUTCFG14_OUTCFG59_STIMER0 = 32
, TIMER_OUTCFG14_OUTCFG59_STIMER1 = 33
, TIMER_OUTCFG14_OUTCFG59_STIMER2 = 34
, TIMER_OUTCFG14_OUTCFG59_STIMER3 = 35
,
TIMER_OUTCFG14_OUTCFG59_STIMER4 = 36
, TIMER_OUTCFG14_OUTCFG59_STIMER5 = 37
, TIMER_OUTCFG14_OUTCFG59_STIMER6 = 38
, TIMER_OUTCFG14_OUTCFG59_STIMER7 = 39
,
TIMER_OUTCFG14_OUTCFG59_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG14_OUTCFG58_Enum {
TIMER_OUTCFG14_OUTCFG58_TIMER00 = 0
, TIMER_OUTCFG14_OUTCFG58_TIMER01 = 1
, TIMER_OUTCFG14_OUTCFG58_TIMER10 = 2
, TIMER_OUTCFG14_OUTCFG58_TIMER11 = 3
,
TIMER_OUTCFG14_OUTCFG58_TIMER20 = 4
, TIMER_OUTCFG14_OUTCFG58_TIMER21 = 5
, TIMER_OUTCFG14_OUTCFG58_TIMER30 = 6
, TIMER_OUTCFG14_OUTCFG58_TIMER31 = 7
,
TIMER_OUTCFG14_OUTCFG58_TIMER40 = 8
, TIMER_OUTCFG14_OUTCFG58_TIMER41 = 9
, TIMER_OUTCFG14_OUTCFG58_TIMER50 = 10
, TIMER_OUTCFG14_OUTCFG58_TIMER51 = 11
,
TIMER_OUTCFG14_OUTCFG58_TIMER60 = 12
, TIMER_OUTCFG14_OUTCFG58_TIMER61 = 13
, TIMER_OUTCFG14_OUTCFG58_TIMER70 = 14
, TIMER_OUTCFG14_OUTCFG58_TIMER71 = 15
,
TIMER_OUTCFG14_OUTCFG58_TIMER80 = 16
, TIMER_OUTCFG14_OUTCFG58_TIMER81 = 17
, TIMER_OUTCFG14_OUTCFG58_TIMER90 = 18
, TIMER_OUTCFG14_OUTCFG58_TIMER91 = 19
,
TIMER_OUTCFG14_OUTCFG58_TIMER100 = 20
, TIMER_OUTCFG14_OUTCFG58_TIMER101 = 21
, TIMER_OUTCFG14_OUTCFG58_TIMER110 = 22
, TIMER_OUTCFG14_OUTCFG58_TIMER111 = 23
,
TIMER_OUTCFG14_OUTCFG58_TIMER120 = 24
, TIMER_OUTCFG14_OUTCFG58_TIMER121 = 25
, TIMER_OUTCFG14_OUTCFG58_TIMER130 = 26
, TIMER_OUTCFG14_OUTCFG58_TIMER131 = 27
,
TIMER_OUTCFG14_OUTCFG58_TIMER140 = 28
, TIMER_OUTCFG14_OUTCFG58_TIMER141 = 29
, TIMER_OUTCFG14_OUTCFG58_TIMER150 = 30
, TIMER_OUTCFG14_OUTCFG58_TIMER151 = 31
,
TIMER_OUTCFG14_OUTCFG58_STIMER0 = 32
, TIMER_OUTCFG14_OUTCFG58_STIMER1 = 33
, TIMER_OUTCFG14_OUTCFG58_STIMER2 = 34
, TIMER_OUTCFG14_OUTCFG58_STIMER3 = 35
,
TIMER_OUTCFG14_OUTCFG58_STIMER4 = 36
, TIMER_OUTCFG14_OUTCFG58_STIMER5 = 37
, TIMER_OUTCFG14_OUTCFG58_STIMER6 = 38
, TIMER_OUTCFG14_OUTCFG58_STIMER7 = 39
,
TIMER_OUTCFG14_OUTCFG58_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG14_OUTCFG57_Enum {
TIMER_OUTCFG14_OUTCFG57_TIMER00 = 0
, TIMER_OUTCFG14_OUTCFG57_TIMER01 = 1
, TIMER_OUTCFG14_OUTCFG57_TIMER10 = 2
, TIMER_OUTCFG14_OUTCFG57_TIMER11 = 3
,
TIMER_OUTCFG14_OUTCFG57_TIMER20 = 4
, TIMER_OUTCFG14_OUTCFG57_TIMER21 = 5
, TIMER_OUTCFG14_OUTCFG57_TIMER30 = 6
, TIMER_OUTCFG14_OUTCFG57_TIMER31 = 7
,
TIMER_OUTCFG14_OUTCFG57_TIMER40 = 8
, TIMER_OUTCFG14_OUTCFG57_TIMER41 = 9
, TIMER_OUTCFG14_OUTCFG57_TIMER50 = 10
, TIMER_OUTCFG14_OUTCFG57_TIMER51 = 11
,
TIMER_OUTCFG14_OUTCFG57_TIMER60 = 12
, TIMER_OUTCFG14_OUTCFG57_TIMER61 = 13
, TIMER_OUTCFG14_OUTCFG57_TIMER70 = 14
, TIMER_OUTCFG14_OUTCFG57_TIMER71 = 15
,
TIMER_OUTCFG14_OUTCFG57_TIMER80 = 16
, TIMER_OUTCFG14_OUTCFG57_TIMER81 = 17
, TIMER_OUTCFG14_OUTCFG57_TIMER90 = 18
, TIMER_OUTCFG14_OUTCFG57_TIMER91 = 19
,
TIMER_OUTCFG14_OUTCFG57_TIMER100 = 20
, TIMER_OUTCFG14_OUTCFG57_TIMER101 = 21
, TIMER_OUTCFG14_OUTCFG57_TIMER110 = 22
, TIMER_OUTCFG14_OUTCFG57_TIMER111 = 23
,
TIMER_OUTCFG14_OUTCFG57_TIMER120 = 24
, TIMER_OUTCFG14_OUTCFG57_TIMER121 = 25
, TIMER_OUTCFG14_OUTCFG57_TIMER130 = 26
, TIMER_OUTCFG14_OUTCFG57_TIMER131 = 27
,
TIMER_OUTCFG14_OUTCFG57_TIMER140 = 28
, TIMER_OUTCFG14_OUTCFG57_TIMER141 = 29
, TIMER_OUTCFG14_OUTCFG57_TIMER150 = 30
, TIMER_OUTCFG14_OUTCFG57_TIMER151 = 31
,
TIMER_OUTCFG14_OUTCFG57_STIMER0 = 32
, TIMER_OUTCFG14_OUTCFG57_STIMER1 = 33
, TIMER_OUTCFG14_OUTCFG57_STIMER2 = 34
, TIMER_OUTCFG14_OUTCFG57_STIMER3 = 35
,
TIMER_OUTCFG14_OUTCFG57_STIMER4 = 36
, TIMER_OUTCFG14_OUTCFG57_STIMER5 = 37
, TIMER_OUTCFG14_OUTCFG57_STIMER6 = 38
, TIMER_OUTCFG14_OUTCFG57_STIMER7 = 39
,
TIMER_OUTCFG14_OUTCFG57_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG14_OUTCFG56_Enum {
TIMER_OUTCFG14_OUTCFG56_TIMER00 = 0
, TIMER_OUTCFG14_OUTCFG56_TIMER01 = 1
, TIMER_OUTCFG14_OUTCFG56_TIMER10 = 2
, TIMER_OUTCFG14_OUTCFG56_TIMER11 = 3
,
TIMER_OUTCFG14_OUTCFG56_TIMER20 = 4
, TIMER_OUTCFG14_OUTCFG56_TIMER21 = 5
, TIMER_OUTCFG14_OUTCFG56_TIMER30 = 6
, TIMER_OUTCFG14_OUTCFG56_TIMER31 = 7
,
TIMER_OUTCFG14_OUTCFG56_TIMER40 = 8
, TIMER_OUTCFG14_OUTCFG56_TIMER41 = 9
, TIMER_OUTCFG14_OUTCFG56_TIMER50 = 10
, TIMER_OUTCFG14_OUTCFG56_TIMER51 = 11
,
TIMER_OUTCFG14_OUTCFG56_TIMER60 = 12
, TIMER_OUTCFG14_OUTCFG56_TIMER61 = 13
, TIMER_OUTCFG14_OUTCFG56_TIMER70 = 14
, TIMER_OUTCFG14_OUTCFG56_TIMER71 = 15
,
TIMER_OUTCFG14_OUTCFG56_TIMER80 = 16
, TIMER_OUTCFG14_OUTCFG56_TIMER81 = 17
, TIMER_OUTCFG14_OUTCFG56_TIMER90 = 18
, TIMER_OUTCFG14_OUTCFG56_TIMER91 = 19
,
TIMER_OUTCFG14_OUTCFG56_TIMER100 = 20
, TIMER_OUTCFG14_OUTCFG56_TIMER101 = 21
, TIMER_OUTCFG14_OUTCFG56_TIMER110 = 22
, TIMER_OUTCFG14_OUTCFG56_TIMER111 = 23
,
TIMER_OUTCFG14_OUTCFG56_TIMER120 = 24
, TIMER_OUTCFG14_OUTCFG56_TIMER121 = 25
, TIMER_OUTCFG14_OUTCFG56_TIMER130 = 26
, TIMER_OUTCFG14_OUTCFG56_TIMER131 = 27
,
TIMER_OUTCFG14_OUTCFG56_TIMER140 = 28
, TIMER_OUTCFG14_OUTCFG56_TIMER141 = 29
, TIMER_OUTCFG14_OUTCFG56_TIMER150 = 30
, TIMER_OUTCFG14_OUTCFG56_TIMER151 = 31
,
TIMER_OUTCFG14_OUTCFG56_STIMER0 = 32
, TIMER_OUTCFG14_OUTCFG56_STIMER1 = 33
, TIMER_OUTCFG14_OUTCFG56_STIMER2 = 34
, TIMER_OUTCFG14_OUTCFG56_STIMER3 = 35
,
TIMER_OUTCFG14_OUTCFG56_STIMER4 = 36
, TIMER_OUTCFG14_OUTCFG56_STIMER5 = 37
, TIMER_OUTCFG14_OUTCFG56_STIMER6 = 38
, TIMER_OUTCFG14_OUTCFG56_STIMER7 = 39
,
TIMER_OUTCFG14_OUTCFG56_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG15_OUTCFG63_Enum {
TIMER_OUTCFG15_OUTCFG63_TIMER00 = 0
, TIMER_OUTCFG15_OUTCFG63_TIMER01 = 1
, TIMER_OUTCFG15_OUTCFG63_TIMER10 = 2
, TIMER_OUTCFG15_OUTCFG63_TIMER11 = 3
,
TIMER_OUTCFG15_OUTCFG63_TIMER20 = 4
, TIMER_OUTCFG15_OUTCFG63_TIMER21 = 5
, TIMER_OUTCFG15_OUTCFG63_TIMER30 = 6
, TIMER_OUTCFG15_OUTCFG63_TIMER31 = 7
,
TIMER_OUTCFG15_OUTCFG63_TIMER40 = 8
, TIMER_OUTCFG15_OUTCFG63_TIMER41 = 9
, TIMER_OUTCFG15_OUTCFG63_TIMER50 = 10
, TIMER_OUTCFG15_OUTCFG63_TIMER51 = 11
,
TIMER_OUTCFG15_OUTCFG63_TIMER60 = 12
, TIMER_OUTCFG15_OUTCFG63_TIMER61 = 13
, TIMER_OUTCFG15_OUTCFG63_TIMER70 = 14
, TIMER_OUTCFG15_OUTCFG63_TIMER71 = 15
,
TIMER_OUTCFG15_OUTCFG63_TIMER80 = 16
, TIMER_OUTCFG15_OUTCFG63_TIMER81 = 17
, TIMER_OUTCFG15_OUTCFG63_TIMER90 = 18
, TIMER_OUTCFG15_OUTCFG63_TIMER91 = 19
,
TIMER_OUTCFG15_OUTCFG63_TIMER100 = 20
, TIMER_OUTCFG15_OUTCFG63_TIMER101 = 21
, TIMER_OUTCFG15_OUTCFG63_TIMER110 = 22
, TIMER_OUTCFG15_OUTCFG63_TIMER111 = 23
,
TIMER_OUTCFG15_OUTCFG63_TIMER120 = 24
, TIMER_OUTCFG15_OUTCFG63_TIMER121 = 25
, TIMER_OUTCFG15_OUTCFG63_TIMER130 = 26
, TIMER_OUTCFG15_OUTCFG63_TIMER131 = 27
,
TIMER_OUTCFG15_OUTCFG63_TIMER140 = 28
, TIMER_OUTCFG15_OUTCFG63_TIMER141 = 29
, TIMER_OUTCFG15_OUTCFG63_TIMER150 = 30
, TIMER_OUTCFG15_OUTCFG63_TIMER151 = 31
,
TIMER_OUTCFG15_OUTCFG63_STIMER0 = 32
, TIMER_OUTCFG15_OUTCFG63_STIMER1 = 33
, TIMER_OUTCFG15_OUTCFG63_STIMER2 = 34
, TIMER_OUTCFG15_OUTCFG63_STIMER3 = 35
,
TIMER_OUTCFG15_OUTCFG63_STIMER4 = 36
, TIMER_OUTCFG15_OUTCFG63_STIMER5 = 37
, TIMER_OUTCFG15_OUTCFG63_STIMER6 = 38
, TIMER_OUTCFG15_OUTCFG63_STIMER7 = 39
,
TIMER_OUTCFG15_OUTCFG63_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG15_OUTCFG62_Enum {
TIMER_OUTCFG15_OUTCFG62_TIMER00 = 0
, TIMER_OUTCFG15_OUTCFG62_TIMER01 = 1
, TIMER_OUTCFG15_OUTCFG62_TIMER10 = 2
, TIMER_OUTCFG15_OUTCFG62_TIMER11 = 3
,
TIMER_OUTCFG15_OUTCFG62_TIMER20 = 4
, TIMER_OUTCFG15_OUTCFG62_TIMER21 = 5
, TIMER_OUTCFG15_OUTCFG62_TIMER30 = 6
, TIMER_OUTCFG15_OUTCFG62_TIMER31 = 7
,
TIMER_OUTCFG15_OUTCFG62_TIMER40 = 8
, TIMER_OUTCFG15_OUTCFG62_TIMER41 = 9
, TIMER_OUTCFG15_OUTCFG62_TIMER50 = 10
, TIMER_OUTCFG15_OUTCFG62_TIMER51 = 11
,
TIMER_OUTCFG15_OUTCFG62_TIMER60 = 12
, TIMER_OUTCFG15_OUTCFG62_TIMER61 = 13
, TIMER_OUTCFG15_OUTCFG62_TIMER70 = 14
, TIMER_OUTCFG15_OUTCFG62_TIMER71 = 15
,
TIMER_OUTCFG15_OUTCFG62_TIMER80 = 16
, TIMER_OUTCFG15_OUTCFG62_TIMER81 = 17
, TIMER_OUTCFG15_OUTCFG62_TIMER90 = 18
, TIMER_OUTCFG15_OUTCFG62_TIMER91 = 19
,
TIMER_OUTCFG15_OUTCFG62_TIMER100 = 20
, TIMER_OUTCFG15_OUTCFG62_TIMER101 = 21
, TIMER_OUTCFG15_OUTCFG62_TIMER110 = 22
, TIMER_OUTCFG15_OUTCFG62_TIMER111 = 23
,
TIMER_OUTCFG15_OUTCFG62_TIMER120 = 24
, TIMER_OUTCFG15_OUTCFG62_TIMER121 = 25
, TIMER_OUTCFG15_OUTCFG62_TIMER130 = 26
, TIMER_OUTCFG15_OUTCFG62_TIMER131 = 27
,
TIMER_OUTCFG15_OUTCFG62_TIMER140 = 28
, TIMER_OUTCFG15_OUTCFG62_TIMER141 = 29
, TIMER_OUTCFG15_OUTCFG62_TIMER150 = 30
, TIMER_OUTCFG15_OUTCFG62_TIMER151 = 31
,
TIMER_OUTCFG15_OUTCFG62_STIMER0 = 32
, TIMER_OUTCFG15_OUTCFG62_STIMER1 = 33
, TIMER_OUTCFG15_OUTCFG62_STIMER2 = 34
, TIMER_OUTCFG15_OUTCFG62_STIMER3 = 35
,
TIMER_OUTCFG15_OUTCFG62_STIMER4 = 36
, TIMER_OUTCFG15_OUTCFG62_STIMER5 = 37
, TIMER_OUTCFG15_OUTCFG62_STIMER6 = 38
, TIMER_OUTCFG15_OUTCFG62_STIMER7 = 39
,
TIMER_OUTCFG15_OUTCFG62_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG15_OUTCFG61_Enum {
TIMER_OUTCFG15_OUTCFG61_TIMER00 = 0
, TIMER_OUTCFG15_OUTCFG61_TIMER01 = 1
, TIMER_OUTCFG15_OUTCFG61_TIMER10 = 2
, TIMER_OUTCFG15_OUTCFG61_TIMER11 = 3
,
TIMER_OUTCFG15_OUTCFG61_TIMER20 = 4
, TIMER_OUTCFG15_OUTCFG61_TIMER21 = 5
, TIMER_OUTCFG15_OUTCFG61_TIMER30 = 6
, TIMER_OUTCFG15_OUTCFG61_TIMER31 = 7
,
TIMER_OUTCFG15_OUTCFG61_TIMER40 = 8
, TIMER_OUTCFG15_OUTCFG61_TIMER41 = 9
, TIMER_OUTCFG15_OUTCFG61_TIMER50 = 10
, TIMER_OUTCFG15_OUTCFG61_TIMER51 = 11
,
TIMER_OUTCFG15_OUTCFG61_TIMER60 = 12
, TIMER_OUTCFG15_OUTCFG61_TIMER61 = 13
, TIMER_OUTCFG15_OUTCFG61_TIMER70 = 14
, TIMER_OUTCFG15_OUTCFG61_TIMER71 = 15
,
TIMER_OUTCFG15_OUTCFG61_TIMER80 = 16
, TIMER_OUTCFG15_OUTCFG61_TIMER81 = 17
, TIMER_OUTCFG15_OUTCFG61_TIMER90 = 18
, TIMER_OUTCFG15_OUTCFG61_TIMER91 = 19
,
TIMER_OUTCFG15_OUTCFG61_TIMER100 = 20
, TIMER_OUTCFG15_OUTCFG61_TIMER101 = 21
, TIMER_OUTCFG15_OUTCFG61_TIMER110 = 22
, TIMER_OUTCFG15_OUTCFG61_TIMER111 = 23
,
TIMER_OUTCFG15_OUTCFG61_TIMER120 = 24
, TIMER_OUTCFG15_OUTCFG61_TIMER121 = 25
, TIMER_OUTCFG15_OUTCFG61_TIMER130 = 26
, TIMER_OUTCFG15_OUTCFG61_TIMER131 = 27
,
TIMER_OUTCFG15_OUTCFG61_TIMER140 = 28
, TIMER_OUTCFG15_OUTCFG61_TIMER141 = 29
, TIMER_OUTCFG15_OUTCFG61_TIMER150 = 30
, TIMER_OUTCFG15_OUTCFG61_TIMER151 = 31
,
TIMER_OUTCFG15_OUTCFG61_STIMER0 = 32
, TIMER_OUTCFG15_OUTCFG61_STIMER1 = 33
, TIMER_OUTCFG15_OUTCFG61_STIMER2 = 34
, TIMER_OUTCFG15_OUTCFG61_STIMER3 = 35
,
TIMER_OUTCFG15_OUTCFG61_STIMER4 = 36
, TIMER_OUTCFG15_OUTCFG61_STIMER5 = 37
, TIMER_OUTCFG15_OUTCFG61_STIMER6 = 38
, TIMER_OUTCFG15_OUTCFG61_STIMER7 = 39
,
TIMER_OUTCFG15_OUTCFG61_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG15_OUTCFG60_Enum {
TIMER_OUTCFG15_OUTCFG60_TIMER00 = 0
, TIMER_OUTCFG15_OUTCFG60_TIMER01 = 1
, TIMER_OUTCFG15_OUTCFG60_TIMER10 = 2
, TIMER_OUTCFG15_OUTCFG60_TIMER11 = 3
,
TIMER_OUTCFG15_OUTCFG60_TIMER20 = 4
, TIMER_OUTCFG15_OUTCFG60_TIMER21 = 5
, TIMER_OUTCFG15_OUTCFG60_TIMER30 = 6
, TIMER_OUTCFG15_OUTCFG60_TIMER31 = 7
,
TIMER_OUTCFG15_OUTCFG60_TIMER40 = 8
, TIMER_OUTCFG15_OUTCFG60_TIMER41 = 9
, TIMER_OUTCFG15_OUTCFG60_TIMER50 = 10
, TIMER_OUTCFG15_OUTCFG60_TIMER51 = 11
,
TIMER_OUTCFG15_OUTCFG60_TIMER60 = 12
, TIMER_OUTCFG15_OUTCFG60_TIMER61 = 13
, TIMER_OUTCFG15_OUTCFG60_TIMER70 = 14
, TIMER_OUTCFG15_OUTCFG60_TIMER71 = 15
,
TIMER_OUTCFG15_OUTCFG60_TIMER80 = 16
, TIMER_OUTCFG15_OUTCFG60_TIMER81 = 17
, TIMER_OUTCFG15_OUTCFG60_TIMER90 = 18
, TIMER_OUTCFG15_OUTCFG60_TIMER91 = 19
,
TIMER_OUTCFG15_OUTCFG60_TIMER100 = 20
, TIMER_OUTCFG15_OUTCFG60_TIMER101 = 21
, TIMER_OUTCFG15_OUTCFG60_TIMER110 = 22
, TIMER_OUTCFG15_OUTCFG60_TIMER111 = 23
,
TIMER_OUTCFG15_OUTCFG60_TIMER120 = 24
, TIMER_OUTCFG15_OUTCFG60_TIMER121 = 25
, TIMER_OUTCFG15_OUTCFG60_TIMER130 = 26
, TIMER_OUTCFG15_OUTCFG60_TIMER131 = 27
,
TIMER_OUTCFG15_OUTCFG60_TIMER140 = 28
, TIMER_OUTCFG15_OUTCFG60_TIMER141 = 29
, TIMER_OUTCFG15_OUTCFG60_TIMER150 = 30
, TIMER_OUTCFG15_OUTCFG60_TIMER151 = 31
,
TIMER_OUTCFG15_OUTCFG60_STIMER0 = 32
, TIMER_OUTCFG15_OUTCFG60_STIMER1 = 33
, TIMER_OUTCFG15_OUTCFG60_STIMER2 = 34
, TIMER_OUTCFG15_OUTCFG60_STIMER3 = 35
,
TIMER_OUTCFG15_OUTCFG60_STIMER4 = 36
, TIMER_OUTCFG15_OUTCFG60_STIMER5 = 37
, TIMER_OUTCFG15_OUTCFG60_STIMER6 = 38
, TIMER_OUTCFG15_OUTCFG60_STIMER7 = 39
,
TIMER_OUTCFG15_OUTCFG60_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG16_OUTCFG67_Enum {
TIMER_OUTCFG16_OUTCFG67_TIMER00 = 0
, TIMER_OUTCFG16_OUTCFG67_TIMER01 = 1
, TIMER_OUTCFG16_OUTCFG67_TIMER10 = 2
, TIMER_OUTCFG16_OUTCFG67_TIMER11 = 3
,
TIMER_OUTCFG16_OUTCFG67_TIMER20 = 4
, TIMER_OUTCFG16_OUTCFG67_TIMER21 = 5
, TIMER_OUTCFG16_OUTCFG67_TIMER30 = 6
, TIMER_OUTCFG16_OUTCFG67_TIMER31 = 7
,
TIMER_OUTCFG16_OUTCFG67_TIMER40 = 8
, TIMER_OUTCFG16_OUTCFG67_TIMER41 = 9
, TIMER_OUTCFG16_OUTCFG67_TIMER50 = 10
, TIMER_OUTCFG16_OUTCFG67_TIMER51 = 11
,
TIMER_OUTCFG16_OUTCFG67_TIMER60 = 12
, TIMER_OUTCFG16_OUTCFG67_TIMER61 = 13
, TIMER_OUTCFG16_OUTCFG67_TIMER70 = 14
, TIMER_OUTCFG16_OUTCFG67_TIMER71 = 15
,
TIMER_OUTCFG16_OUTCFG67_TIMER80 = 16
, TIMER_OUTCFG16_OUTCFG67_TIMER81 = 17
, TIMER_OUTCFG16_OUTCFG67_TIMER90 = 18
, TIMER_OUTCFG16_OUTCFG67_TIMER91 = 19
,
TIMER_OUTCFG16_OUTCFG67_TIMER100 = 20
, TIMER_OUTCFG16_OUTCFG67_TIMER101 = 21
, TIMER_OUTCFG16_OUTCFG67_TIMER110 = 22
, TIMER_OUTCFG16_OUTCFG67_TIMER111 = 23
,
TIMER_OUTCFG16_OUTCFG67_TIMER120 = 24
, TIMER_OUTCFG16_OUTCFG67_TIMER121 = 25
, TIMER_OUTCFG16_OUTCFG67_TIMER130 = 26
, TIMER_OUTCFG16_OUTCFG67_TIMER131 = 27
,
TIMER_OUTCFG16_OUTCFG67_TIMER140 = 28
, TIMER_OUTCFG16_OUTCFG67_TIMER141 = 29
, TIMER_OUTCFG16_OUTCFG67_TIMER150 = 30
, TIMER_OUTCFG16_OUTCFG67_TIMER151 = 31
,
TIMER_OUTCFG16_OUTCFG67_STIMER0 = 32
, TIMER_OUTCFG16_OUTCFG67_STIMER1 = 33
, TIMER_OUTCFG16_OUTCFG67_STIMER2 = 34
, TIMER_OUTCFG16_OUTCFG67_STIMER3 = 35
,
TIMER_OUTCFG16_OUTCFG67_STIMER4 = 36
, TIMER_OUTCFG16_OUTCFG67_STIMER5 = 37
, TIMER_OUTCFG16_OUTCFG67_STIMER6 = 38
, TIMER_OUTCFG16_OUTCFG67_STIMER7 = 39
,
TIMER_OUTCFG16_OUTCFG67_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG16_OUTCFG66_Enum {
TIMER_OUTCFG16_OUTCFG66_TIMER00 = 0
, TIMER_OUTCFG16_OUTCFG66_TIMER01 = 1
, TIMER_OUTCFG16_OUTCFG66_TIMER10 = 2
, TIMER_OUTCFG16_OUTCFG66_TIMER11 = 3
,
TIMER_OUTCFG16_OUTCFG66_TIMER20 = 4
, TIMER_OUTCFG16_OUTCFG66_TIMER21 = 5
, TIMER_OUTCFG16_OUTCFG66_TIMER30 = 6
, TIMER_OUTCFG16_OUTCFG66_TIMER31 = 7
,
TIMER_OUTCFG16_OUTCFG66_TIMER40 = 8
, TIMER_OUTCFG16_OUTCFG66_TIMER41 = 9
, TIMER_OUTCFG16_OUTCFG66_TIMER50 = 10
, TIMER_OUTCFG16_OUTCFG66_TIMER51 = 11
,
TIMER_OUTCFG16_OUTCFG66_TIMER60 = 12
, TIMER_OUTCFG16_OUTCFG66_TIMER61 = 13
, TIMER_OUTCFG16_OUTCFG66_TIMER70 = 14
, TIMER_OUTCFG16_OUTCFG66_TIMER71 = 15
,
TIMER_OUTCFG16_OUTCFG66_TIMER80 = 16
, TIMER_OUTCFG16_OUTCFG66_TIMER81 = 17
, TIMER_OUTCFG16_OUTCFG66_TIMER90 = 18
, TIMER_OUTCFG16_OUTCFG66_TIMER91 = 19
,
TIMER_OUTCFG16_OUTCFG66_TIMER100 = 20
, TIMER_OUTCFG16_OUTCFG66_TIMER101 = 21
, TIMER_OUTCFG16_OUTCFG66_TIMER110 = 22
, TIMER_OUTCFG16_OUTCFG66_TIMER111 = 23
,
TIMER_OUTCFG16_OUTCFG66_TIMER120 = 24
, TIMER_OUTCFG16_OUTCFG66_TIMER121 = 25
, TIMER_OUTCFG16_OUTCFG66_TIMER130 = 26
, TIMER_OUTCFG16_OUTCFG66_TIMER131 = 27
,
TIMER_OUTCFG16_OUTCFG66_TIMER140 = 28
, TIMER_OUTCFG16_OUTCFG66_TIMER141 = 29
, TIMER_OUTCFG16_OUTCFG66_TIMER150 = 30
, TIMER_OUTCFG16_OUTCFG66_TIMER151 = 31
,
TIMER_OUTCFG16_OUTCFG66_STIMER0 = 32
, TIMER_OUTCFG16_OUTCFG66_STIMER1 = 33
, TIMER_OUTCFG16_OUTCFG66_STIMER2 = 34
, TIMER_OUTCFG16_OUTCFG66_STIMER3 = 35
,
TIMER_OUTCFG16_OUTCFG66_STIMER4 = 36
, TIMER_OUTCFG16_OUTCFG66_STIMER5 = 37
, TIMER_OUTCFG16_OUTCFG66_STIMER6 = 38
, TIMER_OUTCFG16_OUTCFG66_STIMER7 = 39
,
TIMER_OUTCFG16_OUTCFG66_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG16_OUTCFG65_Enum {
TIMER_OUTCFG16_OUTCFG65_TIMER00 = 0
, TIMER_OUTCFG16_OUTCFG65_TIMER01 = 1
, TIMER_OUTCFG16_OUTCFG65_TIMER10 = 2
, TIMER_OUTCFG16_OUTCFG65_TIMER11 = 3
,
TIMER_OUTCFG16_OUTCFG65_TIMER20 = 4
, TIMER_OUTCFG16_OUTCFG65_TIMER21 = 5
, TIMER_OUTCFG16_OUTCFG65_TIMER30 = 6
, TIMER_OUTCFG16_OUTCFG65_TIMER31 = 7
,
TIMER_OUTCFG16_OUTCFG65_TIMER40 = 8
, TIMER_OUTCFG16_OUTCFG65_TIMER41 = 9
, TIMER_OUTCFG16_OUTCFG65_TIMER50 = 10
, TIMER_OUTCFG16_OUTCFG65_TIMER51 = 11
,
TIMER_OUTCFG16_OUTCFG65_TIMER60 = 12
, TIMER_OUTCFG16_OUTCFG65_TIMER61 = 13
, TIMER_OUTCFG16_OUTCFG65_TIMER70 = 14
, TIMER_OUTCFG16_OUTCFG65_TIMER71 = 15
,
TIMER_OUTCFG16_OUTCFG65_TIMER80 = 16
, TIMER_OUTCFG16_OUTCFG65_TIMER81 = 17
, TIMER_OUTCFG16_OUTCFG65_TIMER90 = 18
, TIMER_OUTCFG16_OUTCFG65_TIMER91 = 19
,
TIMER_OUTCFG16_OUTCFG65_TIMER100 = 20
, TIMER_OUTCFG16_OUTCFG65_TIMER101 = 21
, TIMER_OUTCFG16_OUTCFG65_TIMER110 = 22
, TIMER_OUTCFG16_OUTCFG65_TIMER111 = 23
,
TIMER_OUTCFG16_OUTCFG65_TIMER120 = 24
, TIMER_OUTCFG16_OUTCFG65_TIMER121 = 25
, TIMER_OUTCFG16_OUTCFG65_TIMER130 = 26
, TIMER_OUTCFG16_OUTCFG65_TIMER131 = 27
,
TIMER_OUTCFG16_OUTCFG65_TIMER140 = 28
, TIMER_OUTCFG16_OUTCFG65_TIMER141 = 29
, TIMER_OUTCFG16_OUTCFG65_TIMER150 = 30
, TIMER_OUTCFG16_OUTCFG65_TIMER151 = 31
,
TIMER_OUTCFG16_OUTCFG65_STIMER0 = 32
, TIMER_OUTCFG16_OUTCFG65_STIMER1 = 33
, TIMER_OUTCFG16_OUTCFG65_STIMER2 = 34
, TIMER_OUTCFG16_OUTCFG65_STIMER3 = 35
,
TIMER_OUTCFG16_OUTCFG65_STIMER4 = 36
, TIMER_OUTCFG16_OUTCFG65_STIMER5 = 37
, TIMER_OUTCFG16_OUTCFG65_STIMER6 = 38
, TIMER_OUTCFG16_OUTCFG65_STIMER7 = 39
,
TIMER_OUTCFG16_OUTCFG65_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG16_OUTCFG64_Enum {
TIMER_OUTCFG16_OUTCFG64_TIMER00 = 0
, TIMER_OUTCFG16_OUTCFG64_TIMER01 = 1
, TIMER_OUTCFG16_OUTCFG64_TIMER10 = 2
, TIMER_OUTCFG16_OUTCFG64_TIMER11 = 3
,
TIMER_OUTCFG16_OUTCFG64_TIMER20 = 4
, TIMER_OUTCFG16_OUTCFG64_TIMER21 = 5
, TIMER_OUTCFG16_OUTCFG64_TIMER30 = 6
, TIMER_OUTCFG16_OUTCFG64_TIMER31 = 7
,
TIMER_OUTCFG16_OUTCFG64_TIMER40 = 8
, TIMER_OUTCFG16_OUTCFG64_TIMER41 = 9
, TIMER_OUTCFG16_OUTCFG64_TIMER50 = 10
, TIMER_OUTCFG16_OUTCFG64_TIMER51 = 11
,
TIMER_OUTCFG16_OUTCFG64_TIMER60 = 12
, TIMER_OUTCFG16_OUTCFG64_TIMER61 = 13
, TIMER_OUTCFG16_OUTCFG64_TIMER70 = 14
, TIMER_OUTCFG16_OUTCFG64_TIMER71 = 15
,
TIMER_OUTCFG16_OUTCFG64_TIMER80 = 16
, TIMER_OUTCFG16_OUTCFG64_TIMER81 = 17
, TIMER_OUTCFG16_OUTCFG64_TIMER90 = 18
, TIMER_OUTCFG16_OUTCFG64_TIMER91 = 19
,
TIMER_OUTCFG16_OUTCFG64_TIMER100 = 20
, TIMER_OUTCFG16_OUTCFG64_TIMER101 = 21
, TIMER_OUTCFG16_OUTCFG64_TIMER110 = 22
, TIMER_OUTCFG16_OUTCFG64_TIMER111 = 23
,
TIMER_OUTCFG16_OUTCFG64_TIMER120 = 24
, TIMER_OUTCFG16_OUTCFG64_TIMER121 = 25
, TIMER_OUTCFG16_OUTCFG64_TIMER130 = 26
, TIMER_OUTCFG16_OUTCFG64_TIMER131 = 27
,
TIMER_OUTCFG16_OUTCFG64_TIMER140 = 28
, TIMER_OUTCFG16_OUTCFG64_TIMER141 = 29
, TIMER_OUTCFG16_OUTCFG64_TIMER150 = 30
, TIMER_OUTCFG16_OUTCFG64_TIMER151 = 31
,
TIMER_OUTCFG16_OUTCFG64_STIMER0 = 32
, TIMER_OUTCFG16_OUTCFG64_STIMER1 = 33
, TIMER_OUTCFG16_OUTCFG64_STIMER2 = 34
, TIMER_OUTCFG16_OUTCFG64_STIMER3 = 35
,
TIMER_OUTCFG16_OUTCFG64_STIMER4 = 36
, TIMER_OUTCFG16_OUTCFG64_STIMER5 = 37
, TIMER_OUTCFG16_OUTCFG64_STIMER6 = 38
, TIMER_OUTCFG16_OUTCFG64_STIMER7 = 39
,
TIMER_OUTCFG16_OUTCFG64_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG17_OUTCFG71_Enum {
TIMER_OUTCFG17_OUTCFG71_TIMER00 = 0
, TIMER_OUTCFG17_OUTCFG71_TIMER01 = 1
, TIMER_OUTCFG17_OUTCFG71_TIMER10 = 2
, TIMER_OUTCFG17_OUTCFG71_TIMER11 = 3
,
TIMER_OUTCFG17_OUTCFG71_TIMER20 = 4
, TIMER_OUTCFG17_OUTCFG71_TIMER21 = 5
, TIMER_OUTCFG17_OUTCFG71_TIMER30 = 6
, TIMER_OUTCFG17_OUTCFG71_TIMER31 = 7
,
TIMER_OUTCFG17_OUTCFG71_TIMER40 = 8
, TIMER_OUTCFG17_OUTCFG71_TIMER41 = 9
, TIMER_OUTCFG17_OUTCFG71_TIMER50 = 10
, TIMER_OUTCFG17_OUTCFG71_TIMER51 = 11
,
TIMER_OUTCFG17_OUTCFG71_TIMER60 = 12
, TIMER_OUTCFG17_OUTCFG71_TIMER61 = 13
, TIMER_OUTCFG17_OUTCFG71_TIMER70 = 14
, TIMER_OUTCFG17_OUTCFG71_TIMER71 = 15
,
TIMER_OUTCFG17_OUTCFG71_TIMER80 = 16
, TIMER_OUTCFG17_OUTCFG71_TIMER81 = 17
, TIMER_OUTCFG17_OUTCFG71_TIMER90 = 18
, TIMER_OUTCFG17_OUTCFG71_TIMER91 = 19
,
TIMER_OUTCFG17_OUTCFG71_TIMER100 = 20
, TIMER_OUTCFG17_OUTCFG71_TIMER101 = 21
, TIMER_OUTCFG17_OUTCFG71_TIMER110 = 22
, TIMER_OUTCFG17_OUTCFG71_TIMER111 = 23
,
TIMER_OUTCFG17_OUTCFG71_TIMER120 = 24
, TIMER_OUTCFG17_OUTCFG71_TIMER121 = 25
, TIMER_OUTCFG17_OUTCFG71_TIMER130 = 26
, TIMER_OUTCFG17_OUTCFG71_TIMER131 = 27
,
TIMER_OUTCFG17_OUTCFG71_TIMER140 = 28
, TIMER_OUTCFG17_OUTCFG71_TIMER141 = 29
, TIMER_OUTCFG17_OUTCFG71_TIMER150 = 30
, TIMER_OUTCFG17_OUTCFG71_TIMER151 = 31
,
TIMER_OUTCFG17_OUTCFG71_STIMER0 = 32
, TIMER_OUTCFG17_OUTCFG71_STIMER1 = 33
, TIMER_OUTCFG17_OUTCFG71_STIMER2 = 34
, TIMER_OUTCFG17_OUTCFG71_STIMER3 = 35
,
TIMER_OUTCFG17_OUTCFG71_STIMER4 = 36
, TIMER_OUTCFG17_OUTCFG71_STIMER5 = 37
, TIMER_OUTCFG17_OUTCFG71_STIMER6 = 38
, TIMER_OUTCFG17_OUTCFG71_STIMER7 = 39
,
TIMER_OUTCFG17_OUTCFG71_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG17_OUTCFG70_Enum {
TIMER_OUTCFG17_OUTCFG70_TIMER00 = 0
, TIMER_OUTCFG17_OUTCFG70_TIMER01 = 1
, TIMER_OUTCFG17_OUTCFG70_TIMER10 = 2
, TIMER_OUTCFG17_OUTCFG70_TIMER11 = 3
,
TIMER_OUTCFG17_OUTCFG70_TIMER20 = 4
, TIMER_OUTCFG17_OUTCFG70_TIMER21 = 5
, TIMER_OUTCFG17_OUTCFG70_TIMER30 = 6
, TIMER_OUTCFG17_OUTCFG70_TIMER31 = 7
,
TIMER_OUTCFG17_OUTCFG70_TIMER40 = 8
, TIMER_OUTCFG17_OUTCFG70_TIMER41 = 9
, TIMER_OUTCFG17_OUTCFG70_TIMER50 = 10
, TIMER_OUTCFG17_OUTCFG70_TIMER51 = 11
,
TIMER_OUTCFG17_OUTCFG70_TIMER60 = 12
, TIMER_OUTCFG17_OUTCFG70_TIMER61 = 13
, TIMER_OUTCFG17_OUTCFG70_TIMER70 = 14
, TIMER_OUTCFG17_OUTCFG70_TIMER71 = 15
,
TIMER_OUTCFG17_OUTCFG70_TIMER80 = 16
, TIMER_OUTCFG17_OUTCFG70_TIMER81 = 17
, TIMER_OUTCFG17_OUTCFG70_TIMER90 = 18
, TIMER_OUTCFG17_OUTCFG70_TIMER91 = 19
,
TIMER_OUTCFG17_OUTCFG70_TIMER100 = 20
, TIMER_OUTCFG17_OUTCFG70_TIMER101 = 21
, TIMER_OUTCFG17_OUTCFG70_TIMER110 = 22
, TIMER_OUTCFG17_OUTCFG70_TIMER111 = 23
,
TIMER_OUTCFG17_OUTCFG70_TIMER120 = 24
, TIMER_OUTCFG17_OUTCFG70_TIMER121 = 25
, TIMER_OUTCFG17_OUTCFG70_TIMER130 = 26
, TIMER_OUTCFG17_OUTCFG70_TIMER131 = 27
,
TIMER_OUTCFG17_OUTCFG70_TIMER140 = 28
, TIMER_OUTCFG17_OUTCFG70_TIMER141 = 29
, TIMER_OUTCFG17_OUTCFG70_TIMER150 = 30
, TIMER_OUTCFG17_OUTCFG70_TIMER151 = 31
,
TIMER_OUTCFG17_OUTCFG70_STIMER0 = 32
, TIMER_OUTCFG17_OUTCFG70_STIMER1 = 33
, TIMER_OUTCFG17_OUTCFG70_STIMER2 = 34
, TIMER_OUTCFG17_OUTCFG70_STIMER3 = 35
,
TIMER_OUTCFG17_OUTCFG70_STIMER4 = 36
, TIMER_OUTCFG17_OUTCFG70_STIMER5 = 37
, TIMER_OUTCFG17_OUTCFG70_STIMER6 = 38
, TIMER_OUTCFG17_OUTCFG70_STIMER7 = 39
,
TIMER_OUTCFG17_OUTCFG70_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG17_OUTCFG69_Enum {
TIMER_OUTCFG17_OUTCFG69_TIMER00 = 0
, TIMER_OUTCFG17_OUTCFG69_TIMER01 = 1
, TIMER_OUTCFG17_OUTCFG69_TIMER10 = 2
, TIMER_OUTCFG17_OUTCFG69_TIMER11 = 3
,
TIMER_OUTCFG17_OUTCFG69_TIMER20 = 4
, TIMER_OUTCFG17_OUTCFG69_TIMER21 = 5
, TIMER_OUTCFG17_OUTCFG69_TIMER30 = 6
, TIMER_OUTCFG17_OUTCFG69_TIMER31 = 7
,
TIMER_OUTCFG17_OUTCFG69_TIMER40 = 8
, TIMER_OUTCFG17_OUTCFG69_TIMER41 = 9
, TIMER_OUTCFG17_OUTCFG69_TIMER50 = 10
, TIMER_OUTCFG17_OUTCFG69_TIMER51 = 11
,
TIMER_OUTCFG17_OUTCFG69_TIMER60 = 12
, TIMER_OUTCFG17_OUTCFG69_TIMER61 = 13
, TIMER_OUTCFG17_OUTCFG69_TIMER70 = 14
, TIMER_OUTCFG17_OUTCFG69_TIMER71 = 15
,
TIMER_OUTCFG17_OUTCFG69_TIMER80 = 16
, TIMER_OUTCFG17_OUTCFG69_TIMER81 = 17
, TIMER_OUTCFG17_OUTCFG69_TIMER90 = 18
, TIMER_OUTCFG17_OUTCFG69_TIMER91 = 19
,
TIMER_OUTCFG17_OUTCFG69_TIMER100 = 20
, TIMER_OUTCFG17_OUTCFG69_TIMER101 = 21
, TIMER_OUTCFG17_OUTCFG69_TIMER110 = 22
, TIMER_OUTCFG17_OUTCFG69_TIMER111 = 23
,
TIMER_OUTCFG17_OUTCFG69_TIMER120 = 24
, TIMER_OUTCFG17_OUTCFG69_TIMER121 = 25
, TIMER_OUTCFG17_OUTCFG69_TIMER130 = 26
, TIMER_OUTCFG17_OUTCFG69_TIMER131 = 27
,
TIMER_OUTCFG17_OUTCFG69_TIMER140 = 28
, TIMER_OUTCFG17_OUTCFG69_TIMER141 = 29
, TIMER_OUTCFG17_OUTCFG69_TIMER150 = 30
, TIMER_OUTCFG17_OUTCFG69_TIMER151 = 31
,
TIMER_OUTCFG17_OUTCFG69_STIMER0 = 32
, TIMER_OUTCFG17_OUTCFG69_STIMER1 = 33
, TIMER_OUTCFG17_OUTCFG69_STIMER2 = 34
, TIMER_OUTCFG17_OUTCFG69_STIMER3 = 35
,
TIMER_OUTCFG17_OUTCFG69_STIMER4 = 36
, TIMER_OUTCFG17_OUTCFG69_STIMER5 = 37
, TIMER_OUTCFG17_OUTCFG69_STIMER6 = 38
, TIMER_OUTCFG17_OUTCFG69_STIMER7 = 39
,
TIMER_OUTCFG17_OUTCFG69_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG17_OUTCFG68_Enum {
TIMER_OUTCFG17_OUTCFG68_TIMER00 = 0
, TIMER_OUTCFG17_OUTCFG68_TIMER01 = 1
, TIMER_OUTCFG17_OUTCFG68_TIMER10 = 2
, TIMER_OUTCFG17_OUTCFG68_TIMER11 = 3
,
TIMER_OUTCFG17_OUTCFG68_TIMER20 = 4
, TIMER_OUTCFG17_OUTCFG68_TIMER21 = 5
, TIMER_OUTCFG17_OUTCFG68_TIMER30 = 6
, TIMER_OUTCFG17_OUTCFG68_TIMER31 = 7
,
TIMER_OUTCFG17_OUTCFG68_TIMER40 = 8
, TIMER_OUTCFG17_OUTCFG68_TIMER41 = 9
, TIMER_OUTCFG17_OUTCFG68_TIMER50 = 10
, TIMER_OUTCFG17_OUTCFG68_TIMER51 = 11
,
TIMER_OUTCFG17_OUTCFG68_TIMER60 = 12
, TIMER_OUTCFG17_OUTCFG68_TIMER61 = 13
, TIMER_OUTCFG17_OUTCFG68_TIMER70 = 14
, TIMER_OUTCFG17_OUTCFG68_TIMER71 = 15
,
TIMER_OUTCFG17_OUTCFG68_TIMER80 = 16
, TIMER_OUTCFG17_OUTCFG68_TIMER81 = 17
, TIMER_OUTCFG17_OUTCFG68_TIMER90 = 18
, TIMER_OUTCFG17_OUTCFG68_TIMER91 = 19
,
TIMER_OUTCFG17_OUTCFG68_TIMER100 = 20
, TIMER_OUTCFG17_OUTCFG68_TIMER101 = 21
, TIMER_OUTCFG17_OUTCFG68_TIMER110 = 22
, TIMER_OUTCFG17_OUTCFG68_TIMER111 = 23
,
TIMER_OUTCFG17_OUTCFG68_TIMER120 = 24
, TIMER_OUTCFG17_OUTCFG68_TIMER121 = 25
, TIMER_OUTCFG17_OUTCFG68_TIMER130 = 26
, TIMER_OUTCFG17_OUTCFG68_TIMER131 = 27
,
TIMER_OUTCFG17_OUTCFG68_TIMER140 = 28
, TIMER_OUTCFG17_OUTCFG68_TIMER141 = 29
, TIMER_OUTCFG17_OUTCFG68_TIMER150 = 30
, TIMER_OUTCFG17_OUTCFG68_TIMER151 = 31
,
TIMER_OUTCFG17_OUTCFG68_STIMER0 = 32
, TIMER_OUTCFG17_OUTCFG68_STIMER1 = 33
, TIMER_OUTCFG17_OUTCFG68_STIMER2 = 34
, TIMER_OUTCFG17_OUTCFG68_STIMER3 = 35
,
TIMER_OUTCFG17_OUTCFG68_STIMER4 = 36
, TIMER_OUTCFG17_OUTCFG68_STIMER5 = 37
, TIMER_OUTCFG17_OUTCFG68_STIMER6 = 38
, TIMER_OUTCFG17_OUTCFG68_STIMER7 = 39
,
TIMER_OUTCFG17_OUTCFG68_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG18_OUTCFG75_Enum {
TIMER_OUTCFG18_OUTCFG75_TIMER00 = 0
, TIMER_OUTCFG18_OUTCFG75_TIMER01 = 1
, TIMER_OUTCFG18_OUTCFG75_TIMER10 = 2
, TIMER_OUTCFG18_OUTCFG75_TIMER11 = 3
,
TIMER_OUTCFG18_OUTCFG75_TIMER20 = 4
, TIMER_OUTCFG18_OUTCFG75_TIMER21 = 5
, TIMER_OUTCFG18_OUTCFG75_TIMER30 = 6
, TIMER_OUTCFG18_OUTCFG75_TIMER31 = 7
,
TIMER_OUTCFG18_OUTCFG75_TIMER40 = 8
, TIMER_OUTCFG18_OUTCFG75_TIMER41 = 9
, TIMER_OUTCFG18_OUTCFG75_TIMER50 = 10
, TIMER_OUTCFG18_OUTCFG75_TIMER51 = 11
,
TIMER_OUTCFG18_OUTCFG75_TIMER60 = 12
, TIMER_OUTCFG18_OUTCFG75_TIMER61 = 13
, TIMER_OUTCFG18_OUTCFG75_TIMER70 = 14
, TIMER_OUTCFG18_OUTCFG75_TIMER71 = 15
,
TIMER_OUTCFG18_OUTCFG75_TIMER80 = 16
, TIMER_OUTCFG18_OUTCFG75_TIMER81 = 17
, TIMER_OUTCFG18_OUTCFG75_TIMER90 = 18
, TIMER_OUTCFG18_OUTCFG75_TIMER91 = 19
,
TIMER_OUTCFG18_OUTCFG75_TIMER100 = 20
, TIMER_OUTCFG18_OUTCFG75_TIMER101 = 21
, TIMER_OUTCFG18_OUTCFG75_TIMER110 = 22
, TIMER_OUTCFG18_OUTCFG75_TIMER111 = 23
,
TIMER_OUTCFG18_OUTCFG75_TIMER120 = 24
, TIMER_OUTCFG18_OUTCFG75_TIMER121 = 25
, TIMER_OUTCFG18_OUTCFG75_TIMER130 = 26
, TIMER_OUTCFG18_OUTCFG75_TIMER131 = 27
,
TIMER_OUTCFG18_OUTCFG75_TIMER140 = 28
, TIMER_OUTCFG18_OUTCFG75_TIMER141 = 29
, TIMER_OUTCFG18_OUTCFG75_TIMER150 = 30
, TIMER_OUTCFG18_OUTCFG75_TIMER151 = 31
,
TIMER_OUTCFG18_OUTCFG75_STIMER0 = 32
, TIMER_OUTCFG18_OUTCFG75_STIMER1 = 33
, TIMER_OUTCFG18_OUTCFG75_STIMER2 = 34
, TIMER_OUTCFG18_OUTCFG75_STIMER3 = 35
,
TIMER_OUTCFG18_OUTCFG75_STIMER4 = 36
, TIMER_OUTCFG18_OUTCFG75_STIMER5 = 37
, TIMER_OUTCFG18_OUTCFG75_STIMER6 = 38
, TIMER_OUTCFG18_OUTCFG75_STIMER7 = 39
,
TIMER_OUTCFG18_OUTCFG75_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG18_OUTCFG74_Enum {
TIMER_OUTCFG18_OUTCFG74_TIMER00 = 0
, TIMER_OUTCFG18_OUTCFG74_TIMER01 = 1
, TIMER_OUTCFG18_OUTCFG74_TIMER10 = 2
, TIMER_OUTCFG18_OUTCFG74_TIMER11 = 3
,
TIMER_OUTCFG18_OUTCFG74_TIMER20 = 4
, TIMER_OUTCFG18_OUTCFG74_TIMER21 = 5
, TIMER_OUTCFG18_OUTCFG74_TIMER30 = 6
, TIMER_OUTCFG18_OUTCFG74_TIMER31 = 7
,
TIMER_OUTCFG18_OUTCFG74_TIMER40 = 8
, TIMER_OUTCFG18_OUTCFG74_TIMER41 = 9
, TIMER_OUTCFG18_OUTCFG74_TIMER50 = 10
, TIMER_OUTCFG18_OUTCFG74_TIMER51 = 11
,
TIMER_OUTCFG18_OUTCFG74_TIMER60 = 12
, TIMER_OUTCFG18_OUTCFG74_TIMER61 = 13
, TIMER_OUTCFG18_OUTCFG74_TIMER70 = 14
, TIMER_OUTCFG18_OUTCFG74_TIMER71 = 15
,
TIMER_OUTCFG18_OUTCFG74_TIMER80 = 16
, TIMER_OUTCFG18_OUTCFG74_TIMER81 = 17
, TIMER_OUTCFG18_OUTCFG74_TIMER90 = 18
, TIMER_OUTCFG18_OUTCFG74_TIMER91 = 19
,
TIMER_OUTCFG18_OUTCFG74_TIMER100 = 20
, TIMER_OUTCFG18_OUTCFG74_TIMER101 = 21
, TIMER_OUTCFG18_OUTCFG74_TIMER110 = 22
, TIMER_OUTCFG18_OUTCFG74_TIMER111 = 23
,
TIMER_OUTCFG18_OUTCFG74_TIMER120 = 24
, TIMER_OUTCFG18_OUTCFG74_TIMER121 = 25
, TIMER_OUTCFG18_OUTCFG74_TIMER130 = 26
, TIMER_OUTCFG18_OUTCFG74_TIMER131 = 27
,
TIMER_OUTCFG18_OUTCFG74_TIMER140 = 28
, TIMER_OUTCFG18_OUTCFG74_TIMER141 = 29
, TIMER_OUTCFG18_OUTCFG74_TIMER150 = 30
, TIMER_OUTCFG18_OUTCFG74_TIMER151 = 31
,
TIMER_OUTCFG18_OUTCFG74_STIMER0 = 32
, TIMER_OUTCFG18_OUTCFG74_STIMER1 = 33
, TIMER_OUTCFG18_OUTCFG74_STIMER2 = 34
, TIMER_OUTCFG18_OUTCFG74_STIMER3 = 35
,
TIMER_OUTCFG18_OUTCFG74_STIMER4 = 36
, TIMER_OUTCFG18_OUTCFG74_STIMER5 = 37
, TIMER_OUTCFG18_OUTCFG74_STIMER6 = 38
, TIMER_OUTCFG18_OUTCFG74_STIMER7 = 39
,
TIMER_OUTCFG18_OUTCFG74_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG18_OUTCFG73_Enum {
TIMER_OUTCFG18_OUTCFG73_TIMER00 = 0
, TIMER_OUTCFG18_OUTCFG73_TIMER01 = 1
, TIMER_OUTCFG18_OUTCFG73_TIMER10 = 2
, TIMER_OUTCFG18_OUTCFG73_TIMER11 = 3
,
TIMER_OUTCFG18_OUTCFG73_TIMER20 = 4
, TIMER_OUTCFG18_OUTCFG73_TIMER21 = 5
, TIMER_OUTCFG18_OUTCFG73_TIMER30 = 6
, TIMER_OUTCFG18_OUTCFG73_TIMER31 = 7
,
TIMER_OUTCFG18_OUTCFG73_TIMER40 = 8
, TIMER_OUTCFG18_OUTCFG73_TIMER41 = 9
, TIMER_OUTCFG18_OUTCFG73_TIMER50 = 10
, TIMER_OUTCFG18_OUTCFG73_TIMER51 = 11
,
TIMER_OUTCFG18_OUTCFG73_TIMER60 = 12
, TIMER_OUTCFG18_OUTCFG73_TIMER61 = 13
, TIMER_OUTCFG18_OUTCFG73_TIMER70 = 14
, TIMER_OUTCFG18_OUTCFG73_TIMER71 = 15
,
TIMER_OUTCFG18_OUTCFG73_TIMER80 = 16
, TIMER_OUTCFG18_OUTCFG73_TIMER81 = 17
, TIMER_OUTCFG18_OUTCFG73_TIMER90 = 18
, TIMER_OUTCFG18_OUTCFG73_TIMER91 = 19
,
TIMER_OUTCFG18_OUTCFG73_TIMER100 = 20
, TIMER_OUTCFG18_OUTCFG73_TIMER101 = 21
, TIMER_OUTCFG18_OUTCFG73_TIMER110 = 22
, TIMER_OUTCFG18_OUTCFG73_TIMER111 = 23
,
TIMER_OUTCFG18_OUTCFG73_TIMER120 = 24
, TIMER_OUTCFG18_OUTCFG73_TIMER121 = 25
, TIMER_OUTCFG18_OUTCFG73_TIMER130 = 26
, TIMER_OUTCFG18_OUTCFG73_TIMER131 = 27
,
TIMER_OUTCFG18_OUTCFG73_TIMER140 = 28
, TIMER_OUTCFG18_OUTCFG73_TIMER141 = 29
, TIMER_OUTCFG18_OUTCFG73_TIMER150 = 30
, TIMER_OUTCFG18_OUTCFG73_TIMER151 = 31
,
TIMER_OUTCFG18_OUTCFG73_STIMER0 = 32
, TIMER_OUTCFG18_OUTCFG73_STIMER1 = 33
, TIMER_OUTCFG18_OUTCFG73_STIMER2 = 34
, TIMER_OUTCFG18_OUTCFG73_STIMER3 = 35
,
TIMER_OUTCFG18_OUTCFG73_STIMER4 = 36
, TIMER_OUTCFG18_OUTCFG73_STIMER5 = 37
, TIMER_OUTCFG18_OUTCFG73_STIMER6 = 38
, TIMER_OUTCFG18_OUTCFG73_STIMER7 = 39
,
TIMER_OUTCFG18_OUTCFG73_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG18_OUTCFG72_Enum {
TIMER_OUTCFG18_OUTCFG72_TIMER00 = 0
, TIMER_OUTCFG18_OUTCFG72_TIMER01 = 1
, TIMER_OUTCFG18_OUTCFG72_TIMER10 = 2
, TIMER_OUTCFG18_OUTCFG72_TIMER11 = 3
,
TIMER_OUTCFG18_OUTCFG72_TIMER20 = 4
, TIMER_OUTCFG18_OUTCFG72_TIMER21 = 5
, TIMER_OUTCFG18_OUTCFG72_TIMER30 = 6
, TIMER_OUTCFG18_OUTCFG72_TIMER31 = 7
,
TIMER_OUTCFG18_OUTCFG72_TIMER40 = 8
, TIMER_OUTCFG18_OUTCFG72_TIMER41 = 9
, TIMER_OUTCFG18_OUTCFG72_TIMER50 = 10
, TIMER_OUTCFG18_OUTCFG72_TIMER51 = 11
,
TIMER_OUTCFG18_OUTCFG72_TIMER60 = 12
, TIMER_OUTCFG18_OUTCFG72_TIMER61 = 13
, TIMER_OUTCFG18_OUTCFG72_TIMER70 = 14
, TIMER_OUTCFG18_OUTCFG72_TIMER71 = 15
,
TIMER_OUTCFG18_OUTCFG72_TIMER80 = 16
, TIMER_OUTCFG18_OUTCFG72_TIMER81 = 17
, TIMER_OUTCFG18_OUTCFG72_TIMER90 = 18
, TIMER_OUTCFG18_OUTCFG72_TIMER91 = 19
,
TIMER_OUTCFG18_OUTCFG72_TIMER100 = 20
, TIMER_OUTCFG18_OUTCFG72_TIMER101 = 21
, TIMER_OUTCFG18_OUTCFG72_TIMER110 = 22
, TIMER_OUTCFG18_OUTCFG72_TIMER111 = 23
,
TIMER_OUTCFG18_OUTCFG72_TIMER120 = 24
, TIMER_OUTCFG18_OUTCFG72_TIMER121 = 25
, TIMER_OUTCFG18_OUTCFG72_TIMER130 = 26
, TIMER_OUTCFG18_OUTCFG72_TIMER131 = 27
,
TIMER_OUTCFG18_OUTCFG72_TIMER140 = 28
, TIMER_OUTCFG18_OUTCFG72_TIMER141 = 29
, TIMER_OUTCFG18_OUTCFG72_TIMER150 = 30
, TIMER_OUTCFG18_OUTCFG72_TIMER151 = 31
,
TIMER_OUTCFG18_OUTCFG72_STIMER0 = 32
, TIMER_OUTCFG18_OUTCFG72_STIMER1 = 33
, TIMER_OUTCFG18_OUTCFG72_STIMER2 = 34
, TIMER_OUTCFG18_OUTCFG72_STIMER3 = 35
,
TIMER_OUTCFG18_OUTCFG72_STIMER4 = 36
, TIMER_OUTCFG18_OUTCFG72_STIMER5 = 37
, TIMER_OUTCFG18_OUTCFG72_STIMER6 = 38
, TIMER_OUTCFG18_OUTCFG72_STIMER7 = 39
,
TIMER_OUTCFG18_OUTCFG72_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG19_OUTCFG79_Enum {
TIMER_OUTCFG19_OUTCFG79_TIMER00 = 0
, TIMER_OUTCFG19_OUTCFG79_TIMER01 = 1
, TIMER_OUTCFG19_OUTCFG79_TIMER10 = 2
, TIMER_OUTCFG19_OUTCFG79_TIMER11 = 3
,
TIMER_OUTCFG19_OUTCFG79_TIMER20 = 4
, TIMER_OUTCFG19_OUTCFG79_TIMER21 = 5
, TIMER_OUTCFG19_OUTCFG79_TIMER30 = 6
, TIMER_OUTCFG19_OUTCFG79_TIMER31 = 7
,
TIMER_OUTCFG19_OUTCFG79_TIMER40 = 8
, TIMER_OUTCFG19_OUTCFG79_TIMER41 = 9
, TIMER_OUTCFG19_OUTCFG79_TIMER50 = 10
, TIMER_OUTCFG19_OUTCFG79_TIMER51 = 11
,
TIMER_OUTCFG19_OUTCFG79_TIMER60 = 12
, TIMER_OUTCFG19_OUTCFG79_TIMER61 = 13
, TIMER_OUTCFG19_OUTCFG79_TIMER70 = 14
, TIMER_OUTCFG19_OUTCFG79_TIMER71 = 15
,
TIMER_OUTCFG19_OUTCFG79_TIMER80 = 16
, TIMER_OUTCFG19_OUTCFG79_TIMER81 = 17
, TIMER_OUTCFG19_OUTCFG79_TIMER90 = 18
, TIMER_OUTCFG19_OUTCFG79_TIMER91 = 19
,
TIMER_OUTCFG19_OUTCFG79_TIMER100 = 20
, TIMER_OUTCFG19_OUTCFG79_TIMER101 = 21
, TIMER_OUTCFG19_OUTCFG79_TIMER110 = 22
, TIMER_OUTCFG19_OUTCFG79_TIMER111 = 23
,
TIMER_OUTCFG19_OUTCFG79_TIMER120 = 24
, TIMER_OUTCFG19_OUTCFG79_TIMER121 = 25
, TIMER_OUTCFG19_OUTCFG79_TIMER130 = 26
, TIMER_OUTCFG19_OUTCFG79_TIMER131 = 27
,
TIMER_OUTCFG19_OUTCFG79_TIMER140 = 28
, TIMER_OUTCFG19_OUTCFG79_TIMER141 = 29
, TIMER_OUTCFG19_OUTCFG79_TIMER150 = 30
, TIMER_OUTCFG19_OUTCFG79_TIMER151 = 31
,
TIMER_OUTCFG19_OUTCFG79_STIMER0 = 32
, TIMER_OUTCFG19_OUTCFG79_STIMER1 = 33
, TIMER_OUTCFG19_OUTCFG79_STIMER2 = 34
, TIMER_OUTCFG19_OUTCFG79_STIMER3 = 35
,
TIMER_OUTCFG19_OUTCFG79_STIMER4 = 36
, TIMER_OUTCFG19_OUTCFG79_STIMER5 = 37
, TIMER_OUTCFG19_OUTCFG79_STIMER6 = 38
, TIMER_OUTCFG19_OUTCFG79_STIMER7 = 39
,
TIMER_OUTCFG19_OUTCFG79_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG19_OUTCFG78_Enum {
TIMER_OUTCFG19_OUTCFG78_TIMER00 = 0
, TIMER_OUTCFG19_OUTCFG78_TIMER01 = 1
, TIMER_OUTCFG19_OUTCFG78_TIMER10 = 2
, TIMER_OUTCFG19_OUTCFG78_TIMER11 = 3
,
TIMER_OUTCFG19_OUTCFG78_TIMER20 = 4
, TIMER_OUTCFG19_OUTCFG78_TIMER21 = 5
, TIMER_OUTCFG19_OUTCFG78_TIMER30 = 6
, TIMER_OUTCFG19_OUTCFG78_TIMER31 = 7
,
TIMER_OUTCFG19_OUTCFG78_TIMER40 = 8
, TIMER_OUTCFG19_OUTCFG78_TIMER41 = 9
, TIMER_OUTCFG19_OUTCFG78_TIMER50 = 10
, TIMER_OUTCFG19_OUTCFG78_TIMER51 = 11
,
TIMER_OUTCFG19_OUTCFG78_TIMER60 = 12
, TIMER_OUTCFG19_OUTCFG78_TIMER61 = 13
, TIMER_OUTCFG19_OUTCFG78_TIMER70 = 14
, TIMER_OUTCFG19_OUTCFG78_TIMER71 = 15
,
TIMER_OUTCFG19_OUTCFG78_TIMER80 = 16
, TIMER_OUTCFG19_OUTCFG78_TIMER81 = 17
, TIMER_OUTCFG19_OUTCFG78_TIMER90 = 18
, TIMER_OUTCFG19_OUTCFG78_TIMER91 = 19
,
TIMER_OUTCFG19_OUTCFG78_TIMER100 = 20
, TIMER_OUTCFG19_OUTCFG78_TIMER101 = 21
, TIMER_OUTCFG19_OUTCFG78_TIMER110 = 22
, TIMER_OUTCFG19_OUTCFG78_TIMER111 = 23
,
TIMER_OUTCFG19_OUTCFG78_TIMER120 = 24
, TIMER_OUTCFG19_OUTCFG78_TIMER121 = 25
, TIMER_OUTCFG19_OUTCFG78_TIMER130 = 26
, TIMER_OUTCFG19_OUTCFG78_TIMER131 = 27
,
TIMER_OUTCFG19_OUTCFG78_TIMER140 = 28
, TIMER_OUTCFG19_OUTCFG78_TIMER141 = 29
, TIMER_OUTCFG19_OUTCFG78_TIMER150 = 30
, TIMER_OUTCFG19_OUTCFG78_TIMER151 = 31
,
TIMER_OUTCFG19_OUTCFG78_STIMER0 = 32
, TIMER_OUTCFG19_OUTCFG78_STIMER1 = 33
, TIMER_OUTCFG19_OUTCFG78_STIMER2 = 34
, TIMER_OUTCFG19_OUTCFG78_STIMER3 = 35
,
TIMER_OUTCFG19_OUTCFG78_STIMER4 = 36
, TIMER_OUTCFG19_OUTCFG78_STIMER5 = 37
, TIMER_OUTCFG19_OUTCFG78_STIMER6 = 38
, TIMER_OUTCFG19_OUTCFG78_STIMER7 = 39
,
TIMER_OUTCFG19_OUTCFG78_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG19_OUTCFG77_Enum {
TIMER_OUTCFG19_OUTCFG77_TIMER00 = 0
, TIMER_OUTCFG19_OUTCFG77_TIMER01 = 1
, TIMER_OUTCFG19_OUTCFG77_TIMER10 = 2
, TIMER_OUTCFG19_OUTCFG77_TIMER11 = 3
,
TIMER_OUTCFG19_OUTCFG77_TIMER20 = 4
, TIMER_OUTCFG19_OUTCFG77_TIMER21 = 5
, TIMER_OUTCFG19_OUTCFG77_TIMER30 = 6
, TIMER_OUTCFG19_OUTCFG77_TIMER31 = 7
,
TIMER_OUTCFG19_OUTCFG77_TIMER40 = 8
, TIMER_OUTCFG19_OUTCFG77_TIMER41 = 9
, TIMER_OUTCFG19_OUTCFG77_TIMER50 = 10
, TIMER_OUTCFG19_OUTCFG77_TIMER51 = 11
,
TIMER_OUTCFG19_OUTCFG77_TIMER60 = 12
, TIMER_OUTCFG19_OUTCFG77_TIMER61 = 13
, TIMER_OUTCFG19_OUTCFG77_TIMER70 = 14
, TIMER_OUTCFG19_OUTCFG77_TIMER71 = 15
,
TIMER_OUTCFG19_OUTCFG77_TIMER80 = 16
, TIMER_OUTCFG19_OUTCFG77_TIMER81 = 17
, TIMER_OUTCFG19_OUTCFG77_TIMER90 = 18
, TIMER_OUTCFG19_OUTCFG77_TIMER91 = 19
,
TIMER_OUTCFG19_OUTCFG77_TIMER100 = 20
, TIMER_OUTCFG19_OUTCFG77_TIMER101 = 21
, TIMER_OUTCFG19_OUTCFG77_TIMER110 = 22
, TIMER_OUTCFG19_OUTCFG77_TIMER111 = 23
,
TIMER_OUTCFG19_OUTCFG77_TIMER120 = 24
, TIMER_OUTCFG19_OUTCFG77_TIMER121 = 25
, TIMER_OUTCFG19_OUTCFG77_TIMER130 = 26
, TIMER_OUTCFG19_OUTCFG77_TIMER131 = 27
,
TIMER_OUTCFG19_OUTCFG77_TIMER140 = 28
, TIMER_OUTCFG19_OUTCFG77_TIMER141 = 29
, TIMER_OUTCFG19_OUTCFG77_TIMER150 = 30
, TIMER_OUTCFG19_OUTCFG77_TIMER151 = 31
,
TIMER_OUTCFG19_OUTCFG77_STIMER0 = 32
, TIMER_OUTCFG19_OUTCFG77_STIMER1 = 33
, TIMER_OUTCFG19_OUTCFG77_STIMER2 = 34
, TIMER_OUTCFG19_OUTCFG77_STIMER3 = 35
,
TIMER_OUTCFG19_OUTCFG77_STIMER4 = 36
, TIMER_OUTCFG19_OUTCFG77_STIMER5 = 37
, TIMER_OUTCFG19_OUTCFG77_STIMER6 = 38
, TIMER_OUTCFG19_OUTCFG77_STIMER7 = 39
,
TIMER_OUTCFG19_OUTCFG77_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG19_OUTCFG76_Enum {
TIMER_OUTCFG19_OUTCFG76_TIMER00 = 0
, TIMER_OUTCFG19_OUTCFG76_TIMER01 = 1
, TIMER_OUTCFG19_OUTCFG76_TIMER10 = 2
, TIMER_OUTCFG19_OUTCFG76_TIMER11 = 3
,
TIMER_OUTCFG19_OUTCFG76_TIMER20 = 4
, TIMER_OUTCFG19_OUTCFG76_TIMER21 = 5
, TIMER_OUTCFG19_OUTCFG76_TIMER30 = 6
, TIMER_OUTCFG19_OUTCFG76_TIMER31 = 7
,
TIMER_OUTCFG19_OUTCFG76_TIMER40 = 8
, TIMER_OUTCFG19_OUTCFG76_TIMER41 = 9
, TIMER_OUTCFG19_OUTCFG76_TIMER50 = 10
, TIMER_OUTCFG19_OUTCFG76_TIMER51 = 11
,
TIMER_OUTCFG19_OUTCFG76_TIMER60 = 12
, TIMER_OUTCFG19_OUTCFG76_TIMER61 = 13
, TIMER_OUTCFG19_OUTCFG76_TIMER70 = 14
, TIMER_OUTCFG19_OUTCFG76_TIMER71 = 15
,
TIMER_OUTCFG19_OUTCFG76_TIMER80 = 16
, TIMER_OUTCFG19_OUTCFG76_TIMER81 = 17
, TIMER_OUTCFG19_OUTCFG76_TIMER90 = 18
, TIMER_OUTCFG19_OUTCFG76_TIMER91 = 19
,
TIMER_OUTCFG19_OUTCFG76_TIMER100 = 20
, TIMER_OUTCFG19_OUTCFG76_TIMER101 = 21
, TIMER_OUTCFG19_OUTCFG76_TIMER110 = 22
, TIMER_OUTCFG19_OUTCFG76_TIMER111 = 23
,
TIMER_OUTCFG19_OUTCFG76_TIMER120 = 24
, TIMER_OUTCFG19_OUTCFG76_TIMER121 = 25
, TIMER_OUTCFG19_OUTCFG76_TIMER130 = 26
, TIMER_OUTCFG19_OUTCFG76_TIMER131 = 27
,
TIMER_OUTCFG19_OUTCFG76_TIMER140 = 28
, TIMER_OUTCFG19_OUTCFG76_TIMER141 = 29
, TIMER_OUTCFG19_OUTCFG76_TIMER150 = 30
, TIMER_OUTCFG19_OUTCFG76_TIMER151 = 31
,
TIMER_OUTCFG19_OUTCFG76_STIMER0 = 32
, TIMER_OUTCFG19_OUTCFG76_STIMER1 = 33
, TIMER_OUTCFG19_OUTCFG76_STIMER2 = 34
, TIMER_OUTCFG19_OUTCFG76_STIMER3 = 35
,
TIMER_OUTCFG19_OUTCFG76_STIMER4 = 36
, TIMER_OUTCFG19_OUTCFG76_STIMER5 = 37
, TIMER_OUTCFG19_OUTCFG76_STIMER6 = 38
, TIMER_OUTCFG19_OUTCFG76_STIMER7 = 39
,
TIMER_OUTCFG19_OUTCFG76_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG20_OUTCFG83_Enum {
TIMER_OUTCFG20_OUTCFG83_TIMER00 = 0
, TIMER_OUTCFG20_OUTCFG83_TIMER01 = 1
, TIMER_OUTCFG20_OUTCFG83_TIMER10 = 2
, TIMER_OUTCFG20_OUTCFG83_TIMER11 = 3
,
TIMER_OUTCFG20_OUTCFG83_TIMER20 = 4
, TIMER_OUTCFG20_OUTCFG83_TIMER21 = 5
, TIMER_OUTCFG20_OUTCFG83_TIMER30 = 6
, TIMER_OUTCFG20_OUTCFG83_TIMER31 = 7
,
TIMER_OUTCFG20_OUTCFG83_TIMER40 = 8
, TIMER_OUTCFG20_OUTCFG83_TIMER41 = 9
, TIMER_OUTCFG20_OUTCFG83_TIMER50 = 10
, TIMER_OUTCFG20_OUTCFG83_TIMER51 = 11
,
TIMER_OUTCFG20_OUTCFG83_TIMER60 = 12
, TIMER_OUTCFG20_OUTCFG83_TIMER61 = 13
, TIMER_OUTCFG20_OUTCFG83_TIMER70 = 14
, TIMER_OUTCFG20_OUTCFG83_TIMER71 = 15
,
TIMER_OUTCFG20_OUTCFG83_TIMER80 = 16
, TIMER_OUTCFG20_OUTCFG83_TIMER81 = 17
, TIMER_OUTCFG20_OUTCFG83_TIMER90 = 18
, TIMER_OUTCFG20_OUTCFG83_TIMER91 = 19
,
TIMER_OUTCFG20_OUTCFG83_TIMER100 = 20
, TIMER_OUTCFG20_OUTCFG83_TIMER101 = 21
, TIMER_OUTCFG20_OUTCFG83_TIMER110 = 22
, TIMER_OUTCFG20_OUTCFG83_TIMER111 = 23
,
TIMER_OUTCFG20_OUTCFG83_TIMER120 = 24
, TIMER_OUTCFG20_OUTCFG83_TIMER121 = 25
, TIMER_OUTCFG20_OUTCFG83_TIMER130 = 26
, TIMER_OUTCFG20_OUTCFG83_TIMER131 = 27
,
TIMER_OUTCFG20_OUTCFG83_TIMER140 = 28
, TIMER_OUTCFG20_OUTCFG83_TIMER141 = 29
, TIMER_OUTCFG20_OUTCFG83_TIMER150 = 30
, TIMER_OUTCFG20_OUTCFG83_TIMER151 = 31
,
TIMER_OUTCFG20_OUTCFG83_STIMER0 = 32
, TIMER_OUTCFG20_OUTCFG83_STIMER1 = 33
, TIMER_OUTCFG20_OUTCFG83_STIMER2 = 34
, TIMER_OUTCFG20_OUTCFG83_STIMER3 = 35
,
TIMER_OUTCFG20_OUTCFG83_STIMER4 = 36
, TIMER_OUTCFG20_OUTCFG83_STIMER5 = 37
, TIMER_OUTCFG20_OUTCFG83_STIMER6 = 38
, TIMER_OUTCFG20_OUTCFG83_STIMER7 = 39
,
TIMER_OUTCFG20_OUTCFG83_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG20_OUTCFG82_Enum {
TIMER_OUTCFG20_OUTCFG82_TIMER00 = 0
, TIMER_OUTCFG20_OUTCFG82_TIMER01 = 1
, TIMER_OUTCFG20_OUTCFG82_TIMER10 = 2
, TIMER_OUTCFG20_OUTCFG82_TIMER11 = 3
,
TIMER_OUTCFG20_OUTCFG82_TIMER20 = 4
, TIMER_OUTCFG20_OUTCFG82_TIMER21 = 5
, TIMER_OUTCFG20_OUTCFG82_TIMER30 = 6
, TIMER_OUTCFG20_OUTCFG82_TIMER31 = 7
,
TIMER_OUTCFG20_OUTCFG82_TIMER40 = 8
, TIMER_OUTCFG20_OUTCFG82_TIMER41 = 9
, TIMER_OUTCFG20_OUTCFG82_TIMER50 = 10
, TIMER_OUTCFG20_OUTCFG82_TIMER51 = 11
,
TIMER_OUTCFG20_OUTCFG82_TIMER60 = 12
, TIMER_OUTCFG20_OUTCFG82_TIMER61 = 13
, TIMER_OUTCFG20_OUTCFG82_TIMER70 = 14
, TIMER_OUTCFG20_OUTCFG82_TIMER71 = 15
,
TIMER_OUTCFG20_OUTCFG82_TIMER80 = 16
, TIMER_OUTCFG20_OUTCFG82_TIMER81 = 17
, TIMER_OUTCFG20_OUTCFG82_TIMER90 = 18
, TIMER_OUTCFG20_OUTCFG82_TIMER91 = 19
,
TIMER_OUTCFG20_OUTCFG82_TIMER100 = 20
, TIMER_OUTCFG20_OUTCFG82_TIMER101 = 21
, TIMER_OUTCFG20_OUTCFG82_TIMER110 = 22
, TIMER_OUTCFG20_OUTCFG82_TIMER111 = 23
,
TIMER_OUTCFG20_OUTCFG82_TIMER120 = 24
, TIMER_OUTCFG20_OUTCFG82_TIMER121 = 25
, TIMER_OUTCFG20_OUTCFG82_TIMER130 = 26
, TIMER_OUTCFG20_OUTCFG82_TIMER131 = 27
,
TIMER_OUTCFG20_OUTCFG82_TIMER140 = 28
, TIMER_OUTCFG20_OUTCFG82_TIMER141 = 29
, TIMER_OUTCFG20_OUTCFG82_TIMER150 = 30
, TIMER_OUTCFG20_OUTCFG82_TIMER151 = 31
,
TIMER_OUTCFG20_OUTCFG82_STIMER0 = 32
, TIMER_OUTCFG20_OUTCFG82_STIMER1 = 33
, TIMER_OUTCFG20_OUTCFG82_STIMER2 = 34
, TIMER_OUTCFG20_OUTCFG82_STIMER3 = 35
,
TIMER_OUTCFG20_OUTCFG82_STIMER4 = 36
, TIMER_OUTCFG20_OUTCFG82_STIMER5 = 37
, TIMER_OUTCFG20_OUTCFG82_STIMER6 = 38
, TIMER_OUTCFG20_OUTCFG82_STIMER7 = 39
,
TIMER_OUTCFG20_OUTCFG82_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG20_OUTCFG81_Enum {
TIMER_OUTCFG20_OUTCFG81_TIMER00 = 0
, TIMER_OUTCFG20_OUTCFG81_TIMER01 = 1
, TIMER_OUTCFG20_OUTCFG81_TIMER10 = 2
, TIMER_OUTCFG20_OUTCFG81_TIMER11 = 3
,
TIMER_OUTCFG20_OUTCFG81_TIMER20 = 4
, TIMER_OUTCFG20_OUTCFG81_TIMER21 = 5
, TIMER_OUTCFG20_OUTCFG81_TIMER30 = 6
, TIMER_OUTCFG20_OUTCFG81_TIMER31 = 7
,
TIMER_OUTCFG20_OUTCFG81_TIMER40 = 8
, TIMER_OUTCFG20_OUTCFG81_TIMER41 = 9
, TIMER_OUTCFG20_OUTCFG81_TIMER50 = 10
, TIMER_OUTCFG20_OUTCFG81_TIMER51 = 11
,
TIMER_OUTCFG20_OUTCFG81_TIMER60 = 12
, TIMER_OUTCFG20_OUTCFG81_TIMER61 = 13
, TIMER_OUTCFG20_OUTCFG81_TIMER70 = 14
, TIMER_OUTCFG20_OUTCFG81_TIMER71 = 15
,
TIMER_OUTCFG20_OUTCFG81_TIMER80 = 16
, TIMER_OUTCFG20_OUTCFG81_TIMER81 = 17
, TIMER_OUTCFG20_OUTCFG81_TIMER90 = 18
, TIMER_OUTCFG20_OUTCFG81_TIMER91 = 19
,
TIMER_OUTCFG20_OUTCFG81_TIMER100 = 20
, TIMER_OUTCFG20_OUTCFG81_TIMER101 = 21
, TIMER_OUTCFG20_OUTCFG81_TIMER110 = 22
, TIMER_OUTCFG20_OUTCFG81_TIMER111 = 23
,
TIMER_OUTCFG20_OUTCFG81_TIMER120 = 24
, TIMER_OUTCFG20_OUTCFG81_TIMER121 = 25
, TIMER_OUTCFG20_OUTCFG81_TIMER130 = 26
, TIMER_OUTCFG20_OUTCFG81_TIMER131 = 27
,
TIMER_OUTCFG20_OUTCFG81_TIMER140 = 28
, TIMER_OUTCFG20_OUTCFG81_TIMER141 = 29
, TIMER_OUTCFG20_OUTCFG81_TIMER150 = 30
, TIMER_OUTCFG20_OUTCFG81_TIMER151 = 31
,
TIMER_OUTCFG20_OUTCFG81_STIMER0 = 32
, TIMER_OUTCFG20_OUTCFG81_STIMER1 = 33
, TIMER_OUTCFG20_OUTCFG81_STIMER2 = 34
, TIMER_OUTCFG20_OUTCFG81_STIMER3 = 35
,
TIMER_OUTCFG20_OUTCFG81_STIMER4 = 36
, TIMER_OUTCFG20_OUTCFG81_STIMER5 = 37
, TIMER_OUTCFG20_OUTCFG81_STIMER6 = 38
, TIMER_OUTCFG20_OUTCFG81_STIMER7 = 39
,
TIMER_OUTCFG20_OUTCFG81_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG20_OUTCFG80_Enum {
TIMER_OUTCFG20_OUTCFG80_TIMER00 = 0
, TIMER_OUTCFG20_OUTCFG80_TIMER01 = 1
, TIMER_OUTCFG20_OUTCFG80_TIMER10 = 2
, TIMER_OUTCFG20_OUTCFG80_TIMER11 = 3
,
TIMER_OUTCFG20_OUTCFG80_TIMER20 = 4
, TIMER_OUTCFG20_OUTCFG80_TIMER21 = 5
, TIMER_OUTCFG20_OUTCFG80_TIMER30 = 6
, TIMER_OUTCFG20_OUTCFG80_TIMER31 = 7
,
TIMER_OUTCFG20_OUTCFG80_TIMER40 = 8
, TIMER_OUTCFG20_OUTCFG80_TIMER41 = 9
, TIMER_OUTCFG20_OUTCFG80_TIMER50 = 10
, TIMER_OUTCFG20_OUTCFG80_TIMER51 = 11
,
TIMER_OUTCFG20_OUTCFG80_TIMER60 = 12
, TIMER_OUTCFG20_OUTCFG80_TIMER61 = 13
, TIMER_OUTCFG20_OUTCFG80_TIMER70 = 14
, TIMER_OUTCFG20_OUTCFG80_TIMER71 = 15
,
TIMER_OUTCFG20_OUTCFG80_TIMER80 = 16
, TIMER_OUTCFG20_OUTCFG80_TIMER81 = 17
, TIMER_OUTCFG20_OUTCFG80_TIMER90 = 18
, TIMER_OUTCFG20_OUTCFG80_TIMER91 = 19
,
TIMER_OUTCFG20_OUTCFG80_TIMER100 = 20
, TIMER_OUTCFG20_OUTCFG80_TIMER101 = 21
, TIMER_OUTCFG20_OUTCFG80_TIMER110 = 22
, TIMER_OUTCFG20_OUTCFG80_TIMER111 = 23
,
TIMER_OUTCFG20_OUTCFG80_TIMER120 = 24
, TIMER_OUTCFG20_OUTCFG80_TIMER121 = 25
, TIMER_OUTCFG20_OUTCFG80_TIMER130 = 26
, TIMER_OUTCFG20_OUTCFG80_TIMER131 = 27
,
TIMER_OUTCFG20_OUTCFG80_TIMER140 = 28
, TIMER_OUTCFG20_OUTCFG80_TIMER141 = 29
, TIMER_OUTCFG20_OUTCFG80_TIMER150 = 30
, TIMER_OUTCFG20_OUTCFG80_TIMER151 = 31
,
TIMER_OUTCFG20_OUTCFG80_STIMER0 = 32
, TIMER_OUTCFG20_OUTCFG80_STIMER1 = 33
, TIMER_OUTCFG20_OUTCFG80_STIMER2 = 34
, TIMER_OUTCFG20_OUTCFG80_STIMER3 = 35
,
TIMER_OUTCFG20_OUTCFG80_STIMER4 = 36
, TIMER_OUTCFG20_OUTCFG80_STIMER5 = 37
, TIMER_OUTCFG20_OUTCFG80_STIMER6 = 38
, TIMER_OUTCFG20_OUTCFG80_STIMER7 = 39
,
TIMER_OUTCFG20_OUTCFG80_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG21_OUTCFG87_Enum {
TIMER_OUTCFG21_OUTCFG87_TIMER00 = 0
, TIMER_OUTCFG21_OUTCFG87_TIMER01 = 1
, TIMER_OUTCFG21_OUTCFG87_TIMER10 = 2
, TIMER_OUTCFG21_OUTCFG87_TIMER11 = 3
,
TIMER_OUTCFG21_OUTCFG87_TIMER20 = 4
, TIMER_OUTCFG21_OUTCFG87_TIMER21 = 5
, TIMER_OUTCFG21_OUTCFG87_TIMER30 = 6
, TIMER_OUTCFG21_OUTCFG87_TIMER31 = 7
,
TIMER_OUTCFG21_OUTCFG87_TIMER40 = 8
, TIMER_OUTCFG21_OUTCFG87_TIMER41 = 9
, TIMER_OUTCFG21_OUTCFG87_TIMER50 = 10
, TIMER_OUTCFG21_OUTCFG87_TIMER51 = 11
,
TIMER_OUTCFG21_OUTCFG87_TIMER60 = 12
, TIMER_OUTCFG21_OUTCFG87_TIMER61 = 13
, TIMER_OUTCFG21_OUTCFG87_TIMER70 = 14
, TIMER_OUTCFG21_OUTCFG87_TIMER71 = 15
,
TIMER_OUTCFG21_OUTCFG87_TIMER80 = 16
, TIMER_OUTCFG21_OUTCFG87_TIMER81 = 17
, TIMER_OUTCFG21_OUTCFG87_TIMER90 = 18
, TIMER_OUTCFG21_OUTCFG87_TIMER91 = 19
,
TIMER_OUTCFG21_OUTCFG87_TIMER100 = 20
, TIMER_OUTCFG21_OUTCFG87_TIMER101 = 21
, TIMER_OUTCFG21_OUTCFG87_TIMER110 = 22
, TIMER_OUTCFG21_OUTCFG87_TIMER111 = 23
,
TIMER_OUTCFG21_OUTCFG87_TIMER120 = 24
, TIMER_OUTCFG21_OUTCFG87_TIMER121 = 25
, TIMER_OUTCFG21_OUTCFG87_TIMER130 = 26
, TIMER_OUTCFG21_OUTCFG87_TIMER131 = 27
,
TIMER_OUTCFG21_OUTCFG87_TIMER140 = 28
, TIMER_OUTCFG21_OUTCFG87_TIMER141 = 29
, TIMER_OUTCFG21_OUTCFG87_TIMER150 = 30
, TIMER_OUTCFG21_OUTCFG87_TIMER151 = 31
,
TIMER_OUTCFG21_OUTCFG87_STIMER0 = 32
, TIMER_OUTCFG21_OUTCFG87_STIMER1 = 33
, TIMER_OUTCFG21_OUTCFG87_STIMER2 = 34
, TIMER_OUTCFG21_OUTCFG87_STIMER3 = 35
,
TIMER_OUTCFG21_OUTCFG87_STIMER4 = 36
, TIMER_OUTCFG21_OUTCFG87_STIMER5 = 37
, TIMER_OUTCFG21_OUTCFG87_STIMER6 = 38
, TIMER_OUTCFG21_OUTCFG87_STIMER7 = 39
,
TIMER_OUTCFG21_OUTCFG87_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG21_OUTCFG86_Enum {
TIMER_OUTCFG21_OUTCFG86_TIMER00 = 0
, TIMER_OUTCFG21_OUTCFG86_TIMER01 = 1
, TIMER_OUTCFG21_OUTCFG86_TIMER10 = 2
, TIMER_OUTCFG21_OUTCFG86_TIMER11 = 3
,
TIMER_OUTCFG21_OUTCFG86_TIMER20 = 4
, TIMER_OUTCFG21_OUTCFG86_TIMER21 = 5
, TIMER_OUTCFG21_OUTCFG86_TIMER30 = 6
, TIMER_OUTCFG21_OUTCFG86_TIMER31 = 7
,
TIMER_OUTCFG21_OUTCFG86_TIMER40 = 8
, TIMER_OUTCFG21_OUTCFG86_TIMER41 = 9
, TIMER_OUTCFG21_OUTCFG86_TIMER50 = 10
, TIMER_OUTCFG21_OUTCFG86_TIMER51 = 11
,
TIMER_OUTCFG21_OUTCFG86_TIMER60 = 12
, TIMER_OUTCFG21_OUTCFG86_TIMER61 = 13
, TIMER_OUTCFG21_OUTCFG86_TIMER70 = 14
, TIMER_OUTCFG21_OUTCFG86_TIMER71 = 15
,
TIMER_OUTCFG21_OUTCFG86_TIMER80 = 16
, TIMER_OUTCFG21_OUTCFG86_TIMER81 = 17
, TIMER_OUTCFG21_OUTCFG86_TIMER90 = 18
, TIMER_OUTCFG21_OUTCFG86_TIMER91 = 19
,
TIMER_OUTCFG21_OUTCFG86_TIMER100 = 20
, TIMER_OUTCFG21_OUTCFG86_TIMER101 = 21
, TIMER_OUTCFG21_OUTCFG86_TIMER110 = 22
, TIMER_OUTCFG21_OUTCFG86_TIMER111 = 23
,
TIMER_OUTCFG21_OUTCFG86_TIMER120 = 24
, TIMER_OUTCFG21_OUTCFG86_TIMER121 = 25
, TIMER_OUTCFG21_OUTCFG86_TIMER130 = 26
, TIMER_OUTCFG21_OUTCFG86_TIMER131 = 27
,
TIMER_OUTCFG21_OUTCFG86_TIMER140 = 28
, TIMER_OUTCFG21_OUTCFG86_TIMER141 = 29
, TIMER_OUTCFG21_OUTCFG86_TIMER150 = 30
, TIMER_OUTCFG21_OUTCFG86_TIMER151 = 31
,
TIMER_OUTCFG21_OUTCFG86_STIMER0 = 32
, TIMER_OUTCFG21_OUTCFG86_STIMER1 = 33
, TIMER_OUTCFG21_OUTCFG86_STIMER2 = 34
, TIMER_OUTCFG21_OUTCFG86_STIMER3 = 35
,
TIMER_OUTCFG21_OUTCFG86_STIMER4 = 36
, TIMER_OUTCFG21_OUTCFG86_STIMER5 = 37
, TIMER_OUTCFG21_OUTCFG86_STIMER6 = 38
, TIMER_OUTCFG21_OUTCFG86_STIMER7 = 39
,
TIMER_OUTCFG21_OUTCFG86_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG21_OUTCFG85_Enum {
TIMER_OUTCFG21_OUTCFG85_TIMER00 = 0
, TIMER_OUTCFG21_OUTCFG85_TIMER01 = 1
, TIMER_OUTCFG21_OUTCFG85_TIMER10 = 2
, TIMER_OUTCFG21_OUTCFG85_TIMER11 = 3
,
TIMER_OUTCFG21_OUTCFG85_TIMER20 = 4
, TIMER_OUTCFG21_OUTCFG85_TIMER21 = 5
, TIMER_OUTCFG21_OUTCFG85_TIMER30 = 6
, TIMER_OUTCFG21_OUTCFG85_TIMER31 = 7
,
TIMER_OUTCFG21_OUTCFG85_TIMER40 = 8
, TIMER_OUTCFG21_OUTCFG85_TIMER41 = 9
, TIMER_OUTCFG21_OUTCFG85_TIMER50 = 10
, TIMER_OUTCFG21_OUTCFG85_TIMER51 = 11
,
TIMER_OUTCFG21_OUTCFG85_TIMER60 = 12
, TIMER_OUTCFG21_OUTCFG85_TIMER61 = 13
, TIMER_OUTCFG21_OUTCFG85_TIMER70 = 14
, TIMER_OUTCFG21_OUTCFG85_TIMER71 = 15
,
TIMER_OUTCFG21_OUTCFG85_TIMER80 = 16
, TIMER_OUTCFG21_OUTCFG85_TIMER81 = 17
, TIMER_OUTCFG21_OUTCFG85_TIMER90 = 18
, TIMER_OUTCFG21_OUTCFG85_TIMER91 = 19
,
TIMER_OUTCFG21_OUTCFG85_TIMER100 = 20
, TIMER_OUTCFG21_OUTCFG85_TIMER101 = 21
, TIMER_OUTCFG21_OUTCFG85_TIMER110 = 22
, TIMER_OUTCFG21_OUTCFG85_TIMER111 = 23
,
TIMER_OUTCFG21_OUTCFG85_TIMER120 = 24
, TIMER_OUTCFG21_OUTCFG85_TIMER121 = 25
, TIMER_OUTCFG21_OUTCFG85_TIMER130 = 26
, TIMER_OUTCFG21_OUTCFG85_TIMER131 = 27
,
TIMER_OUTCFG21_OUTCFG85_TIMER140 = 28
, TIMER_OUTCFG21_OUTCFG85_TIMER141 = 29
, TIMER_OUTCFG21_OUTCFG85_TIMER150 = 30
, TIMER_OUTCFG21_OUTCFG85_TIMER151 = 31
,
TIMER_OUTCFG21_OUTCFG85_STIMER0 = 32
, TIMER_OUTCFG21_OUTCFG85_STIMER1 = 33
, TIMER_OUTCFG21_OUTCFG85_STIMER2 = 34
, TIMER_OUTCFG21_OUTCFG85_STIMER3 = 35
,
TIMER_OUTCFG21_OUTCFG85_STIMER4 = 36
, TIMER_OUTCFG21_OUTCFG85_STIMER5 = 37
, TIMER_OUTCFG21_OUTCFG85_STIMER6 = 38
, TIMER_OUTCFG21_OUTCFG85_STIMER7 = 39
,
TIMER_OUTCFG21_OUTCFG85_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG21_OUTCFG84_Enum {
TIMER_OUTCFG21_OUTCFG84_TIMER00 = 0
, TIMER_OUTCFG21_OUTCFG84_TIMER01 = 1
, TIMER_OUTCFG21_OUTCFG84_TIMER10 = 2
, TIMER_OUTCFG21_OUTCFG84_TIMER11 = 3
,
TIMER_OUTCFG21_OUTCFG84_TIMER20 = 4
, TIMER_OUTCFG21_OUTCFG84_TIMER21 = 5
, TIMER_OUTCFG21_OUTCFG84_TIMER30 = 6
, TIMER_OUTCFG21_OUTCFG84_TIMER31 = 7
,
TIMER_OUTCFG21_OUTCFG84_TIMER40 = 8
, TIMER_OUTCFG21_OUTCFG84_TIMER41 = 9
, TIMER_OUTCFG21_OUTCFG84_TIMER50 = 10
, TIMER_OUTCFG21_OUTCFG84_TIMER51 = 11
,
TIMER_OUTCFG21_OUTCFG84_TIMER60 = 12
, TIMER_OUTCFG21_OUTCFG84_TIMER61 = 13
, TIMER_OUTCFG21_OUTCFG84_TIMER70 = 14
, TIMER_OUTCFG21_OUTCFG84_TIMER71 = 15
,
TIMER_OUTCFG21_OUTCFG84_TIMER80 = 16
, TIMER_OUTCFG21_OUTCFG84_TIMER81 = 17
, TIMER_OUTCFG21_OUTCFG84_TIMER90 = 18
, TIMER_OUTCFG21_OUTCFG84_TIMER91 = 19
,
TIMER_OUTCFG21_OUTCFG84_TIMER100 = 20
, TIMER_OUTCFG21_OUTCFG84_TIMER101 = 21
, TIMER_OUTCFG21_OUTCFG84_TIMER110 = 22
, TIMER_OUTCFG21_OUTCFG84_TIMER111 = 23
,
TIMER_OUTCFG21_OUTCFG84_TIMER120 = 24
, TIMER_OUTCFG21_OUTCFG84_TIMER121 = 25
, TIMER_OUTCFG21_OUTCFG84_TIMER130 = 26
, TIMER_OUTCFG21_OUTCFG84_TIMER131 = 27
,
TIMER_OUTCFG21_OUTCFG84_TIMER140 = 28
, TIMER_OUTCFG21_OUTCFG84_TIMER141 = 29
, TIMER_OUTCFG21_OUTCFG84_TIMER150 = 30
, TIMER_OUTCFG21_OUTCFG84_TIMER151 = 31
,
TIMER_OUTCFG21_OUTCFG84_STIMER0 = 32
, TIMER_OUTCFG21_OUTCFG84_STIMER1 = 33
, TIMER_OUTCFG21_OUTCFG84_STIMER2 = 34
, TIMER_OUTCFG21_OUTCFG84_STIMER3 = 35
,
TIMER_OUTCFG21_OUTCFG84_STIMER4 = 36
, TIMER_OUTCFG21_OUTCFG84_STIMER5 = 37
, TIMER_OUTCFG21_OUTCFG84_STIMER6 = 38
, TIMER_OUTCFG21_OUTCFG84_STIMER7 = 39
,
TIMER_OUTCFG21_OUTCFG84_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG22_OUTCFG91_Enum {
TIMER_OUTCFG22_OUTCFG91_TIMER00 = 0
, TIMER_OUTCFG22_OUTCFG91_TIMER01 = 1
, TIMER_OUTCFG22_OUTCFG91_TIMER10 = 2
, TIMER_OUTCFG22_OUTCFG91_TIMER11 = 3
,
TIMER_OUTCFG22_OUTCFG91_TIMER20 = 4
, TIMER_OUTCFG22_OUTCFG91_TIMER21 = 5
, TIMER_OUTCFG22_OUTCFG91_TIMER30 = 6
, TIMER_OUTCFG22_OUTCFG91_TIMER31 = 7
,
TIMER_OUTCFG22_OUTCFG91_TIMER40 = 8
, TIMER_OUTCFG22_OUTCFG91_TIMER41 = 9
, TIMER_OUTCFG22_OUTCFG91_TIMER50 = 10
, TIMER_OUTCFG22_OUTCFG91_TIMER51 = 11
,
TIMER_OUTCFG22_OUTCFG91_TIMER60 = 12
, TIMER_OUTCFG22_OUTCFG91_TIMER61 = 13
, TIMER_OUTCFG22_OUTCFG91_TIMER70 = 14
, TIMER_OUTCFG22_OUTCFG91_TIMER71 = 15
,
TIMER_OUTCFG22_OUTCFG91_TIMER80 = 16
, TIMER_OUTCFG22_OUTCFG91_TIMER81 = 17
, TIMER_OUTCFG22_OUTCFG91_TIMER90 = 18
, TIMER_OUTCFG22_OUTCFG91_TIMER91 = 19
,
TIMER_OUTCFG22_OUTCFG91_TIMER100 = 20
, TIMER_OUTCFG22_OUTCFG91_TIMER101 = 21
, TIMER_OUTCFG22_OUTCFG91_TIMER110 = 22
, TIMER_OUTCFG22_OUTCFG91_TIMER111 = 23
,
TIMER_OUTCFG22_OUTCFG91_TIMER120 = 24
, TIMER_OUTCFG22_OUTCFG91_TIMER121 = 25
, TIMER_OUTCFG22_OUTCFG91_TIMER130 = 26
, TIMER_OUTCFG22_OUTCFG91_TIMER131 = 27
,
TIMER_OUTCFG22_OUTCFG91_TIMER140 = 28
, TIMER_OUTCFG22_OUTCFG91_TIMER141 = 29
, TIMER_OUTCFG22_OUTCFG91_TIMER150 = 30
, TIMER_OUTCFG22_OUTCFG91_TIMER151 = 31
,
TIMER_OUTCFG22_OUTCFG91_STIMER0 = 32
, TIMER_OUTCFG22_OUTCFG91_STIMER1 = 33
, TIMER_OUTCFG22_OUTCFG91_STIMER2 = 34
, TIMER_OUTCFG22_OUTCFG91_STIMER3 = 35
,
TIMER_OUTCFG22_OUTCFG91_STIMER4 = 36
, TIMER_OUTCFG22_OUTCFG91_STIMER5 = 37
, TIMER_OUTCFG22_OUTCFG91_STIMER6 = 38
, TIMER_OUTCFG22_OUTCFG91_STIMER7 = 39
,
TIMER_OUTCFG22_OUTCFG91_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG22_OUTCFG90_Enum {
TIMER_OUTCFG22_OUTCFG90_TIMER00 = 0
, TIMER_OUTCFG22_OUTCFG90_TIMER01 = 1
, TIMER_OUTCFG22_OUTCFG90_TIMER10 = 2
, TIMER_OUTCFG22_OUTCFG90_TIMER11 = 3
,
TIMER_OUTCFG22_OUTCFG90_TIMER20 = 4
, TIMER_OUTCFG22_OUTCFG90_TIMER21 = 5
, TIMER_OUTCFG22_OUTCFG90_TIMER30 = 6
, TIMER_OUTCFG22_OUTCFG90_TIMER31 = 7
,
TIMER_OUTCFG22_OUTCFG90_TIMER40 = 8
, TIMER_OUTCFG22_OUTCFG90_TIMER41 = 9
, TIMER_OUTCFG22_OUTCFG90_TIMER50 = 10
, TIMER_OUTCFG22_OUTCFG90_TIMER51 = 11
,
TIMER_OUTCFG22_OUTCFG90_TIMER60 = 12
, TIMER_OUTCFG22_OUTCFG90_TIMER61 = 13
, TIMER_OUTCFG22_OUTCFG90_TIMER70 = 14
, TIMER_OUTCFG22_OUTCFG90_TIMER71 = 15
,
TIMER_OUTCFG22_OUTCFG90_TIMER80 = 16
, TIMER_OUTCFG22_OUTCFG90_TIMER81 = 17
, TIMER_OUTCFG22_OUTCFG90_TIMER90 = 18
, TIMER_OUTCFG22_OUTCFG90_TIMER91 = 19
,
TIMER_OUTCFG22_OUTCFG90_TIMER100 = 20
, TIMER_OUTCFG22_OUTCFG90_TIMER101 = 21
, TIMER_OUTCFG22_OUTCFG90_TIMER110 = 22
, TIMER_OUTCFG22_OUTCFG90_TIMER111 = 23
,
TIMER_OUTCFG22_OUTCFG90_TIMER120 = 24
, TIMER_OUTCFG22_OUTCFG90_TIMER121 = 25
, TIMER_OUTCFG22_OUTCFG90_TIMER130 = 26
, TIMER_OUTCFG22_OUTCFG90_TIMER131 = 27
,
TIMER_OUTCFG22_OUTCFG90_TIMER140 = 28
, TIMER_OUTCFG22_OUTCFG90_TIMER141 = 29
, TIMER_OUTCFG22_OUTCFG90_TIMER150 = 30
, TIMER_OUTCFG22_OUTCFG90_TIMER151 = 31
,
TIMER_OUTCFG22_OUTCFG90_STIMER0 = 32
, TIMER_OUTCFG22_OUTCFG90_STIMER1 = 33
, TIMER_OUTCFG22_OUTCFG90_STIMER2 = 34
, TIMER_OUTCFG22_OUTCFG90_STIMER3 = 35
,
TIMER_OUTCFG22_OUTCFG90_STIMER4 = 36
, TIMER_OUTCFG22_OUTCFG90_STIMER5 = 37
, TIMER_OUTCFG22_OUTCFG90_STIMER6 = 38
, TIMER_OUTCFG22_OUTCFG90_STIMER7 = 39
,
TIMER_OUTCFG22_OUTCFG90_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG22_OUTCFG89_Enum {
TIMER_OUTCFG22_OUTCFG89_TIMER00 = 0
, TIMER_OUTCFG22_OUTCFG89_TIMER01 = 1
, TIMER_OUTCFG22_OUTCFG89_TIMER10 = 2
, TIMER_OUTCFG22_OUTCFG89_TIMER11 = 3
,
TIMER_OUTCFG22_OUTCFG89_TIMER20 = 4
, TIMER_OUTCFG22_OUTCFG89_TIMER21 = 5
, TIMER_OUTCFG22_OUTCFG89_TIMER30 = 6
, TIMER_OUTCFG22_OUTCFG89_TIMER31 = 7
,
TIMER_OUTCFG22_OUTCFG89_TIMER40 = 8
, TIMER_OUTCFG22_OUTCFG89_TIMER41 = 9
, TIMER_OUTCFG22_OUTCFG89_TIMER50 = 10
, TIMER_OUTCFG22_OUTCFG89_TIMER51 = 11
,
TIMER_OUTCFG22_OUTCFG89_TIMER60 = 12
, TIMER_OUTCFG22_OUTCFG89_TIMER61 = 13
, TIMER_OUTCFG22_OUTCFG89_TIMER70 = 14
, TIMER_OUTCFG22_OUTCFG89_TIMER71 = 15
,
TIMER_OUTCFG22_OUTCFG89_TIMER80 = 16
, TIMER_OUTCFG22_OUTCFG89_TIMER81 = 17
, TIMER_OUTCFG22_OUTCFG89_TIMER90 = 18
, TIMER_OUTCFG22_OUTCFG89_TIMER91 = 19
,
TIMER_OUTCFG22_OUTCFG89_TIMER100 = 20
, TIMER_OUTCFG22_OUTCFG89_TIMER101 = 21
, TIMER_OUTCFG22_OUTCFG89_TIMER110 = 22
, TIMER_OUTCFG22_OUTCFG89_TIMER111 = 23
,
TIMER_OUTCFG22_OUTCFG89_TIMER120 = 24
, TIMER_OUTCFG22_OUTCFG89_TIMER121 = 25
, TIMER_OUTCFG22_OUTCFG89_TIMER130 = 26
, TIMER_OUTCFG22_OUTCFG89_TIMER131 = 27
,
TIMER_OUTCFG22_OUTCFG89_TIMER140 = 28
, TIMER_OUTCFG22_OUTCFG89_TIMER141 = 29
, TIMER_OUTCFG22_OUTCFG89_TIMER150 = 30
, TIMER_OUTCFG22_OUTCFG89_TIMER151 = 31
,
TIMER_OUTCFG22_OUTCFG89_STIMER0 = 32
, TIMER_OUTCFG22_OUTCFG89_STIMER1 = 33
, TIMER_OUTCFG22_OUTCFG89_STIMER2 = 34
, TIMER_OUTCFG22_OUTCFG89_STIMER3 = 35
,
TIMER_OUTCFG22_OUTCFG89_STIMER4 = 36
, TIMER_OUTCFG22_OUTCFG89_STIMER5 = 37
, TIMER_OUTCFG22_OUTCFG89_STIMER6 = 38
, TIMER_OUTCFG22_OUTCFG89_STIMER7 = 39
,
TIMER_OUTCFG22_OUTCFG89_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG22_OUTCFG88_Enum {
TIMER_OUTCFG22_OUTCFG88_TIMER00 = 0
, TIMER_OUTCFG22_OUTCFG88_TIMER01 = 1
, TIMER_OUTCFG22_OUTCFG88_TIMER10 = 2
, TIMER_OUTCFG22_OUTCFG88_TIMER11 = 3
,
TIMER_OUTCFG22_OUTCFG88_TIMER20 = 4
, TIMER_OUTCFG22_OUTCFG88_TIMER21 = 5
, TIMER_OUTCFG22_OUTCFG88_TIMER30 = 6
, TIMER_OUTCFG22_OUTCFG88_TIMER31 = 7
,
TIMER_OUTCFG22_OUTCFG88_TIMER40 = 8
, TIMER_OUTCFG22_OUTCFG88_TIMER41 = 9
, TIMER_OUTCFG22_OUTCFG88_TIMER50 = 10
, TIMER_OUTCFG22_OUTCFG88_TIMER51 = 11
,
TIMER_OUTCFG22_OUTCFG88_TIMER60 = 12
, TIMER_OUTCFG22_OUTCFG88_TIMER61 = 13
, TIMER_OUTCFG22_OUTCFG88_TIMER70 = 14
, TIMER_OUTCFG22_OUTCFG88_TIMER71 = 15
,
TIMER_OUTCFG22_OUTCFG88_TIMER80 = 16
, TIMER_OUTCFG22_OUTCFG88_TIMER81 = 17
, TIMER_OUTCFG22_OUTCFG88_TIMER90 = 18
, TIMER_OUTCFG22_OUTCFG88_TIMER91 = 19
,
TIMER_OUTCFG22_OUTCFG88_TIMER100 = 20
, TIMER_OUTCFG22_OUTCFG88_TIMER101 = 21
, TIMER_OUTCFG22_OUTCFG88_TIMER110 = 22
, TIMER_OUTCFG22_OUTCFG88_TIMER111 = 23
,
TIMER_OUTCFG22_OUTCFG88_TIMER120 = 24
, TIMER_OUTCFG22_OUTCFG88_TIMER121 = 25
, TIMER_OUTCFG22_OUTCFG88_TIMER130 = 26
, TIMER_OUTCFG22_OUTCFG88_TIMER131 = 27
,
TIMER_OUTCFG22_OUTCFG88_TIMER140 = 28
, TIMER_OUTCFG22_OUTCFG88_TIMER141 = 29
, TIMER_OUTCFG22_OUTCFG88_TIMER150 = 30
, TIMER_OUTCFG22_OUTCFG88_TIMER151 = 31
,
TIMER_OUTCFG22_OUTCFG88_STIMER0 = 32
, TIMER_OUTCFG22_OUTCFG88_STIMER1 = 33
, TIMER_OUTCFG22_OUTCFG88_STIMER2 = 34
, TIMER_OUTCFG22_OUTCFG88_STIMER3 = 35
,
TIMER_OUTCFG22_OUTCFG88_STIMER4 = 36
, TIMER_OUTCFG22_OUTCFG88_STIMER5 = 37
, TIMER_OUTCFG22_OUTCFG88_STIMER6 = 38
, TIMER_OUTCFG22_OUTCFG88_STIMER7 = 39
,
TIMER_OUTCFG22_OUTCFG88_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG23_OUTCFG95_Enum {
TIMER_OUTCFG23_OUTCFG95_TIMER00 = 0
, TIMER_OUTCFG23_OUTCFG95_TIMER01 = 1
, TIMER_OUTCFG23_OUTCFG95_TIMER10 = 2
, TIMER_OUTCFG23_OUTCFG95_TIMER11 = 3
,
TIMER_OUTCFG23_OUTCFG95_TIMER20 = 4
, TIMER_OUTCFG23_OUTCFG95_TIMER21 = 5
, TIMER_OUTCFG23_OUTCFG95_TIMER30 = 6
, TIMER_OUTCFG23_OUTCFG95_TIMER31 = 7
,
TIMER_OUTCFG23_OUTCFG95_TIMER40 = 8
, TIMER_OUTCFG23_OUTCFG95_TIMER41 = 9
, TIMER_OUTCFG23_OUTCFG95_TIMER50 = 10
, TIMER_OUTCFG23_OUTCFG95_TIMER51 = 11
,
TIMER_OUTCFG23_OUTCFG95_TIMER60 = 12
, TIMER_OUTCFG23_OUTCFG95_TIMER61 = 13
, TIMER_OUTCFG23_OUTCFG95_TIMER70 = 14
, TIMER_OUTCFG23_OUTCFG95_TIMER71 = 15
,
TIMER_OUTCFG23_OUTCFG95_TIMER80 = 16
, TIMER_OUTCFG23_OUTCFG95_TIMER81 = 17
, TIMER_OUTCFG23_OUTCFG95_TIMER90 = 18
, TIMER_OUTCFG23_OUTCFG95_TIMER91 = 19
,
TIMER_OUTCFG23_OUTCFG95_TIMER100 = 20
, TIMER_OUTCFG23_OUTCFG95_TIMER101 = 21
, TIMER_OUTCFG23_OUTCFG95_TIMER110 = 22
, TIMER_OUTCFG23_OUTCFG95_TIMER111 = 23
,
TIMER_OUTCFG23_OUTCFG95_TIMER120 = 24
, TIMER_OUTCFG23_OUTCFG95_TIMER121 = 25
, TIMER_OUTCFG23_OUTCFG95_TIMER130 = 26
, TIMER_OUTCFG23_OUTCFG95_TIMER131 = 27
,
TIMER_OUTCFG23_OUTCFG95_TIMER140 = 28
, TIMER_OUTCFG23_OUTCFG95_TIMER141 = 29
, TIMER_OUTCFG23_OUTCFG95_TIMER150 = 30
, TIMER_OUTCFG23_OUTCFG95_TIMER151 = 31
,
TIMER_OUTCFG23_OUTCFG95_STIMER0 = 32
, TIMER_OUTCFG23_OUTCFG95_STIMER1 = 33
, TIMER_OUTCFG23_OUTCFG95_STIMER2 = 34
, TIMER_OUTCFG23_OUTCFG95_STIMER3 = 35
,
TIMER_OUTCFG23_OUTCFG95_STIMER4 = 36
, TIMER_OUTCFG23_OUTCFG95_STIMER5 = 37
, TIMER_OUTCFG23_OUTCFG95_STIMER6 = 38
, TIMER_OUTCFG23_OUTCFG95_STIMER7 = 39
,
TIMER_OUTCFG23_OUTCFG95_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG23_OUTCFG94_Enum {
TIMER_OUTCFG23_OUTCFG94_TIMER00 = 0
, TIMER_OUTCFG23_OUTCFG94_TIMER01 = 1
, TIMER_OUTCFG23_OUTCFG94_TIMER10 = 2
, TIMER_OUTCFG23_OUTCFG94_TIMER11 = 3
,
TIMER_OUTCFG23_OUTCFG94_TIMER20 = 4
, TIMER_OUTCFG23_OUTCFG94_TIMER21 = 5
, TIMER_OUTCFG23_OUTCFG94_TIMER30 = 6
, TIMER_OUTCFG23_OUTCFG94_TIMER31 = 7
,
TIMER_OUTCFG23_OUTCFG94_TIMER40 = 8
, TIMER_OUTCFG23_OUTCFG94_TIMER41 = 9
, TIMER_OUTCFG23_OUTCFG94_TIMER50 = 10
, TIMER_OUTCFG23_OUTCFG94_TIMER51 = 11
,
TIMER_OUTCFG23_OUTCFG94_TIMER60 = 12
, TIMER_OUTCFG23_OUTCFG94_TIMER61 = 13
, TIMER_OUTCFG23_OUTCFG94_TIMER70 = 14
, TIMER_OUTCFG23_OUTCFG94_TIMER71 = 15
,
TIMER_OUTCFG23_OUTCFG94_TIMER80 = 16
, TIMER_OUTCFG23_OUTCFG94_TIMER81 = 17
, TIMER_OUTCFG23_OUTCFG94_TIMER90 = 18
, TIMER_OUTCFG23_OUTCFG94_TIMER91 = 19
,
TIMER_OUTCFG23_OUTCFG94_TIMER100 = 20
, TIMER_OUTCFG23_OUTCFG94_TIMER101 = 21
, TIMER_OUTCFG23_OUTCFG94_TIMER110 = 22
, TIMER_OUTCFG23_OUTCFG94_TIMER111 = 23
,
TIMER_OUTCFG23_OUTCFG94_TIMER120 = 24
, TIMER_OUTCFG23_OUTCFG94_TIMER121 = 25
, TIMER_OUTCFG23_OUTCFG94_TIMER130 = 26
, TIMER_OUTCFG23_OUTCFG94_TIMER131 = 27
,
TIMER_OUTCFG23_OUTCFG94_TIMER140 = 28
, TIMER_OUTCFG23_OUTCFG94_TIMER141 = 29
, TIMER_OUTCFG23_OUTCFG94_TIMER150 = 30
, TIMER_OUTCFG23_OUTCFG94_TIMER151 = 31
,
TIMER_OUTCFG23_OUTCFG94_STIMER0 = 32
, TIMER_OUTCFG23_OUTCFG94_STIMER1 = 33
, TIMER_OUTCFG23_OUTCFG94_STIMER2 = 34
, TIMER_OUTCFG23_OUTCFG94_STIMER3 = 35
,
TIMER_OUTCFG23_OUTCFG94_STIMER4 = 36
, TIMER_OUTCFG23_OUTCFG94_STIMER5 = 37
, TIMER_OUTCFG23_OUTCFG94_STIMER6 = 38
, TIMER_OUTCFG23_OUTCFG94_STIMER7 = 39
,
TIMER_OUTCFG23_OUTCFG94_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG23_OUTCFG93_Enum {
TIMER_OUTCFG23_OUTCFG93_TIMER00 = 0
, TIMER_OUTCFG23_OUTCFG93_TIMER01 = 1
, TIMER_OUTCFG23_OUTCFG93_TIMER10 = 2
, TIMER_OUTCFG23_OUTCFG93_TIMER11 = 3
,
TIMER_OUTCFG23_OUTCFG93_TIMER20 = 4
, TIMER_OUTCFG23_OUTCFG93_TIMER21 = 5
, TIMER_OUTCFG23_OUTCFG93_TIMER30 = 6
, TIMER_OUTCFG23_OUTCFG93_TIMER31 = 7
,
TIMER_OUTCFG23_OUTCFG93_TIMER40 = 8
, TIMER_OUTCFG23_OUTCFG93_TIMER41 = 9
, TIMER_OUTCFG23_OUTCFG93_TIMER50 = 10
, TIMER_OUTCFG23_OUTCFG93_TIMER51 = 11
,
TIMER_OUTCFG23_OUTCFG93_TIMER60 = 12
, TIMER_OUTCFG23_OUTCFG93_TIMER61 = 13
, TIMER_OUTCFG23_OUTCFG93_TIMER70 = 14
, TIMER_OUTCFG23_OUTCFG93_TIMER71 = 15
,
TIMER_OUTCFG23_OUTCFG93_TIMER80 = 16
, TIMER_OUTCFG23_OUTCFG93_TIMER81 = 17
, TIMER_OUTCFG23_OUTCFG93_TIMER90 = 18
, TIMER_OUTCFG23_OUTCFG93_TIMER91 = 19
,
TIMER_OUTCFG23_OUTCFG93_TIMER100 = 20
, TIMER_OUTCFG23_OUTCFG93_TIMER101 = 21
, TIMER_OUTCFG23_OUTCFG93_TIMER110 = 22
, TIMER_OUTCFG23_OUTCFG93_TIMER111 = 23
,
TIMER_OUTCFG23_OUTCFG93_TIMER120 = 24
, TIMER_OUTCFG23_OUTCFG93_TIMER121 = 25
, TIMER_OUTCFG23_OUTCFG93_TIMER130 = 26
, TIMER_OUTCFG23_OUTCFG93_TIMER131 = 27
,
TIMER_OUTCFG23_OUTCFG93_TIMER140 = 28
, TIMER_OUTCFG23_OUTCFG93_TIMER141 = 29
, TIMER_OUTCFG23_OUTCFG93_TIMER150 = 30
, TIMER_OUTCFG23_OUTCFG93_TIMER151 = 31
,
TIMER_OUTCFG23_OUTCFG93_STIMER0 = 32
, TIMER_OUTCFG23_OUTCFG93_STIMER1 = 33
, TIMER_OUTCFG23_OUTCFG93_STIMER2 = 34
, TIMER_OUTCFG23_OUTCFG93_STIMER3 = 35
,
TIMER_OUTCFG23_OUTCFG93_STIMER4 = 36
, TIMER_OUTCFG23_OUTCFG93_STIMER5 = 37
, TIMER_OUTCFG23_OUTCFG93_STIMER6 = 38
, TIMER_OUTCFG23_OUTCFG93_STIMER7 = 39
,
TIMER_OUTCFG23_OUTCFG93_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG23_OUTCFG92_Enum {
TIMER_OUTCFG23_OUTCFG92_TIMER00 = 0
, TIMER_OUTCFG23_OUTCFG92_TIMER01 = 1
, TIMER_OUTCFG23_OUTCFG92_TIMER10 = 2
, TIMER_OUTCFG23_OUTCFG92_TIMER11 = 3
,
TIMER_OUTCFG23_OUTCFG92_TIMER20 = 4
, TIMER_OUTCFG23_OUTCFG92_TIMER21 = 5
, TIMER_OUTCFG23_OUTCFG92_TIMER30 = 6
, TIMER_OUTCFG23_OUTCFG92_TIMER31 = 7
,
TIMER_OUTCFG23_OUTCFG92_TIMER40 = 8
, TIMER_OUTCFG23_OUTCFG92_TIMER41 = 9
, TIMER_OUTCFG23_OUTCFG92_TIMER50 = 10
, TIMER_OUTCFG23_OUTCFG92_TIMER51 = 11
,
TIMER_OUTCFG23_OUTCFG92_TIMER60 = 12
, TIMER_OUTCFG23_OUTCFG92_TIMER61 = 13
, TIMER_OUTCFG23_OUTCFG92_TIMER70 = 14
, TIMER_OUTCFG23_OUTCFG92_TIMER71 = 15
,
TIMER_OUTCFG23_OUTCFG92_TIMER80 = 16
, TIMER_OUTCFG23_OUTCFG92_TIMER81 = 17
, TIMER_OUTCFG23_OUTCFG92_TIMER90 = 18
, TIMER_OUTCFG23_OUTCFG92_TIMER91 = 19
,
TIMER_OUTCFG23_OUTCFG92_TIMER100 = 20
, TIMER_OUTCFG23_OUTCFG92_TIMER101 = 21
, TIMER_OUTCFG23_OUTCFG92_TIMER110 = 22
, TIMER_OUTCFG23_OUTCFG92_TIMER111 = 23
,
TIMER_OUTCFG23_OUTCFG92_TIMER120 = 24
, TIMER_OUTCFG23_OUTCFG92_TIMER121 = 25
, TIMER_OUTCFG23_OUTCFG92_TIMER130 = 26
, TIMER_OUTCFG23_OUTCFG92_TIMER131 = 27
,
TIMER_OUTCFG23_OUTCFG92_TIMER140 = 28
, TIMER_OUTCFG23_OUTCFG92_TIMER141 = 29
, TIMER_OUTCFG23_OUTCFG92_TIMER150 = 30
, TIMER_OUTCFG23_OUTCFG92_TIMER151 = 31
,
TIMER_OUTCFG23_OUTCFG92_STIMER0 = 32
, TIMER_OUTCFG23_OUTCFG92_STIMER1 = 33
, TIMER_OUTCFG23_OUTCFG92_STIMER2 = 34
, TIMER_OUTCFG23_OUTCFG92_STIMER3 = 35
,
TIMER_OUTCFG23_OUTCFG92_STIMER4 = 36
, TIMER_OUTCFG23_OUTCFG92_STIMER5 = 37
, TIMER_OUTCFG23_OUTCFG92_STIMER6 = 38
, TIMER_OUTCFG23_OUTCFG92_STIMER7 = 39
,
TIMER_OUTCFG23_OUTCFG92_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG24_OUTCFG99_Enum {
TIMER_OUTCFG24_OUTCFG99_TIMER00 = 0
, TIMER_OUTCFG24_OUTCFG99_TIMER01 = 1
, TIMER_OUTCFG24_OUTCFG99_TIMER10 = 2
, TIMER_OUTCFG24_OUTCFG99_TIMER11 = 3
,
TIMER_OUTCFG24_OUTCFG99_TIMER20 = 4
, TIMER_OUTCFG24_OUTCFG99_TIMER21 = 5
, TIMER_OUTCFG24_OUTCFG99_TIMER30 = 6
, TIMER_OUTCFG24_OUTCFG99_TIMER31 = 7
,
TIMER_OUTCFG24_OUTCFG99_TIMER40 = 8
, TIMER_OUTCFG24_OUTCFG99_TIMER41 = 9
, TIMER_OUTCFG24_OUTCFG99_TIMER50 = 10
, TIMER_OUTCFG24_OUTCFG99_TIMER51 = 11
,
TIMER_OUTCFG24_OUTCFG99_TIMER60 = 12
, TIMER_OUTCFG24_OUTCFG99_TIMER61 = 13
, TIMER_OUTCFG24_OUTCFG99_TIMER70 = 14
, TIMER_OUTCFG24_OUTCFG99_TIMER71 = 15
,
TIMER_OUTCFG24_OUTCFG99_TIMER80 = 16
, TIMER_OUTCFG24_OUTCFG99_TIMER81 = 17
, TIMER_OUTCFG24_OUTCFG99_TIMER90 = 18
, TIMER_OUTCFG24_OUTCFG99_TIMER91 = 19
,
TIMER_OUTCFG24_OUTCFG99_TIMER100 = 20
, TIMER_OUTCFG24_OUTCFG99_TIMER101 = 21
, TIMER_OUTCFG24_OUTCFG99_TIMER110 = 22
, TIMER_OUTCFG24_OUTCFG99_TIMER111 = 23
,
TIMER_OUTCFG24_OUTCFG99_TIMER120 = 24
, TIMER_OUTCFG24_OUTCFG99_TIMER121 = 25
, TIMER_OUTCFG24_OUTCFG99_TIMER130 = 26
, TIMER_OUTCFG24_OUTCFG99_TIMER131 = 27
,
TIMER_OUTCFG24_OUTCFG99_TIMER140 = 28
, TIMER_OUTCFG24_OUTCFG99_TIMER141 = 29
, TIMER_OUTCFG24_OUTCFG99_TIMER150 = 30
, TIMER_OUTCFG24_OUTCFG99_TIMER151 = 31
,
TIMER_OUTCFG24_OUTCFG99_STIMER0 = 32
, TIMER_OUTCFG24_OUTCFG99_STIMER1 = 33
, TIMER_OUTCFG24_OUTCFG99_STIMER2 = 34
, TIMER_OUTCFG24_OUTCFG99_STIMER3 = 35
,
TIMER_OUTCFG24_OUTCFG99_STIMER4 = 36
, TIMER_OUTCFG24_OUTCFG99_STIMER5 = 37
, TIMER_OUTCFG24_OUTCFG99_STIMER6 = 38
, TIMER_OUTCFG24_OUTCFG99_STIMER7 = 39
,
TIMER_OUTCFG24_OUTCFG99_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG24_OUTCFG98_Enum {
TIMER_OUTCFG24_OUTCFG98_TIMER00 = 0
, TIMER_OUTCFG24_OUTCFG98_TIMER01 = 1
, TIMER_OUTCFG24_OUTCFG98_TIMER10 = 2
, TIMER_OUTCFG24_OUTCFG98_TIMER11 = 3
,
TIMER_OUTCFG24_OUTCFG98_TIMER20 = 4
, TIMER_OUTCFG24_OUTCFG98_TIMER21 = 5
, TIMER_OUTCFG24_OUTCFG98_TIMER30 = 6
, TIMER_OUTCFG24_OUTCFG98_TIMER31 = 7
,
TIMER_OUTCFG24_OUTCFG98_TIMER40 = 8
, TIMER_OUTCFG24_OUTCFG98_TIMER41 = 9
, TIMER_OUTCFG24_OUTCFG98_TIMER50 = 10
, TIMER_OUTCFG24_OUTCFG98_TIMER51 = 11
,
TIMER_OUTCFG24_OUTCFG98_TIMER60 = 12
, TIMER_OUTCFG24_OUTCFG98_TIMER61 = 13
, TIMER_OUTCFG24_OUTCFG98_TIMER70 = 14
, TIMER_OUTCFG24_OUTCFG98_TIMER71 = 15
,
TIMER_OUTCFG24_OUTCFG98_TIMER80 = 16
, TIMER_OUTCFG24_OUTCFG98_TIMER81 = 17
, TIMER_OUTCFG24_OUTCFG98_TIMER90 = 18
, TIMER_OUTCFG24_OUTCFG98_TIMER91 = 19
,
TIMER_OUTCFG24_OUTCFG98_TIMER100 = 20
, TIMER_OUTCFG24_OUTCFG98_TIMER101 = 21
, TIMER_OUTCFG24_OUTCFG98_TIMER110 = 22
, TIMER_OUTCFG24_OUTCFG98_TIMER111 = 23
,
TIMER_OUTCFG24_OUTCFG98_TIMER120 = 24
, TIMER_OUTCFG24_OUTCFG98_TIMER121 = 25
, TIMER_OUTCFG24_OUTCFG98_TIMER130 = 26
, TIMER_OUTCFG24_OUTCFG98_TIMER131 = 27
,
TIMER_OUTCFG24_OUTCFG98_TIMER140 = 28
, TIMER_OUTCFG24_OUTCFG98_TIMER141 = 29
, TIMER_OUTCFG24_OUTCFG98_TIMER150 = 30
, TIMER_OUTCFG24_OUTCFG98_TIMER151 = 31
,
TIMER_OUTCFG24_OUTCFG98_STIMER0 = 32
, TIMER_OUTCFG24_OUTCFG98_STIMER1 = 33
, TIMER_OUTCFG24_OUTCFG98_STIMER2 = 34
, TIMER_OUTCFG24_OUTCFG98_STIMER3 = 35
,
TIMER_OUTCFG24_OUTCFG98_STIMER4 = 36
, TIMER_OUTCFG24_OUTCFG98_STIMER5 = 37
, TIMER_OUTCFG24_OUTCFG98_STIMER6 = 38
, TIMER_OUTCFG24_OUTCFG98_STIMER7 = 39
,
TIMER_OUTCFG24_OUTCFG98_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG24_OUTCFG97_Enum {
TIMER_OUTCFG24_OUTCFG97_TIMER00 = 0
, TIMER_OUTCFG24_OUTCFG97_TIMER01 = 1
, TIMER_OUTCFG24_OUTCFG97_TIMER10 = 2
, TIMER_OUTCFG24_OUTCFG97_TIMER11 = 3
,
TIMER_OUTCFG24_OUTCFG97_TIMER20 = 4
, TIMER_OUTCFG24_OUTCFG97_TIMER21 = 5
, TIMER_OUTCFG24_OUTCFG97_TIMER30 = 6
, TIMER_OUTCFG24_OUTCFG97_TIMER31 = 7
,
TIMER_OUTCFG24_OUTCFG97_TIMER40 = 8
, TIMER_OUTCFG24_OUTCFG97_TIMER41 = 9
, TIMER_OUTCFG24_OUTCFG97_TIMER50 = 10
, TIMER_OUTCFG24_OUTCFG97_TIMER51 = 11
,
TIMER_OUTCFG24_OUTCFG97_TIMER60 = 12
, TIMER_OUTCFG24_OUTCFG97_TIMER61 = 13
, TIMER_OUTCFG24_OUTCFG97_TIMER70 = 14
, TIMER_OUTCFG24_OUTCFG97_TIMER71 = 15
,
TIMER_OUTCFG24_OUTCFG97_TIMER80 = 16
, TIMER_OUTCFG24_OUTCFG97_TIMER81 = 17
, TIMER_OUTCFG24_OUTCFG97_TIMER90 = 18
, TIMER_OUTCFG24_OUTCFG97_TIMER91 = 19
,
TIMER_OUTCFG24_OUTCFG97_TIMER100 = 20
, TIMER_OUTCFG24_OUTCFG97_TIMER101 = 21
, TIMER_OUTCFG24_OUTCFG97_TIMER110 = 22
, TIMER_OUTCFG24_OUTCFG97_TIMER111 = 23
,
TIMER_OUTCFG24_OUTCFG97_TIMER120 = 24
, TIMER_OUTCFG24_OUTCFG97_TIMER121 = 25
, TIMER_OUTCFG24_OUTCFG97_TIMER130 = 26
, TIMER_OUTCFG24_OUTCFG97_TIMER131 = 27
,
TIMER_OUTCFG24_OUTCFG97_TIMER140 = 28
, TIMER_OUTCFG24_OUTCFG97_TIMER141 = 29
, TIMER_OUTCFG24_OUTCFG97_TIMER150 = 30
, TIMER_OUTCFG24_OUTCFG97_TIMER151 = 31
,
TIMER_OUTCFG24_OUTCFG97_STIMER0 = 32
, TIMER_OUTCFG24_OUTCFG97_STIMER1 = 33
, TIMER_OUTCFG24_OUTCFG97_STIMER2 = 34
, TIMER_OUTCFG24_OUTCFG97_STIMER3 = 35
,
TIMER_OUTCFG24_OUTCFG97_STIMER4 = 36
, TIMER_OUTCFG24_OUTCFG97_STIMER5 = 37
, TIMER_OUTCFG24_OUTCFG97_STIMER6 = 38
, TIMER_OUTCFG24_OUTCFG97_STIMER7 = 39
,
TIMER_OUTCFG24_OUTCFG97_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG24_OUTCFG96_Enum {
TIMER_OUTCFG24_OUTCFG96_TIMER00 = 0
, TIMER_OUTCFG24_OUTCFG96_TIMER01 = 1
, TIMER_OUTCFG24_OUTCFG96_TIMER10 = 2
, TIMER_OUTCFG24_OUTCFG96_TIMER11 = 3
,
TIMER_OUTCFG24_OUTCFG96_TIMER20 = 4
, TIMER_OUTCFG24_OUTCFG96_TIMER21 = 5
, TIMER_OUTCFG24_OUTCFG96_TIMER30 = 6
, TIMER_OUTCFG24_OUTCFG96_TIMER31 = 7
,
TIMER_OUTCFG24_OUTCFG96_TIMER40 = 8
, TIMER_OUTCFG24_OUTCFG96_TIMER41 = 9
, TIMER_OUTCFG24_OUTCFG96_TIMER50 = 10
, TIMER_OUTCFG24_OUTCFG96_TIMER51 = 11
,
TIMER_OUTCFG24_OUTCFG96_TIMER60 = 12
, TIMER_OUTCFG24_OUTCFG96_TIMER61 = 13
, TIMER_OUTCFG24_OUTCFG96_TIMER70 = 14
, TIMER_OUTCFG24_OUTCFG96_TIMER71 = 15
,
TIMER_OUTCFG24_OUTCFG96_TIMER80 = 16
, TIMER_OUTCFG24_OUTCFG96_TIMER81 = 17
, TIMER_OUTCFG24_OUTCFG96_TIMER90 = 18
, TIMER_OUTCFG24_OUTCFG96_TIMER91 = 19
,
TIMER_OUTCFG24_OUTCFG96_TIMER100 = 20
, TIMER_OUTCFG24_OUTCFG96_TIMER101 = 21
, TIMER_OUTCFG24_OUTCFG96_TIMER110 = 22
, TIMER_OUTCFG24_OUTCFG96_TIMER111 = 23
,
TIMER_OUTCFG24_OUTCFG96_TIMER120 = 24
, TIMER_OUTCFG24_OUTCFG96_TIMER121 = 25
, TIMER_OUTCFG24_OUTCFG96_TIMER130 = 26
, TIMER_OUTCFG24_OUTCFG96_TIMER131 = 27
,
TIMER_OUTCFG24_OUTCFG96_TIMER140 = 28
, TIMER_OUTCFG24_OUTCFG96_TIMER141 = 29
, TIMER_OUTCFG24_OUTCFG96_TIMER150 = 30
, TIMER_OUTCFG24_OUTCFG96_TIMER151 = 31
,
TIMER_OUTCFG24_OUTCFG96_STIMER0 = 32
, TIMER_OUTCFG24_OUTCFG96_STIMER1 = 33
, TIMER_OUTCFG24_OUTCFG96_STIMER2 = 34
, TIMER_OUTCFG24_OUTCFG96_STIMER3 = 35
,
TIMER_OUTCFG24_OUTCFG96_STIMER4 = 36
, TIMER_OUTCFG24_OUTCFG96_STIMER5 = 37
, TIMER_OUTCFG24_OUTCFG96_STIMER6 = 38
, TIMER_OUTCFG24_OUTCFG96_STIMER7 = 39
,
TIMER_OUTCFG24_OUTCFG96_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG25_OUTCFG103_Enum {
TIMER_OUTCFG25_OUTCFG103_TIMER00 = 0
, TIMER_OUTCFG25_OUTCFG103_TIMER01 = 1
, TIMER_OUTCFG25_OUTCFG103_TIMER10 = 2
, TIMER_OUTCFG25_OUTCFG103_TIMER11 = 3
,
TIMER_OUTCFG25_OUTCFG103_TIMER20 = 4
, TIMER_OUTCFG25_OUTCFG103_TIMER21 = 5
, TIMER_OUTCFG25_OUTCFG103_TIMER30 = 6
, TIMER_OUTCFG25_OUTCFG103_TIMER31 = 7
,
TIMER_OUTCFG25_OUTCFG103_TIMER40 = 8
, TIMER_OUTCFG25_OUTCFG103_TIMER41 = 9
, TIMER_OUTCFG25_OUTCFG103_TIMER50 = 10
, TIMER_OUTCFG25_OUTCFG103_TIMER51 = 11
,
TIMER_OUTCFG25_OUTCFG103_TIMER60 = 12
, TIMER_OUTCFG25_OUTCFG103_TIMER61 = 13
, TIMER_OUTCFG25_OUTCFG103_TIMER70 = 14
, TIMER_OUTCFG25_OUTCFG103_TIMER71 = 15
,
TIMER_OUTCFG25_OUTCFG103_TIMER80 = 16
, TIMER_OUTCFG25_OUTCFG103_TIMER81 = 17
, TIMER_OUTCFG25_OUTCFG103_TIMER90 = 18
, TIMER_OUTCFG25_OUTCFG103_TIMER91 = 19
,
TIMER_OUTCFG25_OUTCFG103_TIMER100 = 20
, TIMER_OUTCFG25_OUTCFG103_TIMER101 = 21
, TIMER_OUTCFG25_OUTCFG103_TIMER110 = 22
, TIMER_OUTCFG25_OUTCFG103_TIMER111 = 23
,
TIMER_OUTCFG25_OUTCFG103_TIMER120 = 24
, TIMER_OUTCFG25_OUTCFG103_TIMER121 = 25
, TIMER_OUTCFG25_OUTCFG103_TIMER130 = 26
, TIMER_OUTCFG25_OUTCFG103_TIMER131 = 27
,
TIMER_OUTCFG25_OUTCFG103_TIMER140 = 28
, TIMER_OUTCFG25_OUTCFG103_TIMER141 = 29
, TIMER_OUTCFG25_OUTCFG103_TIMER150 = 30
, TIMER_OUTCFG25_OUTCFG103_TIMER151 = 31
,
TIMER_OUTCFG25_OUTCFG103_STIMER0 = 32
, TIMER_OUTCFG25_OUTCFG103_STIMER1 = 33
, TIMER_OUTCFG25_OUTCFG103_STIMER2 = 34
, TIMER_OUTCFG25_OUTCFG103_STIMER3 = 35
,
TIMER_OUTCFG25_OUTCFG103_STIMER4 = 36
, TIMER_OUTCFG25_OUTCFG103_STIMER5 = 37
, TIMER_OUTCFG25_OUTCFG103_STIMER6 = 38
, TIMER_OUTCFG25_OUTCFG103_STIMER7 = 39
,
TIMER_OUTCFG25_OUTCFG103_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG25_OUTCFG102_Enum {
TIMER_OUTCFG25_OUTCFG102_TIMER00 = 0
, TIMER_OUTCFG25_OUTCFG102_TIMER01 = 1
, TIMER_OUTCFG25_OUTCFG102_TIMER10 = 2
, TIMER_OUTCFG25_OUTCFG102_TIMER11 = 3
,
TIMER_OUTCFG25_OUTCFG102_TIMER20 = 4
, TIMER_OUTCFG25_OUTCFG102_TIMER21 = 5
, TIMER_OUTCFG25_OUTCFG102_TIMER30 = 6
, TIMER_OUTCFG25_OUTCFG102_TIMER31 = 7
,
TIMER_OUTCFG25_OUTCFG102_TIMER40 = 8
, TIMER_OUTCFG25_OUTCFG102_TIMER41 = 9
, TIMER_OUTCFG25_OUTCFG102_TIMER50 = 10
, TIMER_OUTCFG25_OUTCFG102_TIMER51 = 11
,
TIMER_OUTCFG25_OUTCFG102_TIMER60 = 12
, TIMER_OUTCFG25_OUTCFG102_TIMER61 = 13
, TIMER_OUTCFG25_OUTCFG102_TIMER70 = 14
, TIMER_OUTCFG25_OUTCFG102_TIMER71 = 15
,
TIMER_OUTCFG25_OUTCFG102_TIMER80 = 16
, TIMER_OUTCFG25_OUTCFG102_TIMER81 = 17
, TIMER_OUTCFG25_OUTCFG102_TIMER90 = 18
, TIMER_OUTCFG25_OUTCFG102_TIMER91 = 19
,
TIMER_OUTCFG25_OUTCFG102_TIMER100 = 20
, TIMER_OUTCFG25_OUTCFG102_TIMER101 = 21
, TIMER_OUTCFG25_OUTCFG102_TIMER110 = 22
, TIMER_OUTCFG25_OUTCFG102_TIMER111 = 23
,
TIMER_OUTCFG25_OUTCFG102_TIMER120 = 24
, TIMER_OUTCFG25_OUTCFG102_TIMER121 = 25
, TIMER_OUTCFG25_OUTCFG102_TIMER130 = 26
, TIMER_OUTCFG25_OUTCFG102_TIMER131 = 27
,
TIMER_OUTCFG25_OUTCFG102_TIMER140 = 28
, TIMER_OUTCFG25_OUTCFG102_TIMER141 = 29
, TIMER_OUTCFG25_OUTCFG102_TIMER150 = 30
, TIMER_OUTCFG25_OUTCFG102_TIMER151 = 31
,
TIMER_OUTCFG25_OUTCFG102_STIMER0 = 32
, TIMER_OUTCFG25_OUTCFG102_STIMER1 = 33
, TIMER_OUTCFG25_OUTCFG102_STIMER2 = 34
, TIMER_OUTCFG25_OUTCFG102_STIMER3 = 35
,
TIMER_OUTCFG25_OUTCFG102_STIMER4 = 36
, TIMER_OUTCFG25_OUTCFG102_STIMER5 = 37
, TIMER_OUTCFG25_OUTCFG102_STIMER6 = 38
, TIMER_OUTCFG25_OUTCFG102_STIMER7 = 39
,
TIMER_OUTCFG25_OUTCFG102_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG25_OUTCFG101_Enum {
TIMER_OUTCFG25_OUTCFG101_TIMER00 = 0
, TIMER_OUTCFG25_OUTCFG101_TIMER01 = 1
, TIMER_OUTCFG25_OUTCFG101_TIMER10 = 2
, TIMER_OUTCFG25_OUTCFG101_TIMER11 = 3
,
TIMER_OUTCFG25_OUTCFG101_TIMER20 = 4
, TIMER_OUTCFG25_OUTCFG101_TIMER21 = 5
, TIMER_OUTCFG25_OUTCFG101_TIMER30 = 6
, TIMER_OUTCFG25_OUTCFG101_TIMER31 = 7
,
TIMER_OUTCFG25_OUTCFG101_TIMER40 = 8
, TIMER_OUTCFG25_OUTCFG101_TIMER41 = 9
, TIMER_OUTCFG25_OUTCFG101_TIMER50 = 10
, TIMER_OUTCFG25_OUTCFG101_TIMER51 = 11
,
TIMER_OUTCFG25_OUTCFG101_TIMER60 = 12
, TIMER_OUTCFG25_OUTCFG101_TIMER61 = 13
, TIMER_OUTCFG25_OUTCFG101_TIMER70 = 14
, TIMER_OUTCFG25_OUTCFG101_TIMER71 = 15
,
TIMER_OUTCFG25_OUTCFG101_TIMER80 = 16
, TIMER_OUTCFG25_OUTCFG101_TIMER81 = 17
, TIMER_OUTCFG25_OUTCFG101_TIMER90 = 18
, TIMER_OUTCFG25_OUTCFG101_TIMER91 = 19
,
TIMER_OUTCFG25_OUTCFG101_TIMER100 = 20
, TIMER_OUTCFG25_OUTCFG101_TIMER101 = 21
, TIMER_OUTCFG25_OUTCFG101_TIMER110 = 22
, TIMER_OUTCFG25_OUTCFG101_TIMER111 = 23
,
TIMER_OUTCFG25_OUTCFG101_TIMER120 = 24
, TIMER_OUTCFG25_OUTCFG101_TIMER121 = 25
, TIMER_OUTCFG25_OUTCFG101_TIMER130 = 26
, TIMER_OUTCFG25_OUTCFG101_TIMER131 = 27
,
TIMER_OUTCFG25_OUTCFG101_TIMER140 = 28
, TIMER_OUTCFG25_OUTCFG101_TIMER141 = 29
, TIMER_OUTCFG25_OUTCFG101_TIMER150 = 30
, TIMER_OUTCFG25_OUTCFG101_TIMER151 = 31
,
TIMER_OUTCFG25_OUTCFG101_STIMER0 = 32
, TIMER_OUTCFG25_OUTCFG101_STIMER1 = 33
, TIMER_OUTCFG25_OUTCFG101_STIMER2 = 34
, TIMER_OUTCFG25_OUTCFG101_STIMER3 = 35
,
TIMER_OUTCFG25_OUTCFG101_STIMER4 = 36
, TIMER_OUTCFG25_OUTCFG101_STIMER5 = 37
, TIMER_OUTCFG25_OUTCFG101_STIMER6 = 38
, TIMER_OUTCFG25_OUTCFG101_STIMER7 = 39
,
TIMER_OUTCFG25_OUTCFG101_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG25_OUTCFG100_Enum {
TIMER_OUTCFG25_OUTCFG100_TIMER00 = 0
, TIMER_OUTCFG25_OUTCFG100_TIMER01 = 1
, TIMER_OUTCFG25_OUTCFG100_TIMER10 = 2
, TIMER_OUTCFG25_OUTCFG100_TIMER11 = 3
,
TIMER_OUTCFG25_OUTCFG100_TIMER20 = 4
, TIMER_OUTCFG25_OUTCFG100_TIMER21 = 5
, TIMER_OUTCFG25_OUTCFG100_TIMER30 = 6
, TIMER_OUTCFG25_OUTCFG100_TIMER31 = 7
,
TIMER_OUTCFG25_OUTCFG100_TIMER40 = 8
, TIMER_OUTCFG25_OUTCFG100_TIMER41 = 9
, TIMER_OUTCFG25_OUTCFG100_TIMER50 = 10
, TIMER_OUTCFG25_OUTCFG100_TIMER51 = 11
,
TIMER_OUTCFG25_OUTCFG100_TIMER60 = 12
, TIMER_OUTCFG25_OUTCFG100_TIMER61 = 13
, TIMER_OUTCFG25_OUTCFG100_TIMER70 = 14
, TIMER_OUTCFG25_OUTCFG100_TIMER71 = 15
,
TIMER_OUTCFG25_OUTCFG100_TIMER80 = 16
, TIMER_OUTCFG25_OUTCFG100_TIMER81 = 17
, TIMER_OUTCFG25_OUTCFG100_TIMER90 = 18
, TIMER_OUTCFG25_OUTCFG100_TIMER91 = 19
,
TIMER_OUTCFG25_OUTCFG100_TIMER100 = 20
, TIMER_OUTCFG25_OUTCFG100_TIMER101 = 21
, TIMER_OUTCFG25_OUTCFG100_TIMER110 = 22
, TIMER_OUTCFG25_OUTCFG100_TIMER111 = 23
,
TIMER_OUTCFG25_OUTCFG100_TIMER120 = 24
, TIMER_OUTCFG25_OUTCFG100_TIMER121 = 25
, TIMER_OUTCFG25_OUTCFG100_TIMER130 = 26
, TIMER_OUTCFG25_OUTCFG100_TIMER131 = 27
,
TIMER_OUTCFG25_OUTCFG100_TIMER140 = 28
, TIMER_OUTCFG25_OUTCFG100_TIMER141 = 29
, TIMER_OUTCFG25_OUTCFG100_TIMER150 = 30
, TIMER_OUTCFG25_OUTCFG100_TIMER151 = 31
,
TIMER_OUTCFG25_OUTCFG100_STIMER0 = 32
, TIMER_OUTCFG25_OUTCFG100_STIMER1 = 33
, TIMER_OUTCFG25_OUTCFG100_STIMER2 = 34
, TIMER_OUTCFG25_OUTCFG100_STIMER3 = 35
,
TIMER_OUTCFG25_OUTCFG100_STIMER4 = 36
, TIMER_OUTCFG25_OUTCFG100_STIMER5 = 37
, TIMER_OUTCFG25_OUTCFG100_STIMER6 = 38
, TIMER_OUTCFG25_OUTCFG100_STIMER7 = 39
,
TIMER_OUTCFG25_OUTCFG100_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG26_OUTCFG107_Enum {
TIMER_OUTCFG26_OUTCFG107_TIMER00 = 0
, TIMER_OUTCFG26_OUTCFG107_TIMER01 = 1
, TIMER_OUTCFG26_OUTCFG107_TIMER10 = 2
, TIMER_OUTCFG26_OUTCFG107_TIMER11 = 3
,
TIMER_OUTCFG26_OUTCFG107_TIMER20 = 4
, TIMER_OUTCFG26_OUTCFG107_TIMER21 = 5
, TIMER_OUTCFG26_OUTCFG107_TIMER30 = 6
, TIMER_OUTCFG26_OUTCFG107_TIMER31 = 7
,
TIMER_OUTCFG26_OUTCFG107_TIMER40 = 8
, TIMER_OUTCFG26_OUTCFG107_TIMER41 = 9
, TIMER_OUTCFG26_OUTCFG107_TIMER50 = 10
, TIMER_OUTCFG26_OUTCFG107_TIMER51 = 11
,
TIMER_OUTCFG26_OUTCFG107_TIMER60 = 12
, TIMER_OUTCFG26_OUTCFG107_TIMER61 = 13
, TIMER_OUTCFG26_OUTCFG107_TIMER70 = 14
, TIMER_OUTCFG26_OUTCFG107_TIMER71 = 15
,
TIMER_OUTCFG26_OUTCFG107_TIMER80 = 16
, TIMER_OUTCFG26_OUTCFG107_TIMER81 = 17
, TIMER_OUTCFG26_OUTCFG107_TIMER90 = 18
, TIMER_OUTCFG26_OUTCFG107_TIMER91 = 19
,
TIMER_OUTCFG26_OUTCFG107_TIMER100 = 20
, TIMER_OUTCFG26_OUTCFG107_TIMER101 = 21
, TIMER_OUTCFG26_OUTCFG107_TIMER110 = 22
, TIMER_OUTCFG26_OUTCFG107_TIMER111 = 23
,
TIMER_OUTCFG26_OUTCFG107_TIMER120 = 24
, TIMER_OUTCFG26_OUTCFG107_TIMER121 = 25
, TIMER_OUTCFG26_OUTCFG107_TIMER130 = 26
, TIMER_OUTCFG26_OUTCFG107_TIMER131 = 27
,
TIMER_OUTCFG26_OUTCFG107_TIMER140 = 28
, TIMER_OUTCFG26_OUTCFG107_TIMER141 = 29
, TIMER_OUTCFG26_OUTCFG107_TIMER150 = 30
, TIMER_OUTCFG26_OUTCFG107_TIMER151 = 31
,
TIMER_OUTCFG26_OUTCFG107_STIMER0 = 32
, TIMER_OUTCFG26_OUTCFG107_STIMER1 = 33
, TIMER_OUTCFG26_OUTCFG107_STIMER2 = 34
, TIMER_OUTCFG26_OUTCFG107_STIMER3 = 35
,
TIMER_OUTCFG26_OUTCFG107_STIMER4 = 36
, TIMER_OUTCFG26_OUTCFG107_STIMER5 = 37
, TIMER_OUTCFG26_OUTCFG107_STIMER6 = 38
, TIMER_OUTCFG26_OUTCFG107_STIMER7 = 39
,
TIMER_OUTCFG26_OUTCFG107_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG26_OUTCFG106_Enum {
TIMER_OUTCFG26_OUTCFG106_TIMER00 = 0
, TIMER_OUTCFG26_OUTCFG106_TIMER01 = 1
, TIMER_OUTCFG26_OUTCFG106_TIMER10 = 2
, TIMER_OUTCFG26_OUTCFG106_TIMER11 = 3
,
TIMER_OUTCFG26_OUTCFG106_TIMER20 = 4
, TIMER_OUTCFG26_OUTCFG106_TIMER21 = 5
, TIMER_OUTCFG26_OUTCFG106_TIMER30 = 6
, TIMER_OUTCFG26_OUTCFG106_TIMER31 = 7
,
TIMER_OUTCFG26_OUTCFG106_TIMER40 = 8
, TIMER_OUTCFG26_OUTCFG106_TIMER41 = 9
, TIMER_OUTCFG26_OUTCFG106_TIMER50 = 10
, TIMER_OUTCFG26_OUTCFG106_TIMER51 = 11
,
TIMER_OUTCFG26_OUTCFG106_TIMER60 = 12
, TIMER_OUTCFG26_OUTCFG106_TIMER61 = 13
, TIMER_OUTCFG26_OUTCFG106_TIMER70 = 14
, TIMER_OUTCFG26_OUTCFG106_TIMER71 = 15
,
TIMER_OUTCFG26_OUTCFG106_TIMER80 = 16
, TIMER_OUTCFG26_OUTCFG106_TIMER81 = 17
, TIMER_OUTCFG26_OUTCFG106_TIMER90 = 18
, TIMER_OUTCFG26_OUTCFG106_TIMER91 = 19
,
TIMER_OUTCFG26_OUTCFG106_TIMER100 = 20
, TIMER_OUTCFG26_OUTCFG106_TIMER101 = 21
, TIMER_OUTCFG26_OUTCFG106_TIMER110 = 22
, TIMER_OUTCFG26_OUTCFG106_TIMER111 = 23
,
TIMER_OUTCFG26_OUTCFG106_TIMER120 = 24
, TIMER_OUTCFG26_OUTCFG106_TIMER121 = 25
, TIMER_OUTCFG26_OUTCFG106_TIMER130 = 26
, TIMER_OUTCFG26_OUTCFG106_TIMER131 = 27
,
TIMER_OUTCFG26_OUTCFG106_TIMER140 = 28
, TIMER_OUTCFG26_OUTCFG106_TIMER141 = 29
, TIMER_OUTCFG26_OUTCFG106_TIMER150 = 30
, TIMER_OUTCFG26_OUTCFG106_TIMER151 = 31
,
TIMER_OUTCFG26_OUTCFG106_STIMER0 = 32
, TIMER_OUTCFG26_OUTCFG106_STIMER1 = 33
, TIMER_OUTCFG26_OUTCFG106_STIMER2 = 34
, TIMER_OUTCFG26_OUTCFG106_STIMER3 = 35
,
TIMER_OUTCFG26_OUTCFG106_STIMER4 = 36
, TIMER_OUTCFG26_OUTCFG106_STIMER5 = 37
, TIMER_OUTCFG26_OUTCFG106_STIMER6 = 38
, TIMER_OUTCFG26_OUTCFG106_STIMER7 = 39
,
TIMER_OUTCFG26_OUTCFG106_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG26_OUTCFG105_Enum {
TIMER_OUTCFG26_OUTCFG105_TIMER00 = 0
, TIMER_OUTCFG26_OUTCFG105_TIMER01 = 1
, TIMER_OUTCFG26_OUTCFG105_TIMER10 = 2
, TIMER_OUTCFG26_OUTCFG105_TIMER11 = 3
,
TIMER_OUTCFG26_OUTCFG105_TIMER20 = 4
, TIMER_OUTCFG26_OUTCFG105_TIMER21 = 5
, TIMER_OUTCFG26_OUTCFG105_TIMER30 = 6
, TIMER_OUTCFG26_OUTCFG105_TIMER31 = 7
,
TIMER_OUTCFG26_OUTCFG105_TIMER40 = 8
, TIMER_OUTCFG26_OUTCFG105_TIMER41 = 9
, TIMER_OUTCFG26_OUTCFG105_TIMER50 = 10
, TIMER_OUTCFG26_OUTCFG105_TIMER51 = 11
,
TIMER_OUTCFG26_OUTCFG105_TIMER60 = 12
, TIMER_OUTCFG26_OUTCFG105_TIMER61 = 13
, TIMER_OUTCFG26_OUTCFG105_TIMER70 = 14
, TIMER_OUTCFG26_OUTCFG105_TIMER71 = 15
,
TIMER_OUTCFG26_OUTCFG105_TIMER80 = 16
, TIMER_OUTCFG26_OUTCFG105_TIMER81 = 17
, TIMER_OUTCFG26_OUTCFG105_TIMER90 = 18
, TIMER_OUTCFG26_OUTCFG105_TIMER91 = 19
,
TIMER_OUTCFG26_OUTCFG105_TIMER100 = 20
, TIMER_OUTCFG26_OUTCFG105_TIMER101 = 21
, TIMER_OUTCFG26_OUTCFG105_TIMER110 = 22
, TIMER_OUTCFG26_OUTCFG105_TIMER111 = 23
,
TIMER_OUTCFG26_OUTCFG105_TIMER120 = 24
, TIMER_OUTCFG26_OUTCFG105_TIMER121 = 25
, TIMER_OUTCFG26_OUTCFG105_TIMER130 = 26
, TIMER_OUTCFG26_OUTCFG105_TIMER131 = 27
,
TIMER_OUTCFG26_OUTCFG105_TIMER140 = 28
, TIMER_OUTCFG26_OUTCFG105_TIMER141 = 29
, TIMER_OUTCFG26_OUTCFG105_TIMER150 = 30
, TIMER_OUTCFG26_OUTCFG105_TIMER151 = 31
,
TIMER_OUTCFG26_OUTCFG105_STIMER0 = 32
, TIMER_OUTCFG26_OUTCFG105_STIMER1 = 33
, TIMER_OUTCFG26_OUTCFG105_STIMER2 = 34
, TIMER_OUTCFG26_OUTCFG105_STIMER3 = 35
,
TIMER_OUTCFG26_OUTCFG105_STIMER4 = 36
, TIMER_OUTCFG26_OUTCFG105_STIMER5 = 37
, TIMER_OUTCFG26_OUTCFG105_STIMER6 = 38
, TIMER_OUTCFG26_OUTCFG105_STIMER7 = 39
,
TIMER_OUTCFG26_OUTCFG105_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG26_OUTCFG104_Enum {
TIMER_OUTCFG26_OUTCFG104_TIMER00 = 0
, TIMER_OUTCFG26_OUTCFG104_TIMER01 = 1
, TIMER_OUTCFG26_OUTCFG104_TIMER10 = 2
, TIMER_OUTCFG26_OUTCFG104_TIMER11 = 3
,
TIMER_OUTCFG26_OUTCFG104_TIMER20 = 4
, TIMER_OUTCFG26_OUTCFG104_TIMER21 = 5
, TIMER_OUTCFG26_OUTCFG104_TIMER30 = 6
, TIMER_OUTCFG26_OUTCFG104_TIMER31 = 7
,
TIMER_OUTCFG26_OUTCFG104_TIMER40 = 8
, TIMER_OUTCFG26_OUTCFG104_TIMER41 = 9
, TIMER_OUTCFG26_OUTCFG104_TIMER50 = 10
, TIMER_OUTCFG26_OUTCFG104_TIMER51 = 11
,
TIMER_OUTCFG26_OUTCFG104_TIMER60 = 12
, TIMER_OUTCFG26_OUTCFG104_TIMER61 = 13
, TIMER_OUTCFG26_OUTCFG104_TIMER70 = 14
, TIMER_OUTCFG26_OUTCFG104_TIMER71 = 15
,
TIMER_OUTCFG26_OUTCFG104_TIMER80 = 16
, TIMER_OUTCFG26_OUTCFG104_TIMER81 = 17
, TIMER_OUTCFG26_OUTCFG104_TIMER90 = 18
, TIMER_OUTCFG26_OUTCFG104_TIMER91 = 19
,
TIMER_OUTCFG26_OUTCFG104_TIMER100 = 20
, TIMER_OUTCFG26_OUTCFG104_TIMER101 = 21
, TIMER_OUTCFG26_OUTCFG104_TIMER110 = 22
, TIMER_OUTCFG26_OUTCFG104_TIMER111 = 23
,
TIMER_OUTCFG26_OUTCFG104_TIMER120 = 24
, TIMER_OUTCFG26_OUTCFG104_TIMER121 = 25
, TIMER_OUTCFG26_OUTCFG104_TIMER130 = 26
, TIMER_OUTCFG26_OUTCFG104_TIMER131 = 27
,
TIMER_OUTCFG26_OUTCFG104_TIMER140 = 28
, TIMER_OUTCFG26_OUTCFG104_TIMER141 = 29
, TIMER_OUTCFG26_OUTCFG104_TIMER150 = 30
, TIMER_OUTCFG26_OUTCFG104_TIMER151 = 31
,
TIMER_OUTCFG26_OUTCFG104_STIMER0 = 32
, TIMER_OUTCFG26_OUTCFG104_STIMER1 = 33
, TIMER_OUTCFG26_OUTCFG104_STIMER2 = 34
, TIMER_OUTCFG26_OUTCFG104_STIMER3 = 35
,
TIMER_OUTCFG26_OUTCFG104_STIMER4 = 36
, TIMER_OUTCFG26_OUTCFG104_STIMER5 = 37
, TIMER_OUTCFG26_OUTCFG104_STIMER6 = 38
, TIMER_OUTCFG26_OUTCFG104_STIMER7 = 39
,
TIMER_OUTCFG26_OUTCFG104_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG27_OUTCFG111_Enum {
TIMER_OUTCFG27_OUTCFG111_TIMER00 = 0
, TIMER_OUTCFG27_OUTCFG111_TIMER01 = 1
, TIMER_OUTCFG27_OUTCFG111_TIMER10 = 2
, TIMER_OUTCFG27_OUTCFG111_TIMER11 = 3
,
TIMER_OUTCFG27_OUTCFG111_TIMER20 = 4
, TIMER_OUTCFG27_OUTCFG111_TIMER21 = 5
, TIMER_OUTCFG27_OUTCFG111_TIMER30 = 6
, TIMER_OUTCFG27_OUTCFG111_TIMER31 = 7
,
TIMER_OUTCFG27_OUTCFG111_TIMER40 = 8
, TIMER_OUTCFG27_OUTCFG111_TIMER41 = 9
, TIMER_OUTCFG27_OUTCFG111_TIMER50 = 10
, TIMER_OUTCFG27_OUTCFG111_TIMER51 = 11
,
TIMER_OUTCFG27_OUTCFG111_TIMER60 = 12
, TIMER_OUTCFG27_OUTCFG111_TIMER61 = 13
, TIMER_OUTCFG27_OUTCFG111_TIMER70 = 14
, TIMER_OUTCFG27_OUTCFG111_TIMER71 = 15
,
TIMER_OUTCFG27_OUTCFG111_TIMER80 = 16
, TIMER_OUTCFG27_OUTCFG111_TIMER81 = 17
, TIMER_OUTCFG27_OUTCFG111_TIMER90 = 18
, TIMER_OUTCFG27_OUTCFG111_TIMER91 = 19
,
TIMER_OUTCFG27_OUTCFG111_TIMER100 = 20
, TIMER_OUTCFG27_OUTCFG111_TIMER101 = 21
, TIMER_OUTCFG27_OUTCFG111_TIMER110 = 22
, TIMER_OUTCFG27_OUTCFG111_TIMER111 = 23
,
TIMER_OUTCFG27_OUTCFG111_TIMER120 = 24
, TIMER_OUTCFG27_OUTCFG111_TIMER121 = 25
, TIMER_OUTCFG27_OUTCFG111_TIMER130 = 26
, TIMER_OUTCFG27_OUTCFG111_TIMER131 = 27
,
TIMER_OUTCFG27_OUTCFG111_TIMER140 = 28
, TIMER_OUTCFG27_OUTCFG111_TIMER141 = 29
, TIMER_OUTCFG27_OUTCFG111_TIMER150 = 30
, TIMER_OUTCFG27_OUTCFG111_TIMER151 = 31
,
TIMER_OUTCFG27_OUTCFG111_STIMER0 = 32
, TIMER_OUTCFG27_OUTCFG111_STIMER1 = 33
, TIMER_OUTCFG27_OUTCFG111_STIMER2 = 34
, TIMER_OUTCFG27_OUTCFG111_STIMER3 = 35
,
TIMER_OUTCFG27_OUTCFG111_STIMER4 = 36
, TIMER_OUTCFG27_OUTCFG111_STIMER5 = 37
, TIMER_OUTCFG27_OUTCFG111_STIMER6 = 38
, TIMER_OUTCFG27_OUTCFG111_STIMER7 = 39
,
TIMER_OUTCFG27_OUTCFG111_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG27_OUTCFG110_Enum {
TIMER_OUTCFG27_OUTCFG110_TIMER00 = 0
, TIMER_OUTCFG27_OUTCFG110_TIMER01 = 1
, TIMER_OUTCFG27_OUTCFG110_TIMER10 = 2
, TIMER_OUTCFG27_OUTCFG110_TIMER11 = 3
,
TIMER_OUTCFG27_OUTCFG110_TIMER20 = 4
, TIMER_OUTCFG27_OUTCFG110_TIMER21 = 5
, TIMER_OUTCFG27_OUTCFG110_TIMER30 = 6
, TIMER_OUTCFG27_OUTCFG110_TIMER31 = 7
,
TIMER_OUTCFG27_OUTCFG110_TIMER40 = 8
, TIMER_OUTCFG27_OUTCFG110_TIMER41 = 9
, TIMER_OUTCFG27_OUTCFG110_TIMER50 = 10
, TIMER_OUTCFG27_OUTCFG110_TIMER51 = 11
,
TIMER_OUTCFG27_OUTCFG110_TIMER60 = 12
, TIMER_OUTCFG27_OUTCFG110_TIMER61 = 13
, TIMER_OUTCFG27_OUTCFG110_TIMER70 = 14
, TIMER_OUTCFG27_OUTCFG110_TIMER71 = 15
,
TIMER_OUTCFG27_OUTCFG110_TIMER80 = 16
, TIMER_OUTCFG27_OUTCFG110_TIMER81 = 17
, TIMER_OUTCFG27_OUTCFG110_TIMER90 = 18
, TIMER_OUTCFG27_OUTCFG110_TIMER91 = 19
,
TIMER_OUTCFG27_OUTCFG110_TIMER100 = 20
, TIMER_OUTCFG27_OUTCFG110_TIMER101 = 21
, TIMER_OUTCFG27_OUTCFG110_TIMER110 = 22
, TIMER_OUTCFG27_OUTCFG110_TIMER111 = 23
,
TIMER_OUTCFG27_OUTCFG110_TIMER120 = 24
, TIMER_OUTCFG27_OUTCFG110_TIMER121 = 25
, TIMER_OUTCFG27_OUTCFG110_TIMER130 = 26
, TIMER_OUTCFG27_OUTCFG110_TIMER131 = 27
,
TIMER_OUTCFG27_OUTCFG110_TIMER140 = 28
, TIMER_OUTCFG27_OUTCFG110_TIMER141 = 29
, TIMER_OUTCFG27_OUTCFG110_TIMER150 = 30
, TIMER_OUTCFG27_OUTCFG110_TIMER151 = 31
,
TIMER_OUTCFG27_OUTCFG110_STIMER0 = 32
, TIMER_OUTCFG27_OUTCFG110_STIMER1 = 33
, TIMER_OUTCFG27_OUTCFG110_STIMER2 = 34
, TIMER_OUTCFG27_OUTCFG110_STIMER3 = 35
,
TIMER_OUTCFG27_OUTCFG110_STIMER4 = 36
, TIMER_OUTCFG27_OUTCFG110_STIMER5 = 37
, TIMER_OUTCFG27_OUTCFG110_STIMER6 = 38
, TIMER_OUTCFG27_OUTCFG110_STIMER7 = 39
,
TIMER_OUTCFG27_OUTCFG110_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG27_OUTCFG109_Enum {
TIMER_OUTCFG27_OUTCFG109_TIMER00 = 0
, TIMER_OUTCFG27_OUTCFG109_TIMER01 = 1
, TIMER_OUTCFG27_OUTCFG109_TIMER10 = 2
, TIMER_OUTCFG27_OUTCFG109_TIMER11 = 3
,
TIMER_OUTCFG27_OUTCFG109_TIMER20 = 4
, TIMER_OUTCFG27_OUTCFG109_TIMER21 = 5
, TIMER_OUTCFG27_OUTCFG109_TIMER30 = 6
, TIMER_OUTCFG27_OUTCFG109_TIMER31 = 7
,
TIMER_OUTCFG27_OUTCFG109_TIMER40 = 8
, TIMER_OUTCFG27_OUTCFG109_TIMER41 = 9
, TIMER_OUTCFG27_OUTCFG109_TIMER50 = 10
, TIMER_OUTCFG27_OUTCFG109_TIMER51 = 11
,
TIMER_OUTCFG27_OUTCFG109_TIMER60 = 12
, TIMER_OUTCFG27_OUTCFG109_TIMER61 = 13
, TIMER_OUTCFG27_OUTCFG109_TIMER70 = 14
, TIMER_OUTCFG27_OUTCFG109_TIMER71 = 15
,
TIMER_OUTCFG27_OUTCFG109_TIMER80 = 16
, TIMER_OUTCFG27_OUTCFG109_TIMER81 = 17
, TIMER_OUTCFG27_OUTCFG109_TIMER90 = 18
, TIMER_OUTCFG27_OUTCFG109_TIMER91 = 19
,
TIMER_OUTCFG27_OUTCFG109_TIMER100 = 20
, TIMER_OUTCFG27_OUTCFG109_TIMER101 = 21
, TIMER_OUTCFG27_OUTCFG109_TIMER110 = 22
, TIMER_OUTCFG27_OUTCFG109_TIMER111 = 23
,
TIMER_OUTCFG27_OUTCFG109_TIMER120 = 24
, TIMER_OUTCFG27_OUTCFG109_TIMER121 = 25
, TIMER_OUTCFG27_OUTCFG109_TIMER130 = 26
, TIMER_OUTCFG27_OUTCFG109_TIMER131 = 27
,
TIMER_OUTCFG27_OUTCFG109_TIMER140 = 28
, TIMER_OUTCFG27_OUTCFG109_TIMER141 = 29
, TIMER_OUTCFG27_OUTCFG109_TIMER150 = 30
, TIMER_OUTCFG27_OUTCFG109_TIMER151 = 31
,
TIMER_OUTCFG27_OUTCFG109_STIMER0 = 32
, TIMER_OUTCFG27_OUTCFG109_STIMER1 = 33
, TIMER_OUTCFG27_OUTCFG109_STIMER2 = 34
, TIMER_OUTCFG27_OUTCFG109_STIMER3 = 35
,
TIMER_OUTCFG27_OUTCFG109_STIMER4 = 36
, TIMER_OUTCFG27_OUTCFG109_STIMER5 = 37
, TIMER_OUTCFG27_OUTCFG109_STIMER6 = 38
, TIMER_OUTCFG27_OUTCFG109_STIMER7 = 39
,
TIMER_OUTCFG27_OUTCFG109_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG27_OUTCFG108_Enum {
TIMER_OUTCFG27_OUTCFG108_TIMER00 = 0
, TIMER_OUTCFG27_OUTCFG108_TIMER01 = 1
, TIMER_OUTCFG27_OUTCFG108_TIMER10 = 2
, TIMER_OUTCFG27_OUTCFG108_TIMER11 = 3
,
TIMER_OUTCFG27_OUTCFG108_TIMER20 = 4
, TIMER_OUTCFG27_OUTCFG108_TIMER21 = 5
, TIMER_OUTCFG27_OUTCFG108_TIMER30 = 6
, TIMER_OUTCFG27_OUTCFG108_TIMER31 = 7
,
TIMER_OUTCFG27_OUTCFG108_TIMER40 = 8
, TIMER_OUTCFG27_OUTCFG108_TIMER41 = 9
, TIMER_OUTCFG27_OUTCFG108_TIMER50 = 10
, TIMER_OUTCFG27_OUTCFG108_TIMER51 = 11
,
TIMER_OUTCFG27_OUTCFG108_TIMER60 = 12
, TIMER_OUTCFG27_OUTCFG108_TIMER61 = 13
, TIMER_OUTCFG27_OUTCFG108_TIMER70 = 14
, TIMER_OUTCFG27_OUTCFG108_TIMER71 = 15
,
TIMER_OUTCFG27_OUTCFG108_TIMER80 = 16
, TIMER_OUTCFG27_OUTCFG108_TIMER81 = 17
, TIMER_OUTCFG27_OUTCFG108_TIMER90 = 18
, TIMER_OUTCFG27_OUTCFG108_TIMER91 = 19
,
TIMER_OUTCFG27_OUTCFG108_TIMER100 = 20
, TIMER_OUTCFG27_OUTCFG108_TIMER101 = 21
, TIMER_OUTCFG27_OUTCFG108_TIMER110 = 22
, TIMER_OUTCFG27_OUTCFG108_TIMER111 = 23
,
TIMER_OUTCFG27_OUTCFG108_TIMER120 = 24
, TIMER_OUTCFG27_OUTCFG108_TIMER121 = 25
, TIMER_OUTCFG27_OUTCFG108_TIMER130 = 26
, TIMER_OUTCFG27_OUTCFG108_TIMER131 = 27
,
TIMER_OUTCFG27_OUTCFG108_TIMER140 = 28
, TIMER_OUTCFG27_OUTCFG108_TIMER141 = 29
, TIMER_OUTCFG27_OUTCFG108_TIMER150 = 30
, TIMER_OUTCFG27_OUTCFG108_TIMER151 = 31
,
TIMER_OUTCFG27_OUTCFG108_STIMER0 = 32
, TIMER_OUTCFG27_OUTCFG108_STIMER1 = 33
, TIMER_OUTCFG27_OUTCFG108_STIMER2 = 34
, TIMER_OUTCFG27_OUTCFG108_STIMER3 = 35
,
TIMER_OUTCFG27_OUTCFG108_STIMER4 = 36
, TIMER_OUTCFG27_OUTCFG108_STIMER5 = 37
, TIMER_OUTCFG27_OUTCFG108_STIMER6 = 38
, TIMER_OUTCFG27_OUTCFG108_STIMER7 = 39
,
TIMER_OUTCFG27_OUTCFG108_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG28_OUTCFG115_Enum {
TIMER_OUTCFG28_OUTCFG115_TIMER00 = 0
, TIMER_OUTCFG28_OUTCFG115_TIMER01 = 1
, TIMER_OUTCFG28_OUTCFG115_TIMER10 = 2
, TIMER_OUTCFG28_OUTCFG115_TIMER11 = 3
,
TIMER_OUTCFG28_OUTCFG115_TIMER20 = 4
, TIMER_OUTCFG28_OUTCFG115_TIMER21 = 5
, TIMER_OUTCFG28_OUTCFG115_TIMER30 = 6
, TIMER_OUTCFG28_OUTCFG115_TIMER31 = 7
,
TIMER_OUTCFG28_OUTCFG115_TIMER40 = 8
, TIMER_OUTCFG28_OUTCFG115_TIMER41 = 9
, TIMER_OUTCFG28_OUTCFG115_TIMER50 = 10
, TIMER_OUTCFG28_OUTCFG115_TIMER51 = 11
,
TIMER_OUTCFG28_OUTCFG115_TIMER60 = 12
, TIMER_OUTCFG28_OUTCFG115_TIMER61 = 13
, TIMER_OUTCFG28_OUTCFG115_TIMER70 = 14
, TIMER_OUTCFG28_OUTCFG115_TIMER71 = 15
,
TIMER_OUTCFG28_OUTCFG115_TIMER80 = 16
, TIMER_OUTCFG28_OUTCFG115_TIMER81 = 17
, TIMER_OUTCFG28_OUTCFG115_TIMER90 = 18
, TIMER_OUTCFG28_OUTCFG115_TIMER91 = 19
,
TIMER_OUTCFG28_OUTCFG115_TIMER100 = 20
, TIMER_OUTCFG28_OUTCFG115_TIMER101 = 21
, TIMER_OUTCFG28_OUTCFG115_TIMER110 = 22
, TIMER_OUTCFG28_OUTCFG115_TIMER111 = 23
,
TIMER_OUTCFG28_OUTCFG115_TIMER120 = 24
, TIMER_OUTCFG28_OUTCFG115_TIMER121 = 25
, TIMER_OUTCFG28_OUTCFG115_TIMER130 = 26
, TIMER_OUTCFG28_OUTCFG115_TIMER131 = 27
,
TIMER_OUTCFG28_OUTCFG115_TIMER140 = 28
, TIMER_OUTCFG28_OUTCFG115_TIMER141 = 29
, TIMER_OUTCFG28_OUTCFG115_TIMER150 = 30
, TIMER_OUTCFG28_OUTCFG115_TIMER151 = 31
,
TIMER_OUTCFG28_OUTCFG115_STIMER0 = 32
, TIMER_OUTCFG28_OUTCFG115_STIMER1 = 33
, TIMER_OUTCFG28_OUTCFG115_STIMER2 = 34
, TIMER_OUTCFG28_OUTCFG115_STIMER3 = 35
,
TIMER_OUTCFG28_OUTCFG115_STIMER4 = 36
, TIMER_OUTCFG28_OUTCFG115_STIMER5 = 37
, TIMER_OUTCFG28_OUTCFG115_STIMER6 = 38
, TIMER_OUTCFG28_OUTCFG115_STIMER7 = 39
,
TIMER_OUTCFG28_OUTCFG115_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG28_OUTCFG114_Enum {
TIMER_OUTCFG28_OUTCFG114_TIMER00 = 0
, TIMER_OUTCFG28_OUTCFG114_TIMER01 = 1
, TIMER_OUTCFG28_OUTCFG114_TIMER10 = 2
, TIMER_OUTCFG28_OUTCFG114_TIMER11 = 3
,
TIMER_OUTCFG28_OUTCFG114_TIMER20 = 4
, TIMER_OUTCFG28_OUTCFG114_TIMER21 = 5
, TIMER_OUTCFG28_OUTCFG114_TIMER30 = 6
, TIMER_OUTCFG28_OUTCFG114_TIMER31 = 7
,
TIMER_OUTCFG28_OUTCFG114_TIMER40 = 8
, TIMER_OUTCFG28_OUTCFG114_TIMER41 = 9
, TIMER_OUTCFG28_OUTCFG114_TIMER50 = 10
, TIMER_OUTCFG28_OUTCFG114_TIMER51 = 11
,
TIMER_OUTCFG28_OUTCFG114_TIMER60 = 12
, TIMER_OUTCFG28_OUTCFG114_TIMER61 = 13
, TIMER_OUTCFG28_OUTCFG114_TIMER70 = 14
, TIMER_OUTCFG28_OUTCFG114_TIMER71 = 15
,
TIMER_OUTCFG28_OUTCFG114_TIMER80 = 16
, TIMER_OUTCFG28_OUTCFG114_TIMER81 = 17
, TIMER_OUTCFG28_OUTCFG114_TIMER90 = 18
, TIMER_OUTCFG28_OUTCFG114_TIMER91 = 19
,
TIMER_OUTCFG28_OUTCFG114_TIMER100 = 20
, TIMER_OUTCFG28_OUTCFG114_TIMER101 = 21
, TIMER_OUTCFG28_OUTCFG114_TIMER110 = 22
, TIMER_OUTCFG28_OUTCFG114_TIMER111 = 23
,
TIMER_OUTCFG28_OUTCFG114_TIMER120 = 24
, TIMER_OUTCFG28_OUTCFG114_TIMER121 = 25
, TIMER_OUTCFG28_OUTCFG114_TIMER130 = 26
, TIMER_OUTCFG28_OUTCFG114_TIMER131 = 27
,
TIMER_OUTCFG28_OUTCFG114_TIMER140 = 28
, TIMER_OUTCFG28_OUTCFG114_TIMER141 = 29
, TIMER_OUTCFG28_OUTCFG114_TIMER150 = 30
, TIMER_OUTCFG28_OUTCFG114_TIMER151 = 31
,
TIMER_OUTCFG28_OUTCFG114_STIMER0 = 32
, TIMER_OUTCFG28_OUTCFG114_STIMER1 = 33
, TIMER_OUTCFG28_OUTCFG114_STIMER2 = 34
, TIMER_OUTCFG28_OUTCFG114_STIMER3 = 35
,
TIMER_OUTCFG28_OUTCFG114_STIMER4 = 36
, TIMER_OUTCFG28_OUTCFG114_STIMER5 = 37
, TIMER_OUTCFG28_OUTCFG114_STIMER6 = 38
, TIMER_OUTCFG28_OUTCFG114_STIMER7 = 39
,
TIMER_OUTCFG28_OUTCFG114_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG28_OUTCFG113_Enum {
TIMER_OUTCFG28_OUTCFG113_TIMER00 = 0
, TIMER_OUTCFG28_OUTCFG113_TIMER01 = 1
, TIMER_OUTCFG28_OUTCFG113_TIMER10 = 2
, TIMER_OUTCFG28_OUTCFG113_TIMER11 = 3
,
TIMER_OUTCFG28_OUTCFG113_TIMER20 = 4
, TIMER_OUTCFG28_OUTCFG113_TIMER21 = 5
, TIMER_OUTCFG28_OUTCFG113_TIMER30 = 6
, TIMER_OUTCFG28_OUTCFG113_TIMER31 = 7
,
TIMER_OUTCFG28_OUTCFG113_TIMER40 = 8
, TIMER_OUTCFG28_OUTCFG113_TIMER41 = 9
, TIMER_OUTCFG28_OUTCFG113_TIMER50 = 10
, TIMER_OUTCFG28_OUTCFG113_TIMER51 = 11
,
TIMER_OUTCFG28_OUTCFG113_TIMER60 = 12
, TIMER_OUTCFG28_OUTCFG113_TIMER61 = 13
, TIMER_OUTCFG28_OUTCFG113_TIMER70 = 14
, TIMER_OUTCFG28_OUTCFG113_TIMER71 = 15
,
TIMER_OUTCFG28_OUTCFG113_TIMER80 = 16
, TIMER_OUTCFG28_OUTCFG113_TIMER81 = 17
, TIMER_OUTCFG28_OUTCFG113_TIMER90 = 18
, TIMER_OUTCFG28_OUTCFG113_TIMER91 = 19
,
TIMER_OUTCFG28_OUTCFG113_TIMER100 = 20
, TIMER_OUTCFG28_OUTCFG113_TIMER101 = 21
, TIMER_OUTCFG28_OUTCFG113_TIMER110 = 22
, TIMER_OUTCFG28_OUTCFG113_TIMER111 = 23
,
TIMER_OUTCFG28_OUTCFG113_TIMER120 = 24
, TIMER_OUTCFG28_OUTCFG113_TIMER121 = 25
, TIMER_OUTCFG28_OUTCFG113_TIMER130 = 26
, TIMER_OUTCFG28_OUTCFG113_TIMER131 = 27
,
TIMER_OUTCFG28_OUTCFG113_TIMER140 = 28
, TIMER_OUTCFG28_OUTCFG113_TIMER141 = 29
, TIMER_OUTCFG28_OUTCFG113_TIMER150 = 30
, TIMER_OUTCFG28_OUTCFG113_TIMER151 = 31
,
TIMER_OUTCFG28_OUTCFG113_STIMER0 = 32
, TIMER_OUTCFG28_OUTCFG113_STIMER1 = 33
, TIMER_OUTCFG28_OUTCFG113_STIMER2 = 34
, TIMER_OUTCFG28_OUTCFG113_STIMER3 = 35
,
TIMER_OUTCFG28_OUTCFG113_STIMER4 = 36
, TIMER_OUTCFG28_OUTCFG113_STIMER5 = 37
, TIMER_OUTCFG28_OUTCFG113_STIMER6 = 38
, TIMER_OUTCFG28_OUTCFG113_STIMER7 = 39
,
TIMER_OUTCFG28_OUTCFG113_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG28_OUTCFG112_Enum {
TIMER_OUTCFG28_OUTCFG112_TIMER00 = 0
, TIMER_OUTCFG28_OUTCFG112_TIMER01 = 1
, TIMER_OUTCFG28_OUTCFG112_TIMER10 = 2
, TIMER_OUTCFG28_OUTCFG112_TIMER11 = 3
,
TIMER_OUTCFG28_OUTCFG112_TIMER20 = 4
, TIMER_OUTCFG28_OUTCFG112_TIMER21 = 5
, TIMER_OUTCFG28_OUTCFG112_TIMER30 = 6
, TIMER_OUTCFG28_OUTCFG112_TIMER31 = 7
,
TIMER_OUTCFG28_OUTCFG112_TIMER40 = 8
, TIMER_OUTCFG28_OUTCFG112_TIMER41 = 9
, TIMER_OUTCFG28_OUTCFG112_TIMER50 = 10
, TIMER_OUTCFG28_OUTCFG112_TIMER51 = 11
,
TIMER_OUTCFG28_OUTCFG112_TIMER60 = 12
, TIMER_OUTCFG28_OUTCFG112_TIMER61 = 13
, TIMER_OUTCFG28_OUTCFG112_TIMER70 = 14
, TIMER_OUTCFG28_OUTCFG112_TIMER71 = 15
,
TIMER_OUTCFG28_OUTCFG112_TIMER80 = 16
, TIMER_OUTCFG28_OUTCFG112_TIMER81 = 17
, TIMER_OUTCFG28_OUTCFG112_TIMER90 = 18
, TIMER_OUTCFG28_OUTCFG112_TIMER91 = 19
,
TIMER_OUTCFG28_OUTCFG112_TIMER100 = 20
, TIMER_OUTCFG28_OUTCFG112_TIMER101 = 21
, TIMER_OUTCFG28_OUTCFG112_TIMER110 = 22
, TIMER_OUTCFG28_OUTCFG112_TIMER111 = 23
,
TIMER_OUTCFG28_OUTCFG112_TIMER120 = 24
, TIMER_OUTCFG28_OUTCFG112_TIMER121 = 25
, TIMER_OUTCFG28_OUTCFG112_TIMER130 = 26
, TIMER_OUTCFG28_OUTCFG112_TIMER131 = 27
,
TIMER_OUTCFG28_OUTCFG112_TIMER140 = 28
, TIMER_OUTCFG28_OUTCFG112_TIMER141 = 29
, TIMER_OUTCFG28_OUTCFG112_TIMER150 = 30
, TIMER_OUTCFG28_OUTCFG112_TIMER151 = 31
,
TIMER_OUTCFG28_OUTCFG112_STIMER0 = 32
, TIMER_OUTCFG28_OUTCFG112_STIMER1 = 33
, TIMER_OUTCFG28_OUTCFG112_STIMER2 = 34
, TIMER_OUTCFG28_OUTCFG112_STIMER3 = 35
,
TIMER_OUTCFG28_OUTCFG112_STIMER4 = 36
, TIMER_OUTCFG28_OUTCFG112_STIMER5 = 37
, TIMER_OUTCFG28_OUTCFG112_STIMER6 = 38
, TIMER_OUTCFG28_OUTCFG112_STIMER7 = 39
,
TIMER_OUTCFG28_OUTCFG112_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG29_OUTCFG119_Enum {
TIMER_OUTCFG29_OUTCFG119_TIMER00 = 0
, TIMER_OUTCFG29_OUTCFG119_TIMER01 = 1
, TIMER_OUTCFG29_OUTCFG119_TIMER10 = 2
, TIMER_OUTCFG29_OUTCFG119_TIMER11 = 3
,
TIMER_OUTCFG29_OUTCFG119_TIMER20 = 4
, TIMER_OUTCFG29_OUTCFG119_TIMER21 = 5
, TIMER_OUTCFG29_OUTCFG119_TIMER30 = 6
, TIMER_OUTCFG29_OUTCFG119_TIMER31 = 7
,
TIMER_OUTCFG29_OUTCFG119_TIMER40 = 8
, TIMER_OUTCFG29_OUTCFG119_TIMER41 = 9
, TIMER_OUTCFG29_OUTCFG119_TIMER50 = 10
, TIMER_OUTCFG29_OUTCFG119_TIMER51 = 11
,
TIMER_OUTCFG29_OUTCFG119_TIMER60 = 12
, TIMER_OUTCFG29_OUTCFG119_TIMER61 = 13
, TIMER_OUTCFG29_OUTCFG119_TIMER70 = 14
, TIMER_OUTCFG29_OUTCFG119_TIMER71 = 15
,
TIMER_OUTCFG29_OUTCFG119_TIMER80 = 16
, TIMER_OUTCFG29_OUTCFG119_TIMER81 = 17
, TIMER_OUTCFG29_OUTCFG119_TIMER90 = 18
, TIMER_OUTCFG29_OUTCFG119_TIMER91 = 19
,
TIMER_OUTCFG29_OUTCFG119_TIMER100 = 20
, TIMER_OUTCFG29_OUTCFG119_TIMER101 = 21
, TIMER_OUTCFG29_OUTCFG119_TIMER110 = 22
, TIMER_OUTCFG29_OUTCFG119_TIMER111 = 23
,
TIMER_OUTCFG29_OUTCFG119_TIMER120 = 24
, TIMER_OUTCFG29_OUTCFG119_TIMER121 = 25
, TIMER_OUTCFG29_OUTCFG119_TIMER130 = 26
, TIMER_OUTCFG29_OUTCFG119_TIMER131 = 27
,
TIMER_OUTCFG29_OUTCFG119_TIMER140 = 28
, TIMER_OUTCFG29_OUTCFG119_TIMER141 = 29
, TIMER_OUTCFG29_OUTCFG119_TIMER150 = 30
, TIMER_OUTCFG29_OUTCFG119_TIMER151 = 31
,
TIMER_OUTCFG29_OUTCFG119_STIMER0 = 32
, TIMER_OUTCFG29_OUTCFG119_STIMER1 = 33
, TIMER_OUTCFG29_OUTCFG119_STIMER2 = 34
, TIMER_OUTCFG29_OUTCFG119_STIMER3 = 35
,
TIMER_OUTCFG29_OUTCFG119_STIMER4 = 36
, TIMER_OUTCFG29_OUTCFG119_STIMER5 = 37
, TIMER_OUTCFG29_OUTCFG119_STIMER6 = 38
, TIMER_OUTCFG29_OUTCFG119_STIMER7 = 39
,
TIMER_OUTCFG29_OUTCFG119_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG29_OUTCFG118_Enum {
TIMER_OUTCFG29_OUTCFG118_TIMER00 = 0
, TIMER_OUTCFG29_OUTCFG118_TIMER01 = 1
, TIMER_OUTCFG29_OUTCFG118_TIMER10 = 2
, TIMER_OUTCFG29_OUTCFG118_TIMER11 = 3
,
TIMER_OUTCFG29_OUTCFG118_TIMER20 = 4
, TIMER_OUTCFG29_OUTCFG118_TIMER21 = 5
, TIMER_OUTCFG29_OUTCFG118_TIMER30 = 6
, TIMER_OUTCFG29_OUTCFG118_TIMER31 = 7
,
TIMER_OUTCFG29_OUTCFG118_TIMER40 = 8
, TIMER_OUTCFG29_OUTCFG118_TIMER41 = 9
, TIMER_OUTCFG29_OUTCFG118_TIMER50 = 10
, TIMER_OUTCFG29_OUTCFG118_TIMER51 = 11
,
TIMER_OUTCFG29_OUTCFG118_TIMER60 = 12
, TIMER_OUTCFG29_OUTCFG118_TIMER61 = 13
, TIMER_OUTCFG29_OUTCFG118_TIMER70 = 14
, TIMER_OUTCFG29_OUTCFG118_TIMER71 = 15
,
TIMER_OUTCFG29_OUTCFG118_TIMER80 = 16
, TIMER_OUTCFG29_OUTCFG118_TIMER81 = 17
, TIMER_OUTCFG29_OUTCFG118_TIMER90 = 18
, TIMER_OUTCFG29_OUTCFG118_TIMER91 = 19
,
TIMER_OUTCFG29_OUTCFG118_TIMER100 = 20
, TIMER_OUTCFG29_OUTCFG118_TIMER101 = 21
, TIMER_OUTCFG29_OUTCFG118_TIMER110 = 22
, TIMER_OUTCFG29_OUTCFG118_TIMER111 = 23
,
TIMER_OUTCFG29_OUTCFG118_TIMER120 = 24
, TIMER_OUTCFG29_OUTCFG118_TIMER121 = 25
, TIMER_OUTCFG29_OUTCFG118_TIMER130 = 26
, TIMER_OUTCFG29_OUTCFG118_TIMER131 = 27
,
TIMER_OUTCFG29_OUTCFG118_TIMER140 = 28
, TIMER_OUTCFG29_OUTCFG118_TIMER141 = 29
, TIMER_OUTCFG29_OUTCFG118_TIMER150 = 30
, TIMER_OUTCFG29_OUTCFG118_TIMER151 = 31
,
TIMER_OUTCFG29_OUTCFG118_STIMER0 = 32
, TIMER_OUTCFG29_OUTCFG118_STIMER1 = 33
, TIMER_OUTCFG29_OUTCFG118_STIMER2 = 34
, TIMER_OUTCFG29_OUTCFG118_STIMER3 = 35
,
TIMER_OUTCFG29_OUTCFG118_STIMER4 = 36
, TIMER_OUTCFG29_OUTCFG118_STIMER5 = 37
, TIMER_OUTCFG29_OUTCFG118_STIMER6 = 38
, TIMER_OUTCFG29_OUTCFG118_STIMER7 = 39
,
TIMER_OUTCFG29_OUTCFG118_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG29_OUTCFG117_Enum {
TIMER_OUTCFG29_OUTCFG117_TIMER00 = 0
, TIMER_OUTCFG29_OUTCFG117_TIMER01 = 1
, TIMER_OUTCFG29_OUTCFG117_TIMER10 = 2
, TIMER_OUTCFG29_OUTCFG117_TIMER11 = 3
,
TIMER_OUTCFG29_OUTCFG117_TIMER20 = 4
, TIMER_OUTCFG29_OUTCFG117_TIMER21 = 5
, TIMER_OUTCFG29_OUTCFG117_TIMER30 = 6
, TIMER_OUTCFG29_OUTCFG117_TIMER31 = 7
,
TIMER_OUTCFG29_OUTCFG117_TIMER40 = 8
, TIMER_OUTCFG29_OUTCFG117_TIMER41 = 9
, TIMER_OUTCFG29_OUTCFG117_TIMER50 = 10
, TIMER_OUTCFG29_OUTCFG117_TIMER51 = 11
,
TIMER_OUTCFG29_OUTCFG117_TIMER60 = 12
, TIMER_OUTCFG29_OUTCFG117_TIMER61 = 13
, TIMER_OUTCFG29_OUTCFG117_TIMER70 = 14
, TIMER_OUTCFG29_OUTCFG117_TIMER71 = 15
,
TIMER_OUTCFG29_OUTCFG117_TIMER80 = 16
, TIMER_OUTCFG29_OUTCFG117_TIMER81 = 17
, TIMER_OUTCFG29_OUTCFG117_TIMER90 = 18
, TIMER_OUTCFG29_OUTCFG117_TIMER91 = 19
,
TIMER_OUTCFG29_OUTCFG117_TIMER100 = 20
, TIMER_OUTCFG29_OUTCFG117_TIMER101 = 21
, TIMER_OUTCFG29_OUTCFG117_TIMER110 = 22
, TIMER_OUTCFG29_OUTCFG117_TIMER111 = 23
,
TIMER_OUTCFG29_OUTCFG117_TIMER120 = 24
, TIMER_OUTCFG29_OUTCFG117_TIMER121 = 25
, TIMER_OUTCFG29_OUTCFG117_TIMER130 = 26
, TIMER_OUTCFG29_OUTCFG117_TIMER131 = 27
,
TIMER_OUTCFG29_OUTCFG117_TIMER140 = 28
, TIMER_OUTCFG29_OUTCFG117_TIMER141 = 29
, TIMER_OUTCFG29_OUTCFG117_TIMER150 = 30
, TIMER_OUTCFG29_OUTCFG117_TIMER151 = 31
,
TIMER_OUTCFG29_OUTCFG117_STIMER0 = 32
, TIMER_OUTCFG29_OUTCFG117_STIMER1 = 33
, TIMER_OUTCFG29_OUTCFG117_STIMER2 = 34
, TIMER_OUTCFG29_OUTCFG117_STIMER3 = 35
,
TIMER_OUTCFG29_OUTCFG117_STIMER4 = 36
, TIMER_OUTCFG29_OUTCFG117_STIMER5 = 37
, TIMER_OUTCFG29_OUTCFG117_STIMER6 = 38
, TIMER_OUTCFG29_OUTCFG117_STIMER7 = 39
,
TIMER_OUTCFG29_OUTCFG117_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG29_OUTCFG116_Enum {
TIMER_OUTCFG29_OUTCFG116_TIMER00 = 0
, TIMER_OUTCFG29_OUTCFG116_TIMER01 = 1
, TIMER_OUTCFG29_OUTCFG116_TIMER10 = 2
, TIMER_OUTCFG29_OUTCFG116_TIMER11 = 3
,
TIMER_OUTCFG29_OUTCFG116_TIMER20 = 4
, TIMER_OUTCFG29_OUTCFG116_TIMER21 = 5
, TIMER_OUTCFG29_OUTCFG116_TIMER30 = 6
, TIMER_OUTCFG29_OUTCFG116_TIMER31 = 7
,
TIMER_OUTCFG29_OUTCFG116_TIMER40 = 8
, TIMER_OUTCFG29_OUTCFG116_TIMER41 = 9
, TIMER_OUTCFG29_OUTCFG116_TIMER50 = 10
, TIMER_OUTCFG29_OUTCFG116_TIMER51 = 11
,
TIMER_OUTCFG29_OUTCFG116_TIMER60 = 12
, TIMER_OUTCFG29_OUTCFG116_TIMER61 = 13
, TIMER_OUTCFG29_OUTCFG116_TIMER70 = 14
, TIMER_OUTCFG29_OUTCFG116_TIMER71 = 15
,
TIMER_OUTCFG29_OUTCFG116_TIMER80 = 16
, TIMER_OUTCFG29_OUTCFG116_TIMER81 = 17
, TIMER_OUTCFG29_OUTCFG116_TIMER90 = 18
, TIMER_OUTCFG29_OUTCFG116_TIMER91 = 19
,
TIMER_OUTCFG29_OUTCFG116_TIMER100 = 20
, TIMER_OUTCFG29_OUTCFG116_TIMER101 = 21
, TIMER_OUTCFG29_OUTCFG116_TIMER110 = 22
, TIMER_OUTCFG29_OUTCFG116_TIMER111 = 23
,
TIMER_OUTCFG29_OUTCFG116_TIMER120 = 24
, TIMER_OUTCFG29_OUTCFG116_TIMER121 = 25
, TIMER_OUTCFG29_OUTCFG116_TIMER130 = 26
, TIMER_OUTCFG29_OUTCFG116_TIMER131 = 27
,
TIMER_OUTCFG29_OUTCFG116_TIMER140 = 28
, TIMER_OUTCFG29_OUTCFG116_TIMER141 = 29
, TIMER_OUTCFG29_OUTCFG116_TIMER150 = 30
, TIMER_OUTCFG29_OUTCFG116_TIMER151 = 31
,
TIMER_OUTCFG29_OUTCFG116_STIMER0 = 32
, TIMER_OUTCFG29_OUTCFG116_STIMER1 = 33
, TIMER_OUTCFG29_OUTCFG116_STIMER2 = 34
, TIMER_OUTCFG29_OUTCFG116_STIMER3 = 35
,
TIMER_OUTCFG29_OUTCFG116_STIMER4 = 36
, TIMER_OUTCFG29_OUTCFG116_STIMER5 = 37
, TIMER_OUTCFG29_OUTCFG116_STIMER6 = 38
, TIMER_OUTCFG29_OUTCFG116_STIMER7 = 39
,
TIMER_OUTCFG29_OUTCFG116_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG30_OUTCFG123_Enum {
TIMER_OUTCFG30_OUTCFG123_TIMER00 = 0
, TIMER_OUTCFG30_OUTCFG123_TIMER01 = 1
, TIMER_OUTCFG30_OUTCFG123_TIMER10 = 2
, TIMER_OUTCFG30_OUTCFG123_TIMER11 = 3
,
TIMER_OUTCFG30_OUTCFG123_TIMER20 = 4
, TIMER_OUTCFG30_OUTCFG123_TIMER21 = 5
, TIMER_OUTCFG30_OUTCFG123_TIMER30 = 6
, TIMER_OUTCFG30_OUTCFG123_TIMER31 = 7
,
TIMER_OUTCFG30_OUTCFG123_TIMER40 = 8
, TIMER_OUTCFG30_OUTCFG123_TIMER41 = 9
, TIMER_OUTCFG30_OUTCFG123_TIMER50 = 10
, TIMER_OUTCFG30_OUTCFG123_TIMER51 = 11
,
TIMER_OUTCFG30_OUTCFG123_TIMER60 = 12
, TIMER_OUTCFG30_OUTCFG123_TIMER61 = 13
, TIMER_OUTCFG30_OUTCFG123_TIMER70 = 14
, TIMER_OUTCFG30_OUTCFG123_TIMER71 = 15
,
TIMER_OUTCFG30_OUTCFG123_TIMER80 = 16
, TIMER_OUTCFG30_OUTCFG123_TIMER81 = 17
, TIMER_OUTCFG30_OUTCFG123_TIMER90 = 18
, TIMER_OUTCFG30_OUTCFG123_TIMER91 = 19
,
TIMER_OUTCFG30_OUTCFG123_TIMER100 = 20
, TIMER_OUTCFG30_OUTCFG123_TIMER101 = 21
, TIMER_OUTCFG30_OUTCFG123_TIMER110 = 22
, TIMER_OUTCFG30_OUTCFG123_TIMER111 = 23
,
TIMER_OUTCFG30_OUTCFG123_TIMER120 = 24
, TIMER_OUTCFG30_OUTCFG123_TIMER121 = 25
, TIMER_OUTCFG30_OUTCFG123_TIMER130 = 26
, TIMER_OUTCFG30_OUTCFG123_TIMER131 = 27
,
TIMER_OUTCFG30_OUTCFG123_TIMER140 = 28
, TIMER_OUTCFG30_OUTCFG123_TIMER141 = 29
, TIMER_OUTCFG30_OUTCFG123_TIMER150 = 30
, TIMER_OUTCFG30_OUTCFG123_TIMER151 = 31
,
TIMER_OUTCFG30_OUTCFG123_STIMER0 = 32
, TIMER_OUTCFG30_OUTCFG123_STIMER1 = 33
, TIMER_OUTCFG30_OUTCFG123_STIMER2 = 34
, TIMER_OUTCFG30_OUTCFG123_STIMER3 = 35
,
TIMER_OUTCFG30_OUTCFG123_STIMER4 = 36
, TIMER_OUTCFG30_OUTCFG123_STIMER5 = 37
, TIMER_OUTCFG30_OUTCFG123_STIMER6 = 38
, TIMER_OUTCFG30_OUTCFG123_STIMER7 = 39
,
TIMER_OUTCFG30_OUTCFG123_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG30_OUTCFG122_Enum {
TIMER_OUTCFG30_OUTCFG122_TIMER00 = 0
, TIMER_OUTCFG30_OUTCFG122_TIMER01 = 1
, TIMER_OUTCFG30_OUTCFG122_TIMER10 = 2
, TIMER_OUTCFG30_OUTCFG122_TIMER11 = 3
,
TIMER_OUTCFG30_OUTCFG122_TIMER20 = 4
, TIMER_OUTCFG30_OUTCFG122_TIMER21 = 5
, TIMER_OUTCFG30_OUTCFG122_TIMER30 = 6
, TIMER_OUTCFG30_OUTCFG122_TIMER31 = 7
,
TIMER_OUTCFG30_OUTCFG122_TIMER40 = 8
, TIMER_OUTCFG30_OUTCFG122_TIMER41 = 9
, TIMER_OUTCFG30_OUTCFG122_TIMER50 = 10
, TIMER_OUTCFG30_OUTCFG122_TIMER51 = 11
,
TIMER_OUTCFG30_OUTCFG122_TIMER60 = 12
, TIMER_OUTCFG30_OUTCFG122_TIMER61 = 13
, TIMER_OUTCFG30_OUTCFG122_TIMER70 = 14
, TIMER_OUTCFG30_OUTCFG122_TIMER71 = 15
,
TIMER_OUTCFG30_OUTCFG122_TIMER80 = 16
, TIMER_OUTCFG30_OUTCFG122_TIMER81 = 17
, TIMER_OUTCFG30_OUTCFG122_TIMER90 = 18
, TIMER_OUTCFG30_OUTCFG122_TIMER91 = 19
,
TIMER_OUTCFG30_OUTCFG122_TIMER100 = 20
, TIMER_OUTCFG30_OUTCFG122_TIMER101 = 21
, TIMER_OUTCFG30_OUTCFG122_TIMER110 = 22
, TIMER_OUTCFG30_OUTCFG122_TIMER111 = 23
,
TIMER_OUTCFG30_OUTCFG122_TIMER120 = 24
, TIMER_OUTCFG30_OUTCFG122_TIMER121 = 25
, TIMER_OUTCFG30_OUTCFG122_TIMER130 = 26
, TIMER_OUTCFG30_OUTCFG122_TIMER131 = 27
,
TIMER_OUTCFG30_OUTCFG122_TIMER140 = 28
, TIMER_OUTCFG30_OUTCFG122_TIMER141 = 29
, TIMER_OUTCFG30_OUTCFG122_TIMER150 = 30
, TIMER_OUTCFG30_OUTCFG122_TIMER151 = 31
,
TIMER_OUTCFG30_OUTCFG122_STIMER0 = 32
, TIMER_OUTCFG30_OUTCFG122_STIMER1 = 33
, TIMER_OUTCFG30_OUTCFG122_STIMER2 = 34
, TIMER_OUTCFG30_OUTCFG122_STIMER3 = 35
,
TIMER_OUTCFG30_OUTCFG122_STIMER4 = 36
, TIMER_OUTCFG30_OUTCFG122_STIMER5 = 37
, TIMER_OUTCFG30_OUTCFG122_STIMER6 = 38
, TIMER_OUTCFG30_OUTCFG122_STIMER7 = 39
,
TIMER_OUTCFG30_OUTCFG122_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG30_OUTCFG121_Enum {
TIMER_OUTCFG30_OUTCFG121_TIMER00 = 0
, TIMER_OUTCFG30_OUTCFG121_TIMER01 = 1
, TIMER_OUTCFG30_OUTCFG121_TIMER10 = 2
, TIMER_OUTCFG30_OUTCFG121_TIMER11 = 3
,
TIMER_OUTCFG30_OUTCFG121_TIMER20 = 4
, TIMER_OUTCFG30_OUTCFG121_TIMER21 = 5
, TIMER_OUTCFG30_OUTCFG121_TIMER30 = 6
, TIMER_OUTCFG30_OUTCFG121_TIMER31 = 7
,
TIMER_OUTCFG30_OUTCFG121_TIMER40 = 8
, TIMER_OUTCFG30_OUTCFG121_TIMER41 = 9
, TIMER_OUTCFG30_OUTCFG121_TIMER50 = 10
, TIMER_OUTCFG30_OUTCFG121_TIMER51 = 11
,
TIMER_OUTCFG30_OUTCFG121_TIMER60 = 12
, TIMER_OUTCFG30_OUTCFG121_TIMER61 = 13
, TIMER_OUTCFG30_OUTCFG121_TIMER70 = 14
, TIMER_OUTCFG30_OUTCFG121_TIMER71 = 15
,
TIMER_OUTCFG30_OUTCFG121_TIMER80 = 16
, TIMER_OUTCFG30_OUTCFG121_TIMER81 = 17
, TIMER_OUTCFG30_OUTCFG121_TIMER90 = 18
, TIMER_OUTCFG30_OUTCFG121_TIMER91 = 19
,
TIMER_OUTCFG30_OUTCFG121_TIMER100 = 20
, TIMER_OUTCFG30_OUTCFG121_TIMER101 = 21
, TIMER_OUTCFG30_OUTCFG121_TIMER110 = 22
, TIMER_OUTCFG30_OUTCFG121_TIMER111 = 23
,
TIMER_OUTCFG30_OUTCFG121_TIMER120 = 24
, TIMER_OUTCFG30_OUTCFG121_TIMER121 = 25
, TIMER_OUTCFG30_OUTCFG121_TIMER130 = 26
, TIMER_OUTCFG30_OUTCFG121_TIMER131 = 27
,
TIMER_OUTCFG30_OUTCFG121_TIMER140 = 28
, TIMER_OUTCFG30_OUTCFG121_TIMER141 = 29
, TIMER_OUTCFG30_OUTCFG121_TIMER150 = 30
, TIMER_OUTCFG30_OUTCFG121_TIMER151 = 31
,
TIMER_OUTCFG30_OUTCFG121_STIMER0 = 32
, TIMER_OUTCFG30_OUTCFG121_STIMER1 = 33
, TIMER_OUTCFG30_OUTCFG121_STIMER2 = 34
, TIMER_OUTCFG30_OUTCFG121_STIMER3 = 35
,
TIMER_OUTCFG30_OUTCFG121_STIMER4 = 36
, TIMER_OUTCFG30_OUTCFG121_STIMER5 = 37
, TIMER_OUTCFG30_OUTCFG121_STIMER6 = 38
, TIMER_OUTCFG30_OUTCFG121_STIMER7 = 39
,
TIMER_OUTCFG30_OUTCFG121_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG30_OUTCFG120_Enum {
TIMER_OUTCFG30_OUTCFG120_TIMER00 = 0
, TIMER_OUTCFG30_OUTCFG120_TIMER01 = 1
, TIMER_OUTCFG30_OUTCFG120_TIMER10 = 2
, TIMER_OUTCFG30_OUTCFG120_TIMER11 = 3
,
TIMER_OUTCFG30_OUTCFG120_TIMER20 = 4
, TIMER_OUTCFG30_OUTCFG120_TIMER21 = 5
, TIMER_OUTCFG30_OUTCFG120_TIMER30 = 6
, TIMER_OUTCFG30_OUTCFG120_TIMER31 = 7
,
TIMER_OUTCFG30_OUTCFG120_TIMER40 = 8
, TIMER_OUTCFG30_OUTCFG120_TIMER41 = 9
, TIMER_OUTCFG30_OUTCFG120_TIMER50 = 10
, TIMER_OUTCFG30_OUTCFG120_TIMER51 = 11
,
TIMER_OUTCFG30_OUTCFG120_TIMER60 = 12
, TIMER_OUTCFG30_OUTCFG120_TIMER61 = 13
, TIMER_OUTCFG30_OUTCFG120_TIMER70 = 14
, TIMER_OUTCFG30_OUTCFG120_TIMER71 = 15
,
TIMER_OUTCFG30_OUTCFG120_TIMER80 = 16
, TIMER_OUTCFG30_OUTCFG120_TIMER81 = 17
, TIMER_OUTCFG30_OUTCFG120_TIMER90 = 18
, TIMER_OUTCFG30_OUTCFG120_TIMER91 = 19
,
TIMER_OUTCFG30_OUTCFG120_TIMER100 = 20
, TIMER_OUTCFG30_OUTCFG120_TIMER101 = 21
, TIMER_OUTCFG30_OUTCFG120_TIMER110 = 22
, TIMER_OUTCFG30_OUTCFG120_TIMER111 = 23
,
TIMER_OUTCFG30_OUTCFG120_TIMER120 = 24
, TIMER_OUTCFG30_OUTCFG120_TIMER121 = 25
, TIMER_OUTCFG30_OUTCFG120_TIMER130 = 26
, TIMER_OUTCFG30_OUTCFG120_TIMER131 = 27
,
TIMER_OUTCFG30_OUTCFG120_TIMER140 = 28
, TIMER_OUTCFG30_OUTCFG120_TIMER141 = 29
, TIMER_OUTCFG30_OUTCFG120_TIMER150 = 30
, TIMER_OUTCFG30_OUTCFG120_TIMER151 = 31
,
TIMER_OUTCFG30_OUTCFG120_STIMER0 = 32
, TIMER_OUTCFG30_OUTCFG120_STIMER1 = 33
, TIMER_OUTCFG30_OUTCFG120_STIMER2 = 34
, TIMER_OUTCFG30_OUTCFG120_STIMER3 = 35
,
TIMER_OUTCFG30_OUTCFG120_STIMER4 = 36
, TIMER_OUTCFG30_OUTCFG120_STIMER5 = 37
, TIMER_OUTCFG30_OUTCFG120_STIMER6 = 38
, TIMER_OUTCFG30_OUTCFG120_STIMER7 = 39
,
TIMER_OUTCFG30_OUTCFG120_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG31_OUTCFG127_Enum {
TIMER_OUTCFG31_OUTCFG127_TIMER00 = 0
, TIMER_OUTCFG31_OUTCFG127_TIMER01 = 1
, TIMER_OUTCFG31_OUTCFG127_TIMER10 = 2
, TIMER_OUTCFG31_OUTCFG127_TIMER11 = 3
,
TIMER_OUTCFG31_OUTCFG127_TIMER20 = 4
, TIMER_OUTCFG31_OUTCFG127_TIMER21 = 5
, TIMER_OUTCFG31_OUTCFG127_TIMER30 = 6
, TIMER_OUTCFG31_OUTCFG127_TIMER31 = 7
,
TIMER_OUTCFG31_OUTCFG127_TIMER40 = 8
, TIMER_OUTCFG31_OUTCFG127_TIMER41 = 9
, TIMER_OUTCFG31_OUTCFG127_TIMER50 = 10
, TIMER_OUTCFG31_OUTCFG127_TIMER51 = 11
,
TIMER_OUTCFG31_OUTCFG127_TIMER60 = 12
, TIMER_OUTCFG31_OUTCFG127_TIMER61 = 13
, TIMER_OUTCFG31_OUTCFG127_TIMER70 = 14
, TIMER_OUTCFG31_OUTCFG127_TIMER71 = 15
,
TIMER_OUTCFG31_OUTCFG127_TIMER80 = 16
, TIMER_OUTCFG31_OUTCFG127_TIMER81 = 17
, TIMER_OUTCFG31_OUTCFG127_TIMER90 = 18
, TIMER_OUTCFG31_OUTCFG127_TIMER91 = 19
,
TIMER_OUTCFG31_OUTCFG127_TIMER100 = 20
, TIMER_OUTCFG31_OUTCFG127_TIMER101 = 21
, TIMER_OUTCFG31_OUTCFG127_TIMER110 = 22
, TIMER_OUTCFG31_OUTCFG127_TIMER111 = 23
,
TIMER_OUTCFG31_OUTCFG127_TIMER120 = 24
, TIMER_OUTCFG31_OUTCFG127_TIMER121 = 25
, TIMER_OUTCFG31_OUTCFG127_TIMER130 = 26
, TIMER_OUTCFG31_OUTCFG127_TIMER131 = 27
,
TIMER_OUTCFG31_OUTCFG127_TIMER140 = 28
, TIMER_OUTCFG31_OUTCFG127_TIMER141 = 29
, TIMER_OUTCFG31_OUTCFG127_TIMER150 = 30
, TIMER_OUTCFG31_OUTCFG127_TIMER151 = 31
,
TIMER_OUTCFG31_OUTCFG127_STIMER0 = 32
, TIMER_OUTCFG31_OUTCFG127_STIMER1 = 33
, TIMER_OUTCFG31_OUTCFG127_STIMER2 = 34
, TIMER_OUTCFG31_OUTCFG127_STIMER3 = 35
,
TIMER_OUTCFG31_OUTCFG127_STIMER4 = 36
, TIMER_OUTCFG31_OUTCFG127_STIMER5 = 37
, TIMER_OUTCFG31_OUTCFG127_STIMER6 = 38
, TIMER_OUTCFG31_OUTCFG127_STIMER7 = 39
,
TIMER_OUTCFG31_OUTCFG127_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG31_OUTCFG126_Enum {
TIMER_OUTCFG31_OUTCFG126_TIMER00 = 0
, TIMER_OUTCFG31_OUTCFG126_TIMER01 = 1
, TIMER_OUTCFG31_OUTCFG126_TIMER10 = 2
, TIMER_OUTCFG31_OUTCFG126_TIMER11 = 3
,
TIMER_OUTCFG31_OUTCFG126_TIMER20 = 4
, TIMER_OUTCFG31_OUTCFG126_TIMER21 = 5
, TIMER_OUTCFG31_OUTCFG126_TIMER30 = 6
, TIMER_OUTCFG31_OUTCFG126_TIMER31 = 7
,
TIMER_OUTCFG31_OUTCFG126_TIMER40 = 8
, TIMER_OUTCFG31_OUTCFG126_TIMER41 = 9
, TIMER_OUTCFG31_OUTCFG126_TIMER50 = 10
, TIMER_OUTCFG31_OUTCFG126_TIMER51 = 11
,
TIMER_OUTCFG31_OUTCFG126_TIMER60 = 12
, TIMER_OUTCFG31_OUTCFG126_TIMER61 = 13
, TIMER_OUTCFG31_OUTCFG126_TIMER70 = 14
, TIMER_OUTCFG31_OUTCFG126_TIMER71 = 15
,
TIMER_OUTCFG31_OUTCFG126_TIMER80 = 16
, TIMER_OUTCFG31_OUTCFG126_TIMER81 = 17
, TIMER_OUTCFG31_OUTCFG126_TIMER90 = 18
, TIMER_OUTCFG31_OUTCFG126_TIMER91 = 19
,
TIMER_OUTCFG31_OUTCFG126_TIMER100 = 20
, TIMER_OUTCFG31_OUTCFG126_TIMER101 = 21
, TIMER_OUTCFG31_OUTCFG126_TIMER110 = 22
, TIMER_OUTCFG31_OUTCFG126_TIMER111 = 23
,
TIMER_OUTCFG31_OUTCFG126_TIMER120 = 24
, TIMER_OUTCFG31_OUTCFG126_TIMER121 = 25
, TIMER_OUTCFG31_OUTCFG126_TIMER130 = 26
, TIMER_OUTCFG31_OUTCFG126_TIMER131 = 27
,
TIMER_OUTCFG31_OUTCFG126_TIMER140 = 28
, TIMER_OUTCFG31_OUTCFG126_TIMER141 = 29
, TIMER_OUTCFG31_OUTCFG126_TIMER150 = 30
, TIMER_OUTCFG31_OUTCFG126_TIMER151 = 31
,
TIMER_OUTCFG31_OUTCFG126_STIMER0 = 32
, TIMER_OUTCFG31_OUTCFG126_STIMER1 = 33
, TIMER_OUTCFG31_OUTCFG126_STIMER2 = 34
, TIMER_OUTCFG31_OUTCFG126_STIMER3 = 35
,
TIMER_OUTCFG31_OUTCFG126_STIMER4 = 36
, TIMER_OUTCFG31_OUTCFG126_STIMER5 = 37
, TIMER_OUTCFG31_OUTCFG126_STIMER6 = 38
, TIMER_OUTCFG31_OUTCFG126_STIMER7 = 39
,
TIMER_OUTCFG31_OUTCFG126_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG31_OUTCFG125_Enum {
TIMER_OUTCFG31_OUTCFG125_TIMER00 = 0
, TIMER_OUTCFG31_OUTCFG125_TIMER01 = 1
, TIMER_OUTCFG31_OUTCFG125_TIMER10 = 2
, TIMER_OUTCFG31_OUTCFG125_TIMER11 = 3
,
TIMER_OUTCFG31_OUTCFG125_TIMER20 = 4
, TIMER_OUTCFG31_OUTCFG125_TIMER21 = 5
, TIMER_OUTCFG31_OUTCFG125_TIMER30 = 6
, TIMER_OUTCFG31_OUTCFG125_TIMER31 = 7
,
TIMER_OUTCFG31_OUTCFG125_TIMER40 = 8
, TIMER_OUTCFG31_OUTCFG125_TIMER41 = 9
, TIMER_OUTCFG31_OUTCFG125_TIMER50 = 10
, TIMER_OUTCFG31_OUTCFG125_TIMER51 = 11
,
TIMER_OUTCFG31_OUTCFG125_TIMER60 = 12
, TIMER_OUTCFG31_OUTCFG125_TIMER61 = 13
, TIMER_OUTCFG31_OUTCFG125_TIMER70 = 14
, TIMER_OUTCFG31_OUTCFG125_TIMER71 = 15
,
TIMER_OUTCFG31_OUTCFG125_TIMER80 = 16
, TIMER_OUTCFG31_OUTCFG125_TIMER81 = 17
, TIMER_OUTCFG31_OUTCFG125_TIMER90 = 18
, TIMER_OUTCFG31_OUTCFG125_TIMER91 = 19
,
TIMER_OUTCFG31_OUTCFG125_TIMER100 = 20
, TIMER_OUTCFG31_OUTCFG125_TIMER101 = 21
, TIMER_OUTCFG31_OUTCFG125_TIMER110 = 22
, TIMER_OUTCFG31_OUTCFG125_TIMER111 = 23
,
TIMER_OUTCFG31_OUTCFG125_TIMER120 = 24
, TIMER_OUTCFG31_OUTCFG125_TIMER121 = 25
, TIMER_OUTCFG31_OUTCFG125_TIMER130 = 26
, TIMER_OUTCFG31_OUTCFG125_TIMER131 = 27
,
TIMER_OUTCFG31_OUTCFG125_TIMER140 = 28
, TIMER_OUTCFG31_OUTCFG125_TIMER141 = 29
, TIMER_OUTCFG31_OUTCFG125_TIMER150 = 30
, TIMER_OUTCFG31_OUTCFG125_TIMER151 = 31
,
TIMER_OUTCFG31_OUTCFG125_STIMER0 = 32
, TIMER_OUTCFG31_OUTCFG125_STIMER1 = 33
, TIMER_OUTCFG31_OUTCFG125_STIMER2 = 34
, TIMER_OUTCFG31_OUTCFG125_STIMER3 = 35
,
TIMER_OUTCFG31_OUTCFG125_STIMER4 = 36
, TIMER_OUTCFG31_OUTCFG125_STIMER5 = 37
, TIMER_OUTCFG31_OUTCFG125_STIMER6 = 38
, TIMER_OUTCFG31_OUTCFG125_STIMER7 = 39
,
TIMER_OUTCFG31_OUTCFG125_DISABLED = 63
} |
| |
| enum | TIMER_OUTCFG31_OUTCFG124_Enum {
TIMER_OUTCFG31_OUTCFG124_TIMER00 = 0
, TIMER_OUTCFG31_OUTCFG124_TIMER01 = 1
, TIMER_OUTCFG31_OUTCFG124_TIMER10 = 2
, TIMER_OUTCFG31_OUTCFG124_TIMER11 = 3
,
TIMER_OUTCFG31_OUTCFG124_TIMER20 = 4
, TIMER_OUTCFG31_OUTCFG124_TIMER21 = 5
, TIMER_OUTCFG31_OUTCFG124_TIMER30 = 6
, TIMER_OUTCFG31_OUTCFG124_TIMER31 = 7
,
TIMER_OUTCFG31_OUTCFG124_TIMER40 = 8
, TIMER_OUTCFG31_OUTCFG124_TIMER41 = 9
, TIMER_OUTCFG31_OUTCFG124_TIMER50 = 10
, TIMER_OUTCFG31_OUTCFG124_TIMER51 = 11
,
TIMER_OUTCFG31_OUTCFG124_TIMER60 = 12
, TIMER_OUTCFG31_OUTCFG124_TIMER61 = 13
, TIMER_OUTCFG31_OUTCFG124_TIMER70 = 14
, TIMER_OUTCFG31_OUTCFG124_TIMER71 = 15
,
TIMER_OUTCFG31_OUTCFG124_TIMER80 = 16
, TIMER_OUTCFG31_OUTCFG124_TIMER81 = 17
, TIMER_OUTCFG31_OUTCFG124_TIMER90 = 18
, TIMER_OUTCFG31_OUTCFG124_TIMER91 = 19
,
TIMER_OUTCFG31_OUTCFG124_TIMER100 = 20
, TIMER_OUTCFG31_OUTCFG124_TIMER101 = 21
, TIMER_OUTCFG31_OUTCFG124_TIMER110 = 22
, TIMER_OUTCFG31_OUTCFG124_TIMER111 = 23
,
TIMER_OUTCFG31_OUTCFG124_TIMER120 = 24
, TIMER_OUTCFG31_OUTCFG124_TIMER121 = 25
, TIMER_OUTCFG31_OUTCFG124_TIMER130 = 26
, TIMER_OUTCFG31_OUTCFG124_TIMER131 = 27
,
TIMER_OUTCFG31_OUTCFG124_TIMER140 = 28
, TIMER_OUTCFG31_OUTCFG124_TIMER141 = 29
, TIMER_OUTCFG31_OUTCFG124_TIMER150 = 30
, TIMER_OUTCFG31_OUTCFG124_TIMER151 = 31
,
TIMER_OUTCFG31_OUTCFG124_STIMER0 = 32
, TIMER_OUTCFG31_OUTCFG124_STIMER1 = 33
, TIMER_OUTCFG31_OUTCFG124_STIMER2 = 34
, TIMER_OUTCFG31_OUTCFG124_STIMER3 = 35
,
TIMER_OUTCFG31_OUTCFG124_STIMER4 = 36
, TIMER_OUTCFG31_OUTCFG124_STIMER5 = 37
, TIMER_OUTCFG31_OUTCFG124_STIMER6 = 38
, TIMER_OUTCFG31_OUTCFG124_STIMER7 = 39
,
TIMER_OUTCFG31_OUTCFG124_DISABLED = 63
} |
| |
| enum | TIMER_CTRL0_TMR0TMODE_Enum { TIMER_CTRL0_TMR0TMODE_DIS = 0
, TIMER_CTRL0_TMR0TMODE_RISE = 1
, TIMER_CTRL0_TMR0TMODE_FALL = 2
, TIMER_CTRL0_TMR0TMODE_BOTH = 3
} |
| |
| enum | TIMER_CTRL0_TMR0CLK_Enum {
TIMER_CTRL0_TMR0CLK_HFRC_DIV4 = 0
, TIMER_CTRL0_TMR0CLK_HFRC_DIV16 = 1
, TIMER_CTRL0_TMR0CLK_HFRC_DIV64 = 2
, TIMER_CTRL0_TMR0CLK_HFRC_DIV256 = 3
,
TIMER_CTRL0_TMR0CLK_HFRC_DIV1024 = 4
, TIMER_CTRL0_TMR0CLK_HFRC_DIV4K = 5
, TIMER_CTRL0_TMR0CLK_LFRC = 6
, TIMER_CTRL0_TMR0CLK_LFRC_DIV2 = 7
,
TIMER_CTRL0_TMR0CLK_LFRC_DIV32 = 8
, TIMER_CTRL0_TMR0CLK_LFRC_DIV1K = 9
, TIMER_CTRL0_TMR0CLK_XT = 10
, TIMER_CTRL0_TMR0CLK_XT_DIV2 = 11
,
TIMER_CTRL0_TMR0CLK_XT_DIV4 = 12
, TIMER_CTRL0_TMR0CLK_XT_DIV8 = 13
, TIMER_CTRL0_TMR0CLK_XT_DIV16 = 14
, TIMER_CTRL0_TMR0CLK_XT_DIV32 = 15
,
TIMER_CTRL0_TMR0CLK_XT_DIV128 = 16
, TIMER_CTRL0_TMR0CLK_RTC_100HZ = 17
, TIMER_CTRL0_TMR0CLK_BUCKC = 28
, TIMER_CTRL0_TMR0CLK_BUCKF = 29
,
TIMER_CTRL0_TMR0CLK_BUCKS = 30
, TIMER_CTRL0_TMR0CLK_BUCKC_LV = 31
, TIMER_CTRL0_TMR0CLK_TMR00 = 32
, TIMER_CTRL0_TMR0CLK_TMR01 = 33
,
TIMER_CTRL0_TMR0CLK_TMR10 = 34
, TIMER_CTRL0_TMR0CLK_TMR11 = 35
, TIMER_CTRL0_TMR0CLK_TMR20 = 36
, TIMER_CTRL0_TMR0CLK_TMR21 = 37
,
TIMER_CTRL0_TMR0CLK_TMR30 = 38
, TIMER_CTRL0_TMR0CLK_TMR31 = 39
, TIMER_CTRL0_TMR0CLK_TMR40 = 40
, TIMER_CTRL0_TMR0CLK_TMR41 = 41
,
TIMER_CTRL0_TMR0CLK_TMR50 = 42
, TIMER_CTRL0_TMR0CLK_TMR51 = 43
, TIMER_CTRL0_TMR0CLK_TMR60 = 44
, TIMER_CTRL0_TMR0CLK_TMR61 = 45
,
TIMER_CTRL0_TMR0CLK_TMR70 = 46
, TIMER_CTRL0_TMR0CLK_TMR71 = 47
, TIMER_CTRL0_TMR0CLK_TMR80 = 48
, TIMER_CTRL0_TMR0CLK_TMR81 = 49
,
TIMER_CTRL0_TMR0CLK_TMR90 = 50
, TIMER_CTRL0_TMR0CLK_TMR91 = 51
, TIMER_CTRL0_TMR0CLK_TMR100 = 52
, TIMER_CTRL0_TMR0CLK_TMR101 = 53
,
TIMER_CTRL0_TMR0CLK_TMR110 = 54
, TIMER_CTRL0_TMR0CLK_TMR111 = 55
, TIMER_CTRL0_TMR0CLK_TMR120 = 56
, TIMER_CTRL0_TMR0CLK_TMR121 = 57
,
TIMER_CTRL0_TMR0CLK_TMR130 = 58
, TIMER_CTRL0_TMR0CLK_TMR131 = 59
, TIMER_CTRL0_TMR0CLK_TMR140 = 60
, TIMER_CTRL0_TMR0CLK_TMR141 = 61
,
TIMER_CTRL0_TMR0CLK_TMR150 = 62
, TIMER_CTRL0_TMR0CLK_TMR151 = 63
, TIMER_CTRL0_TMR0CLK_GPIO0 = 128
, TIMER_CTRL0_TMR0CLK_GPIO63 = 191
,
TIMER_CTRL0_TMR0CLK_GPIO95 = 223
, TIMER_CTRL0_TMR0CLK_GPIO127 = 255
} |
| |
| enum | TIMER_CTRL0_TMR0FN_Enum {
TIMER_CTRL0_TMR0FN_EDGE = 1
, TIMER_CTRL0_TMR0FN_UPCOUNT = 2
, TIMER_CTRL0_TMR0FN_PWM = 4
, TIMER_CTRL0_TMR0FN_SINGLEPATTERN = 12
,
TIMER_CTRL0_TMR0FN_REPEATPATTERN = 13
} |
| |
| enum | TIMER_CTRL0_TMR0POL1_Enum { TIMER_CTRL0_TMR0POL1_NORMAL = 0
, TIMER_CTRL0_TMR0POL1_INVERTED = 1
} |
| |
| enum | TIMER_CTRL0_TMR0POL0_Enum { TIMER_CTRL0_TMR0POL0_NORMAL = 0
, TIMER_CTRL0_TMR0POL0_INVERTED = 1
} |
| |
| enum | TIMER_CTRL0_TMR0CLR_Enum { TIMER_CTRL0_TMR0CLR_CLEAR = 1
, TIMER_CTRL0_TMR0CLR_DEFAULT = 0
} |
| |
| enum | TIMER_CTRL0_TMR0EN_Enum { TIMER_CTRL0_TMR0EN_DIS = 0
, TIMER_CTRL0_TMR0EN_EN = 1
} |
| |
| enum | TIMER_MODE0_TMR0TRIGSEL_Enum {
TIMER_MODE0_TMR0TRIGSEL_TMR00 = 0
, TIMER_MODE0_TMR0TRIGSEL_TMR01 = 1
, TIMER_MODE0_TMR0TRIGSEL_TMR10 = 2
, TIMER_MODE0_TMR0TRIGSEL_TMR11 = 3
,
TIMER_MODE0_TMR0TRIGSEL_TMR20 = 4
, TIMER_MODE0_TMR0TRIGSEL_TMR21 = 5
, TIMER_MODE0_TMR0TRIGSEL_TMR30 = 6
, TIMER_MODE0_TMR0TRIGSEL_TMR31 = 7
,
TIMER_MODE0_TMR0TRIGSEL_TMR40 = 8
, TIMER_MODE0_TMR0TRIGSEL_TMR41 = 9
, TIMER_MODE0_TMR0TRIGSEL_TMR50 = 10
, TIMER_MODE0_TMR0TRIGSEL_TMR51 = 11
,
TIMER_MODE0_TMR0TRIGSEL_TMR60 = 12
, TIMER_MODE0_TMR0TRIGSEL_TMR61 = 13
, TIMER_MODE0_TMR0TRIGSEL_TMR70 = 14
, TIMER_MODE0_TMR0TRIGSEL_TMR71 = 15
,
TIMER_MODE0_TMR0TRIGSEL_TMR80 = 16
, TIMER_MODE0_TMR0TRIGSEL_TMR81 = 17
, TIMER_MODE0_TMR0TRIGSEL_TMR90 = 18
, TIMER_MODE0_TMR0TRIGSEL_TMR91 = 19
,
TIMER_MODE0_TMR0TRIGSEL_TMR100 = 20
, TIMER_MODE0_TMR0TRIGSEL_TMR101 = 21
, TIMER_MODE0_TMR0TRIGSEL_TMR110 = 22
, TIMER_MODE0_TMR0TRIGSEL_TMR111 = 23
,
TIMER_MODE0_TMR0TRIGSEL_TMR120 = 24
, TIMER_MODE0_TMR0TRIGSEL_TMR121 = 25
, TIMER_MODE0_TMR0TRIGSEL_TMR130 = 26
, TIMER_MODE0_TMR0TRIGSEL_TMR131 = 27
,
TIMER_MODE0_TMR0TRIGSEL_TMR140 = 28
, TIMER_MODE0_TMR0TRIGSEL_TMR141 = 29
, TIMER_MODE0_TMR0TRIGSEL_TMR150 = 30
, TIMER_MODE0_TMR0TRIGSEL_TMR151 = 31
,
TIMER_MODE0_TMR0TRIGSEL_GPIO0 = 128
, TIMER_MODE0_TMR0TRIGSEL_GPIO127 = 255
} |
| |
| enum | TIMER_CTRL1_TMR1TMODE_Enum { TIMER_CTRL1_TMR1TMODE_DIS = 0
, TIMER_CTRL1_TMR1TMODE_RISE = 1
, TIMER_CTRL1_TMR1TMODE_FALL = 2
, TIMER_CTRL1_TMR1TMODE_BOTH = 3
} |
| |
| enum | TIMER_CTRL1_TMR1CLK_Enum {
TIMER_CTRL1_TMR1CLK_HFRC_DIV4 = 0
, TIMER_CTRL1_TMR1CLK_HFRC_DIV16 = 1
, TIMER_CTRL1_TMR1CLK_HFRC_DIV64 = 2
, TIMER_CTRL1_TMR1CLK_HFRC_DIV256 = 3
,
TIMER_CTRL1_TMR1CLK_HFRC_DIV1024 = 4
, TIMER_CTRL1_TMR1CLK_HFRC_DIV4K = 5
, TIMER_CTRL1_TMR1CLK_LFRC = 6
, TIMER_CTRL1_TMR1CLK_LFRC_DIV2 = 7
,
TIMER_CTRL1_TMR1CLK_LFRC_DIV32 = 8
, TIMER_CTRL1_TMR1CLK_LFRC_DIV1K = 9
, TIMER_CTRL1_TMR1CLK_XT = 10
, TIMER_CTRL1_TMR1CLK_XT_DIV2 = 11
,
TIMER_CTRL1_TMR1CLK_XT_DIV4 = 12
, TIMER_CTRL1_TMR1CLK_XT_DIV8 = 13
, TIMER_CTRL1_TMR1CLK_XT_DIV16 = 14
, TIMER_CTRL1_TMR1CLK_XT_DIV32 = 15
,
TIMER_CTRL1_TMR1CLK_XT_DIV128 = 16
, TIMER_CTRL1_TMR1CLK_RTC_100HZ = 17
, TIMER_CTRL1_TMR1CLK_BUCKC = 28
, TIMER_CTRL1_TMR1CLK_BUCKF = 29
,
TIMER_CTRL1_TMR1CLK_BUCKS = 30
, TIMER_CTRL1_TMR1CLK_BUCKC_LV = 31
, TIMER_CTRL1_TMR1CLK_TMR00 = 32
, TIMER_CTRL1_TMR1CLK_TMR01 = 33
,
TIMER_CTRL1_TMR1CLK_TMR10 = 34
, TIMER_CTRL1_TMR1CLK_TMR11 = 35
, TIMER_CTRL1_TMR1CLK_TMR20 = 36
, TIMER_CTRL1_TMR1CLK_TMR21 = 37
,
TIMER_CTRL1_TMR1CLK_TMR30 = 38
, TIMER_CTRL1_TMR1CLK_TMR31 = 39
, TIMER_CTRL1_TMR1CLK_TMR40 = 40
, TIMER_CTRL1_TMR1CLK_TMR41 = 41
,
TIMER_CTRL1_TMR1CLK_TMR50 = 42
, TIMER_CTRL1_TMR1CLK_TMR51 = 43
, TIMER_CTRL1_TMR1CLK_TMR60 = 44
, TIMER_CTRL1_TMR1CLK_TMR61 = 45
,
TIMER_CTRL1_TMR1CLK_TMR70 = 46
, TIMER_CTRL1_TMR1CLK_TMR71 = 47
, TIMER_CTRL1_TMR1CLK_TMR80 = 48
, TIMER_CTRL1_TMR1CLK_TMR81 = 49
,
TIMER_CTRL1_TMR1CLK_TMR90 = 50
, TIMER_CTRL1_TMR1CLK_TMR91 = 51
, TIMER_CTRL1_TMR1CLK_TMR100 = 52
, TIMER_CTRL1_TMR1CLK_TMR101 = 53
,
TIMER_CTRL1_TMR1CLK_TMR110 = 54
, TIMER_CTRL1_TMR1CLK_TMR111 = 55
, TIMER_CTRL1_TMR1CLK_TMR120 = 56
, TIMER_CTRL1_TMR1CLK_TMR121 = 57
,
TIMER_CTRL1_TMR1CLK_TMR130 = 58
, TIMER_CTRL1_TMR1CLK_TMR131 = 59
, TIMER_CTRL1_TMR1CLK_TMR140 = 60
, TIMER_CTRL1_TMR1CLK_TMR141 = 61
,
TIMER_CTRL1_TMR1CLK_TMR150 = 62
, TIMER_CTRL1_TMR1CLK_TMR151 = 63
, TIMER_CTRL1_TMR1CLK_GPIO0 = 128
, TIMER_CTRL1_TMR1CLK_GPIO63 = 191
,
TIMER_CTRL1_TMR1CLK_GPIO95 = 223
, TIMER_CTRL1_TMR1CLK_GPIO127 = 255
} |
| |
| enum | TIMER_CTRL1_TMR1FN_Enum {
TIMER_CTRL1_TMR1FN_EDGE = 1
, TIMER_CTRL1_TMR1FN_UPCOUNT = 2
, TIMER_CTRL1_TMR1FN_PWM = 4
, TIMER_CTRL1_TMR1FN_SINGLEPATTERN = 12
,
TIMER_CTRL1_TMR1FN_REPEATPATTERN = 13
} |
| |
| enum | TIMER_CTRL1_TMR1POL1_Enum { TIMER_CTRL1_TMR1POL1_NORMAL = 0
, TIMER_CTRL1_TMR1POL1_INVERTED = 1
} |
| |
| enum | TIMER_CTRL1_TMR1POL0_Enum { TIMER_CTRL1_TMR1POL0_NORMAL = 0
, TIMER_CTRL1_TMR1POL0_INVERTED = 1
} |
| |
| enum | TIMER_CTRL1_TMR1CLR_Enum { TIMER_CTRL1_TMR1CLR_CLEAR = 1
, TIMER_CTRL1_TMR1CLR_DEFAULT = 0
} |
| |
| enum | TIMER_CTRL1_TMR1EN_Enum { TIMER_CTRL1_TMR1EN_DIS = 0
, TIMER_CTRL1_TMR1EN_EN = 1
} |
| |
| enum | TIMER_MODE1_TMR1TRIGSEL_Enum {
TIMER_MODE1_TMR1TRIGSEL_TMR00 = 0
, TIMER_MODE1_TMR1TRIGSEL_TMR01 = 1
, TIMER_MODE1_TMR1TRIGSEL_TMR10 = 2
, TIMER_MODE1_TMR1TRIGSEL_TMR11 = 3
,
TIMER_MODE1_TMR1TRIGSEL_TMR20 = 4
, TIMER_MODE1_TMR1TRIGSEL_TMR21 = 5
, TIMER_MODE1_TMR1TRIGSEL_TMR30 = 6
, TIMER_MODE1_TMR1TRIGSEL_TMR31 = 7
,
TIMER_MODE1_TMR1TRIGSEL_TMR40 = 8
, TIMER_MODE1_TMR1TRIGSEL_TMR41 = 9
, TIMER_MODE1_TMR1TRIGSEL_TMR50 = 10
, TIMER_MODE1_TMR1TRIGSEL_TMR51 = 11
,
TIMER_MODE1_TMR1TRIGSEL_TMR60 = 12
, TIMER_MODE1_TMR1TRIGSEL_TMR61 = 13
, TIMER_MODE1_TMR1TRIGSEL_TMR70 = 14
, TIMER_MODE1_TMR1TRIGSEL_TMR71 = 15
,
TIMER_MODE1_TMR1TRIGSEL_TMR80 = 16
, TIMER_MODE1_TMR1TRIGSEL_TMR81 = 17
, TIMER_MODE1_TMR1TRIGSEL_TMR90 = 18
, TIMER_MODE1_TMR1TRIGSEL_TMR91 = 19
,
TIMER_MODE1_TMR1TRIGSEL_TMR100 = 20
, TIMER_MODE1_TMR1TRIGSEL_TMR101 = 21
, TIMER_MODE1_TMR1TRIGSEL_TMR110 = 22
, TIMER_MODE1_TMR1TRIGSEL_TMR111 = 23
,
TIMER_MODE1_TMR1TRIGSEL_TMR120 = 24
, TIMER_MODE1_TMR1TRIGSEL_TMR121 = 25
, TIMER_MODE1_TMR1TRIGSEL_TMR130 = 26
, TIMER_MODE1_TMR1TRIGSEL_TMR131 = 27
,
TIMER_MODE1_TMR1TRIGSEL_TMR140 = 28
, TIMER_MODE1_TMR1TRIGSEL_TMR141 = 29
, TIMER_MODE1_TMR1TRIGSEL_TMR150 = 30
, TIMER_MODE1_TMR1TRIGSEL_TMR151 = 31
,
TIMER_MODE1_TMR1TRIGSEL_GPIO0 = 128
, TIMER_MODE1_TMR1TRIGSEL_GPIO127 = 255
} |
| |
| enum | TIMER_CTRL2_TMR2TMODE_Enum { TIMER_CTRL2_TMR2TMODE_DIS = 0
, TIMER_CTRL2_TMR2TMODE_RISE = 1
, TIMER_CTRL2_TMR2TMODE_FALL = 2
, TIMER_CTRL2_TMR2TMODE_BOTH = 3
} |
| |
| enum | TIMER_CTRL2_TMR2CLK_Enum {
TIMER_CTRL2_TMR2CLK_HFRC_DIV4 = 0
, TIMER_CTRL2_TMR2CLK_HFRC_DIV16 = 1
, TIMER_CTRL2_TMR2CLK_HFRC_DIV64 = 2
, TIMER_CTRL2_TMR2CLK_HFRC_DIV256 = 3
,
TIMER_CTRL2_TMR2CLK_HFRC_DIV1024 = 4
, TIMER_CTRL2_TMR2CLK_HFRC_DIV4K = 5
, TIMER_CTRL2_TMR2CLK_LFRC = 6
, TIMER_CTRL2_TMR2CLK_LFRC_DIV2 = 7
,
TIMER_CTRL2_TMR2CLK_LFRC_DIV32 = 8
, TIMER_CTRL2_TMR2CLK_LFRC_DIV1K = 9
, TIMER_CTRL2_TMR2CLK_XT = 10
, TIMER_CTRL2_TMR2CLK_XT_DIV2 = 11
,
TIMER_CTRL2_TMR2CLK_XT_DIV4 = 12
, TIMER_CTRL2_TMR2CLK_XT_DIV8 = 13
, TIMER_CTRL2_TMR2CLK_XT_DIV16 = 14
, TIMER_CTRL2_TMR2CLK_XT_DIV32 = 15
,
TIMER_CTRL2_TMR2CLK_XT_DIV128 = 16
, TIMER_CTRL2_TMR2CLK_RTC_100HZ = 17
, TIMER_CTRL2_TMR2CLK_BUCKC = 28
, TIMER_CTRL2_TMR2CLK_BUCKF = 29
,
TIMER_CTRL2_TMR2CLK_BUCKS = 30
, TIMER_CTRL2_TMR2CLK_BUCKC_LV = 31
, TIMER_CTRL2_TMR2CLK_TMR00 = 32
, TIMER_CTRL2_TMR2CLK_TMR01 = 33
,
TIMER_CTRL2_TMR2CLK_TMR10 = 34
, TIMER_CTRL2_TMR2CLK_TMR11 = 35
, TIMER_CTRL2_TMR2CLK_TMR20 = 36
, TIMER_CTRL2_TMR2CLK_TMR21 = 37
,
TIMER_CTRL2_TMR2CLK_TMR30 = 38
, TIMER_CTRL2_TMR2CLK_TMR31 = 39
, TIMER_CTRL2_TMR2CLK_TMR40 = 40
, TIMER_CTRL2_TMR2CLK_TMR41 = 41
,
TIMER_CTRL2_TMR2CLK_TMR50 = 42
, TIMER_CTRL2_TMR2CLK_TMR51 = 43
, TIMER_CTRL2_TMR2CLK_TMR60 = 44
, TIMER_CTRL2_TMR2CLK_TMR61 = 45
,
TIMER_CTRL2_TMR2CLK_TMR70 = 46
, TIMER_CTRL2_TMR2CLK_TMR71 = 47
, TIMER_CTRL2_TMR2CLK_TMR80 = 48
, TIMER_CTRL2_TMR2CLK_TMR81 = 49
,
TIMER_CTRL2_TMR2CLK_TMR90 = 50
, TIMER_CTRL2_TMR2CLK_TMR91 = 51
, TIMER_CTRL2_TMR2CLK_TMR100 = 52
, TIMER_CTRL2_TMR2CLK_TMR101 = 53
,
TIMER_CTRL2_TMR2CLK_TMR110 = 54
, TIMER_CTRL2_TMR2CLK_TMR111 = 55
, TIMER_CTRL2_TMR2CLK_TMR120 = 56
, TIMER_CTRL2_TMR2CLK_TMR121 = 57
,
TIMER_CTRL2_TMR2CLK_TMR130 = 58
, TIMER_CTRL2_TMR2CLK_TMR131 = 59
, TIMER_CTRL2_TMR2CLK_TMR140 = 60
, TIMER_CTRL2_TMR2CLK_TMR141 = 61
,
TIMER_CTRL2_TMR2CLK_TMR150 = 62
, TIMER_CTRL2_TMR2CLK_TMR151 = 63
, TIMER_CTRL2_TMR2CLK_GPIO0 = 128
, TIMER_CTRL2_TMR2CLK_GPIO63 = 191
,
TIMER_CTRL2_TMR2CLK_GPIO95 = 223
, TIMER_CTRL2_TMR2CLK_GPIO127 = 255
} |
| |
| enum | TIMER_CTRL2_TMR2FN_Enum {
TIMER_CTRL2_TMR2FN_EDGE = 1
, TIMER_CTRL2_TMR2FN_UPCOUNT = 2
, TIMER_CTRL2_TMR2FN_PWM = 4
, TIMER_CTRL2_TMR2FN_SINGLEPATTERN = 12
,
TIMER_CTRL2_TMR2FN_REPEATPATTERN = 13
} |
| |
| enum | TIMER_CTRL2_TMR2POL1_Enum { TIMER_CTRL2_TMR2POL1_NORMAL = 0
, TIMER_CTRL2_TMR2POL1_INVERTED = 1
} |
| |
| enum | TIMER_CTRL2_TMR2POL0_Enum { TIMER_CTRL2_TMR2POL0_NORMAL = 0
, TIMER_CTRL2_TMR2POL0_INVERTED = 1
} |
| |
| enum | TIMER_CTRL2_TMR2CLR_Enum { TIMER_CTRL2_TMR2CLR_CLEAR = 1
, TIMER_CTRL2_TMR2CLR_DEFAULT = 0
} |
| |
| enum | TIMER_CTRL2_TMR2EN_Enum { TIMER_CTRL2_TMR2EN_DIS = 0
, TIMER_CTRL2_TMR2EN_EN = 1
} |
| |
| enum | TIMER_MODE2_TMR2TRIGSEL_Enum {
TIMER_MODE2_TMR2TRIGSEL_TMR00 = 0
, TIMER_MODE2_TMR2TRIGSEL_TMR01 = 1
, TIMER_MODE2_TMR2TRIGSEL_TMR10 = 2
, TIMER_MODE2_TMR2TRIGSEL_TMR11 = 3
,
TIMER_MODE2_TMR2TRIGSEL_TMR20 = 4
, TIMER_MODE2_TMR2TRIGSEL_TMR21 = 5
, TIMER_MODE2_TMR2TRIGSEL_TMR30 = 6
, TIMER_MODE2_TMR2TRIGSEL_TMR31 = 7
,
TIMER_MODE2_TMR2TRIGSEL_TMR40 = 8
, TIMER_MODE2_TMR2TRIGSEL_TMR41 = 9
, TIMER_MODE2_TMR2TRIGSEL_TMR50 = 10
, TIMER_MODE2_TMR2TRIGSEL_TMR51 = 11
,
TIMER_MODE2_TMR2TRIGSEL_TMR60 = 12
, TIMER_MODE2_TMR2TRIGSEL_TMR61 = 13
, TIMER_MODE2_TMR2TRIGSEL_TMR70 = 14
, TIMER_MODE2_TMR2TRIGSEL_TMR71 = 15
,
TIMER_MODE2_TMR2TRIGSEL_TMR80 = 16
, TIMER_MODE2_TMR2TRIGSEL_TMR81 = 17
, TIMER_MODE2_TMR2TRIGSEL_TMR90 = 18
, TIMER_MODE2_TMR2TRIGSEL_TMR91 = 19
,
TIMER_MODE2_TMR2TRIGSEL_TMR100 = 20
, TIMER_MODE2_TMR2TRIGSEL_TMR101 = 21
, TIMER_MODE2_TMR2TRIGSEL_TMR110 = 22
, TIMER_MODE2_TMR2TRIGSEL_TMR111 = 23
,
TIMER_MODE2_TMR2TRIGSEL_TMR120 = 24
, TIMER_MODE2_TMR2TRIGSEL_TMR121 = 25
, TIMER_MODE2_TMR2TRIGSEL_TMR130 = 26
, TIMER_MODE2_TMR2TRIGSEL_TMR131 = 27
,
TIMER_MODE2_TMR2TRIGSEL_TMR140 = 28
, TIMER_MODE2_TMR2TRIGSEL_TMR141 = 29
, TIMER_MODE2_TMR2TRIGSEL_TMR150 = 30
, TIMER_MODE2_TMR2TRIGSEL_TMR151 = 31
,
TIMER_MODE2_TMR2TRIGSEL_GPIO0 = 128
, TIMER_MODE2_TMR2TRIGSEL_GPIO127 = 255
} |
| |
| enum | TIMER_CTRL3_TMR3TMODE_Enum { TIMER_CTRL3_TMR3TMODE_DIS = 0
, TIMER_CTRL3_TMR3TMODE_RISE = 1
, TIMER_CTRL3_TMR3TMODE_FALL = 2
, TIMER_CTRL3_TMR3TMODE_BOTH = 3
} |
| |
| enum | TIMER_CTRL3_TMR3CLK_Enum {
TIMER_CTRL3_TMR3CLK_HFRC_DIV4 = 0
, TIMER_CTRL3_TMR3CLK_HFRC_DIV16 = 1
, TIMER_CTRL3_TMR3CLK_HFRC_DIV64 = 2
, TIMER_CTRL3_TMR3CLK_HFRC_DIV256 = 3
,
TIMER_CTRL3_TMR3CLK_HFRC_DIV1024 = 4
, TIMER_CTRL3_TMR3CLK_HFRC_DIV4K = 5
, TIMER_CTRL3_TMR3CLK_LFRC = 6
, TIMER_CTRL3_TMR3CLK_LFRC_DIV2 = 7
,
TIMER_CTRL3_TMR3CLK_LFRC_DIV32 = 8
, TIMER_CTRL3_TMR3CLK_LFRC_DIV1K = 9
, TIMER_CTRL3_TMR3CLK_XT = 10
, TIMER_CTRL3_TMR3CLK_XT_DIV2 = 11
,
TIMER_CTRL3_TMR3CLK_XT_DIV4 = 12
, TIMER_CTRL3_TMR3CLK_XT_DIV8 = 13
, TIMER_CTRL3_TMR3CLK_XT_DIV16 = 14
, TIMER_CTRL3_TMR3CLK_XT_DIV32 = 15
,
TIMER_CTRL3_TMR3CLK_XT_DIV128 = 16
, TIMER_CTRL3_TMR3CLK_RTC_100HZ = 17
, TIMER_CTRL3_TMR3CLK_BUCKC = 28
, TIMER_CTRL3_TMR3CLK_BUCKF = 29
,
TIMER_CTRL3_TMR3CLK_BUCKS = 30
, TIMER_CTRL3_TMR3CLK_BUCKC_LV = 31
, TIMER_CTRL3_TMR3CLK_TMR00 = 32
, TIMER_CTRL3_TMR3CLK_TMR01 = 33
,
TIMER_CTRL3_TMR3CLK_TMR10 = 34
, TIMER_CTRL3_TMR3CLK_TMR11 = 35
, TIMER_CTRL3_TMR3CLK_TMR20 = 36
, TIMER_CTRL3_TMR3CLK_TMR21 = 37
,
TIMER_CTRL3_TMR3CLK_TMR30 = 38
, TIMER_CTRL3_TMR3CLK_TMR31 = 39
, TIMER_CTRL3_TMR3CLK_TMR40 = 40
, TIMER_CTRL3_TMR3CLK_TMR41 = 41
,
TIMER_CTRL3_TMR3CLK_TMR50 = 42
, TIMER_CTRL3_TMR3CLK_TMR51 = 43
, TIMER_CTRL3_TMR3CLK_TMR60 = 44
, TIMER_CTRL3_TMR3CLK_TMR61 = 45
,
TIMER_CTRL3_TMR3CLK_TMR70 = 46
, TIMER_CTRL3_TMR3CLK_TMR71 = 47
, TIMER_CTRL3_TMR3CLK_TMR80 = 48
, TIMER_CTRL3_TMR3CLK_TMR81 = 49
,
TIMER_CTRL3_TMR3CLK_TMR90 = 50
, TIMER_CTRL3_TMR3CLK_TMR91 = 51
, TIMER_CTRL3_TMR3CLK_TMR100 = 52
, TIMER_CTRL3_TMR3CLK_TMR101 = 53
,
TIMER_CTRL3_TMR3CLK_TMR110 = 54
, TIMER_CTRL3_TMR3CLK_TMR111 = 55
, TIMER_CTRL3_TMR3CLK_TMR120 = 56
, TIMER_CTRL3_TMR3CLK_TMR121 = 57
,
TIMER_CTRL3_TMR3CLK_TMR130 = 58
, TIMER_CTRL3_TMR3CLK_TMR131 = 59
, TIMER_CTRL3_TMR3CLK_TMR140 = 60
, TIMER_CTRL3_TMR3CLK_TMR141 = 61
,
TIMER_CTRL3_TMR3CLK_TMR150 = 62
, TIMER_CTRL3_TMR3CLK_TMR151 = 63
, TIMER_CTRL3_TMR3CLK_GPIO0 = 128
, TIMER_CTRL3_TMR3CLK_GPIO63 = 191
,
TIMER_CTRL3_TMR3CLK_GPIO95 = 223
, TIMER_CTRL3_TMR3CLK_GPIO127 = 255
} |
| |
| enum | TIMER_CTRL3_TMR3FN_Enum {
TIMER_CTRL3_TMR3FN_EDGE = 1
, TIMER_CTRL3_TMR3FN_UPCOUNT = 2
, TIMER_CTRL3_TMR3FN_PWM = 4
, TIMER_CTRL3_TMR3FN_SINGLEPATTERN = 12
,
TIMER_CTRL3_TMR3FN_REPEATPATTERN = 13
} |
| |
| enum | TIMER_CTRL3_TMR3POL1_Enum { TIMER_CTRL3_TMR3POL1_NORMAL = 0
, TIMER_CTRL3_TMR3POL1_INVERTED = 1
} |
| |
| enum | TIMER_CTRL3_TMR3POL0_Enum { TIMER_CTRL3_TMR3POL0_NORMAL = 0
, TIMER_CTRL3_TMR3POL0_INVERTED = 1
} |
| |
| enum | TIMER_CTRL3_TMR3CLR_Enum { TIMER_CTRL3_TMR3CLR_CLEAR = 1
, TIMER_CTRL3_TMR3CLR_DEFAULT = 0
} |
| |
| enum | TIMER_CTRL3_TMR3EN_Enum { TIMER_CTRL3_TMR3EN_DIS = 0
, TIMER_CTRL3_TMR3EN_EN = 1
} |
| |
| enum | TIMER_MODE3_TMR3TRIGSEL_Enum {
TIMER_MODE3_TMR3TRIGSEL_TMR00 = 0
, TIMER_MODE3_TMR3TRIGSEL_TMR01 = 1
, TIMER_MODE3_TMR3TRIGSEL_TMR10 = 2
, TIMER_MODE3_TMR3TRIGSEL_TMR11 = 3
,
TIMER_MODE3_TMR3TRIGSEL_TMR20 = 4
, TIMER_MODE3_TMR3TRIGSEL_TMR21 = 5
, TIMER_MODE3_TMR3TRIGSEL_TMR30 = 6
, TIMER_MODE3_TMR3TRIGSEL_TMR31 = 7
,
TIMER_MODE3_TMR3TRIGSEL_TMR40 = 8
, TIMER_MODE3_TMR3TRIGSEL_TMR41 = 9
, TIMER_MODE3_TMR3TRIGSEL_TMR50 = 10
, TIMER_MODE3_TMR3TRIGSEL_TMR51 = 11
,
TIMER_MODE3_TMR3TRIGSEL_TMR60 = 12
, TIMER_MODE3_TMR3TRIGSEL_TMR61 = 13
, TIMER_MODE3_TMR3TRIGSEL_TMR70 = 14
, TIMER_MODE3_TMR3TRIGSEL_TMR71 = 15
,
TIMER_MODE3_TMR3TRIGSEL_TMR80 = 16
, TIMER_MODE3_TMR3TRIGSEL_TMR81 = 17
, TIMER_MODE3_TMR3TRIGSEL_TMR90 = 18
, TIMER_MODE3_TMR3TRIGSEL_TMR91 = 19
,
TIMER_MODE3_TMR3TRIGSEL_TMR100 = 20
, TIMER_MODE3_TMR3TRIGSEL_TMR101 = 21
, TIMER_MODE3_TMR3TRIGSEL_TMR110 = 22
, TIMER_MODE3_TMR3TRIGSEL_TMR111 = 23
,
TIMER_MODE3_TMR3TRIGSEL_TMR120 = 24
, TIMER_MODE3_TMR3TRIGSEL_TMR121 = 25
, TIMER_MODE3_TMR3TRIGSEL_TMR130 = 26
, TIMER_MODE3_TMR3TRIGSEL_TMR131 = 27
,
TIMER_MODE3_TMR3TRIGSEL_TMR140 = 28
, TIMER_MODE3_TMR3TRIGSEL_TMR141 = 29
, TIMER_MODE3_TMR3TRIGSEL_TMR150 = 30
, TIMER_MODE3_TMR3TRIGSEL_TMR151 = 31
,
TIMER_MODE3_TMR3TRIGSEL_GPIO0 = 128
, TIMER_MODE3_TMR3TRIGSEL_GPIO127 = 255
} |
| |
| enum | TIMER_CTRL4_TMR4TMODE_Enum { TIMER_CTRL4_TMR4TMODE_DIS = 0
, TIMER_CTRL4_TMR4TMODE_RISE = 1
, TIMER_CTRL4_TMR4TMODE_FALL = 2
, TIMER_CTRL4_TMR4TMODE_BOTH = 3
} |
| |
| enum | TIMER_CTRL4_TMR4CLK_Enum {
TIMER_CTRL4_TMR4CLK_HFRC_DIV4 = 0
, TIMER_CTRL4_TMR4CLK_HFRC_DIV16 = 1
, TIMER_CTRL4_TMR4CLK_HFRC_DIV64 = 2
, TIMER_CTRL4_TMR4CLK_HFRC_DIV256 = 3
,
TIMER_CTRL4_TMR4CLK_HFRC_DIV1024 = 4
, TIMER_CTRL4_TMR4CLK_HFRC_DIV4K = 5
, TIMER_CTRL4_TMR4CLK_LFRC = 6
, TIMER_CTRL4_TMR4CLK_LFRC_DIV2 = 7
,
TIMER_CTRL4_TMR4CLK_LFRC_DIV32 = 8
, TIMER_CTRL4_TMR4CLK_LFRC_DIV1K = 9
, TIMER_CTRL4_TMR4CLK_XT = 10
, TIMER_CTRL4_TMR4CLK_XT_DIV2 = 11
,
TIMER_CTRL4_TMR4CLK_XT_DIV4 = 12
, TIMER_CTRL4_TMR4CLK_XT_DIV8 = 13
, TIMER_CTRL4_TMR4CLK_XT_DIV16 = 14
, TIMER_CTRL4_TMR4CLK_XT_DIV32 = 15
,
TIMER_CTRL4_TMR4CLK_XT_DIV128 = 16
, TIMER_CTRL4_TMR4CLK_RTC_100HZ = 17
, TIMER_CTRL4_TMR4CLK_BUCKC = 28
, TIMER_CTRL4_TMR4CLK_BUCKF = 29
,
TIMER_CTRL4_TMR4CLK_BUCKS = 30
, TIMER_CTRL4_TMR4CLK_BUCKC_LV = 31
, TIMER_CTRL4_TMR4CLK_TMR00 = 32
, TIMER_CTRL4_TMR4CLK_TMR01 = 33
,
TIMER_CTRL4_TMR4CLK_TMR10 = 34
, TIMER_CTRL4_TMR4CLK_TMR11 = 35
, TIMER_CTRL4_TMR4CLK_TMR20 = 36
, TIMER_CTRL4_TMR4CLK_TMR21 = 37
,
TIMER_CTRL4_TMR4CLK_TMR30 = 38
, TIMER_CTRL4_TMR4CLK_TMR31 = 39
, TIMER_CTRL4_TMR4CLK_TMR40 = 40
, TIMER_CTRL4_TMR4CLK_TMR41 = 41
,
TIMER_CTRL4_TMR4CLK_TMR50 = 42
, TIMER_CTRL4_TMR4CLK_TMR51 = 43
, TIMER_CTRL4_TMR4CLK_TMR60 = 44
, TIMER_CTRL4_TMR4CLK_TMR61 = 45
,
TIMER_CTRL4_TMR4CLK_TMR70 = 46
, TIMER_CTRL4_TMR4CLK_TMR71 = 47
, TIMER_CTRL4_TMR4CLK_TMR80 = 48
, TIMER_CTRL4_TMR4CLK_TMR81 = 49
,
TIMER_CTRL4_TMR4CLK_TMR90 = 50
, TIMER_CTRL4_TMR4CLK_TMR91 = 51
, TIMER_CTRL4_TMR4CLK_TMR100 = 52
, TIMER_CTRL4_TMR4CLK_TMR101 = 53
,
TIMER_CTRL4_TMR4CLK_TMR110 = 54
, TIMER_CTRL4_TMR4CLK_TMR111 = 55
, TIMER_CTRL4_TMR4CLK_TMR120 = 56
, TIMER_CTRL4_TMR4CLK_TMR121 = 57
,
TIMER_CTRL4_TMR4CLK_TMR130 = 58
, TIMER_CTRL4_TMR4CLK_TMR131 = 59
, TIMER_CTRL4_TMR4CLK_TMR140 = 60
, TIMER_CTRL4_TMR4CLK_TMR141 = 61
,
TIMER_CTRL4_TMR4CLK_TMR150 = 62
, TIMER_CTRL4_TMR4CLK_TMR151 = 63
, TIMER_CTRL4_TMR4CLK_GPIO0 = 128
, TIMER_CTRL4_TMR4CLK_GPIO63 = 191
,
TIMER_CTRL4_TMR4CLK_GPIO95 = 223
, TIMER_CTRL4_TMR4CLK_GPIO127 = 255
} |
| |
| enum | TIMER_CTRL4_TMR4FN_Enum {
TIMER_CTRL4_TMR4FN_EDGE = 1
, TIMER_CTRL4_TMR4FN_UPCOUNT = 2
, TIMER_CTRL4_TMR4FN_PWM = 4
, TIMER_CTRL4_TMR4FN_SINGLEPATTERN = 12
,
TIMER_CTRL4_TMR4FN_REPEATPATTERN = 13
} |
| |
| enum | TIMER_CTRL4_TMR4POL1_Enum { TIMER_CTRL4_TMR4POL1_NORMAL = 0
, TIMER_CTRL4_TMR4POL1_INVERTED = 1
} |
| |
| enum | TIMER_CTRL4_TMR4POL0_Enum { TIMER_CTRL4_TMR4POL0_NORMAL = 0
, TIMER_CTRL4_TMR4POL0_INVERTED = 1
} |
| |
| enum | TIMER_CTRL4_TMR4CLR_Enum { TIMER_CTRL4_TMR4CLR_CLEAR = 1
, TIMER_CTRL4_TMR4CLR_DEFAULT = 0
} |
| |
| enum | TIMER_CTRL4_TMR4EN_Enum { TIMER_CTRL4_TMR4EN_DIS = 0
, TIMER_CTRL4_TMR4EN_EN = 1
} |
| |
| enum | TIMER_MODE4_TMR4TRIGSEL_Enum {
TIMER_MODE4_TMR4TRIGSEL_TMR00 = 0
, TIMER_MODE4_TMR4TRIGSEL_TMR01 = 1
, TIMER_MODE4_TMR4TRIGSEL_TMR10 = 2
, TIMER_MODE4_TMR4TRIGSEL_TMR11 = 3
,
TIMER_MODE4_TMR4TRIGSEL_TMR20 = 4
, TIMER_MODE4_TMR4TRIGSEL_TMR21 = 5
, TIMER_MODE4_TMR4TRIGSEL_TMR30 = 6
, TIMER_MODE4_TMR4TRIGSEL_TMR31 = 7
,
TIMER_MODE4_TMR4TRIGSEL_TMR40 = 8
, TIMER_MODE4_TMR4TRIGSEL_TMR41 = 9
, TIMER_MODE4_TMR4TRIGSEL_TMR50 = 10
, TIMER_MODE4_TMR4TRIGSEL_TMR51 = 11
,
TIMER_MODE4_TMR4TRIGSEL_TMR60 = 12
, TIMER_MODE4_TMR4TRIGSEL_TMR61 = 13
, TIMER_MODE4_TMR4TRIGSEL_TMR70 = 14
, TIMER_MODE4_TMR4TRIGSEL_TMR71 = 15
,
TIMER_MODE4_TMR4TRIGSEL_TMR80 = 16
, TIMER_MODE4_TMR4TRIGSEL_TMR81 = 17
, TIMER_MODE4_TMR4TRIGSEL_TMR90 = 18
, TIMER_MODE4_TMR4TRIGSEL_TMR91 = 19
,
TIMER_MODE4_TMR4TRIGSEL_TMR100 = 20
, TIMER_MODE4_TMR4TRIGSEL_TMR101 = 21
, TIMER_MODE4_TMR4TRIGSEL_TMR110 = 22
, TIMER_MODE4_TMR4TRIGSEL_TMR111 = 23
,
TIMER_MODE4_TMR4TRIGSEL_TMR120 = 24
, TIMER_MODE4_TMR4TRIGSEL_TMR121 = 25
, TIMER_MODE4_TMR4TRIGSEL_TMR130 = 26
, TIMER_MODE4_TMR4TRIGSEL_TMR131 = 27
,
TIMER_MODE4_TMR4TRIGSEL_TMR140 = 28
, TIMER_MODE4_TMR4TRIGSEL_TMR141 = 29
, TIMER_MODE4_TMR4TRIGSEL_TMR150 = 30
, TIMER_MODE4_TMR4TRIGSEL_TMR151 = 31
,
TIMER_MODE4_TMR4TRIGSEL_GPIO0 = 128
, TIMER_MODE4_TMR4TRIGSEL_GPIO127 = 255
} |
| |
| enum | TIMER_CTRL5_TMR5TMODE_Enum { TIMER_CTRL5_TMR5TMODE_DIS = 0
, TIMER_CTRL5_TMR5TMODE_RISE = 1
, TIMER_CTRL5_TMR5TMODE_FALL = 2
, TIMER_CTRL5_TMR5TMODE_BOTH = 3
} |
| |
| enum | TIMER_CTRL5_TMR5CLK_Enum {
TIMER_CTRL5_TMR5CLK_HFRC_DIV4 = 0
, TIMER_CTRL5_TMR5CLK_HFRC_DIV16 = 1
, TIMER_CTRL5_TMR5CLK_HFRC_DIV64 = 2
, TIMER_CTRL5_TMR5CLK_HFRC_DIV256 = 3
,
TIMER_CTRL5_TMR5CLK_HFRC_DIV1024 = 4
, TIMER_CTRL5_TMR5CLK_HFRC_DIV4K = 5
, TIMER_CTRL5_TMR5CLK_LFRC = 6
, TIMER_CTRL5_TMR5CLK_LFRC_DIV2 = 7
,
TIMER_CTRL5_TMR5CLK_LFRC_DIV32 = 8
, TIMER_CTRL5_TMR5CLK_LFRC_DIV1K = 9
, TIMER_CTRL5_TMR5CLK_XT = 10
, TIMER_CTRL5_TMR5CLK_XT_DIV2 = 11
,
TIMER_CTRL5_TMR5CLK_XT_DIV4 = 12
, TIMER_CTRL5_TMR5CLK_XT_DIV8 = 13
, TIMER_CTRL5_TMR5CLK_XT_DIV16 = 14
, TIMER_CTRL5_TMR5CLK_XT_DIV32 = 15
,
TIMER_CTRL5_TMR5CLK_XT_DIV128 = 16
, TIMER_CTRL5_TMR5CLK_RTC_100HZ = 17
, TIMER_CTRL5_TMR5CLK_BUCKC = 28
, TIMER_CTRL5_TMR5CLK_BUCKF = 29
,
TIMER_CTRL5_TMR5CLK_BUCKS = 30
, TIMER_CTRL5_TMR5CLK_BUCKC_LV = 31
, TIMER_CTRL5_TMR5CLK_TMR00 = 32
, TIMER_CTRL5_TMR5CLK_TMR01 = 33
,
TIMER_CTRL5_TMR5CLK_TMR10 = 34
, TIMER_CTRL5_TMR5CLK_TMR11 = 35
, TIMER_CTRL5_TMR5CLK_TMR20 = 36
, TIMER_CTRL5_TMR5CLK_TMR21 = 37
,
TIMER_CTRL5_TMR5CLK_TMR30 = 38
, TIMER_CTRL5_TMR5CLK_TMR31 = 39
, TIMER_CTRL5_TMR5CLK_TMR40 = 40
, TIMER_CTRL5_TMR5CLK_TMR41 = 41
,
TIMER_CTRL5_TMR5CLK_TMR50 = 42
, TIMER_CTRL5_TMR5CLK_TMR51 = 43
, TIMER_CTRL5_TMR5CLK_TMR60 = 44
, TIMER_CTRL5_TMR5CLK_TMR61 = 45
,
TIMER_CTRL5_TMR5CLK_TMR70 = 46
, TIMER_CTRL5_TMR5CLK_TMR71 = 47
, TIMER_CTRL5_TMR5CLK_TMR80 = 48
, TIMER_CTRL5_TMR5CLK_TMR81 = 49
,
TIMER_CTRL5_TMR5CLK_TMR90 = 50
, TIMER_CTRL5_TMR5CLK_TMR91 = 51
, TIMER_CTRL5_TMR5CLK_TMR100 = 52
, TIMER_CTRL5_TMR5CLK_TMR101 = 53
,
TIMER_CTRL5_TMR5CLK_TMR110 = 54
, TIMER_CTRL5_TMR5CLK_TMR111 = 55
, TIMER_CTRL5_TMR5CLK_TMR120 = 56
, TIMER_CTRL5_TMR5CLK_TMR121 = 57
,
TIMER_CTRL5_TMR5CLK_TMR130 = 58
, TIMER_CTRL5_TMR5CLK_TMR131 = 59
, TIMER_CTRL5_TMR5CLK_TMR140 = 60
, TIMER_CTRL5_TMR5CLK_TMR141 = 61
,
TIMER_CTRL5_TMR5CLK_TMR150 = 62
, TIMER_CTRL5_TMR5CLK_TMR151 = 63
, TIMER_CTRL5_TMR5CLK_GPIO0 = 128
, TIMER_CTRL5_TMR5CLK_GPIO63 = 191
,
TIMER_CTRL5_TMR5CLK_GPIO95 = 223
, TIMER_CTRL5_TMR5CLK_GPIO127 = 255
} |
| |
| enum | TIMER_CTRL5_TMR5FN_Enum {
TIMER_CTRL5_TMR5FN_EDGE = 1
, TIMER_CTRL5_TMR5FN_UPCOUNT = 2
, TIMER_CTRL5_TMR5FN_PWM = 4
, TIMER_CTRL5_TMR5FN_SINGLEPATTERN = 12
,
TIMER_CTRL5_TMR5FN_REPEATPATTERN = 13
} |
| |
| enum | TIMER_CTRL5_TMR5POL1_Enum { TIMER_CTRL5_TMR5POL1_NORMAL = 0
, TIMER_CTRL5_TMR5POL1_INVERTED = 1
} |
| |
| enum | TIMER_CTRL5_TMR5POL0_Enum { TIMER_CTRL5_TMR5POL0_NORMAL = 0
, TIMER_CTRL5_TMR5POL0_INVERTED = 1
} |
| |
| enum | TIMER_CTRL5_TMR5CLR_Enum { TIMER_CTRL5_TMR5CLR_CLEAR = 1
, TIMER_CTRL5_TMR5CLR_DEFAULT = 0
} |
| |
| enum | TIMER_CTRL5_TMR5EN_Enum { TIMER_CTRL5_TMR5EN_DIS = 0
, TIMER_CTRL5_TMR5EN_EN = 1
} |
| |
| enum | TIMER_MODE5_TMR5TRIGSEL_Enum {
TIMER_MODE5_TMR5TRIGSEL_TMR00 = 0
, TIMER_MODE5_TMR5TRIGSEL_TMR01 = 1
, TIMER_MODE5_TMR5TRIGSEL_TMR10 = 2
, TIMER_MODE5_TMR5TRIGSEL_TMR11 = 3
,
TIMER_MODE5_TMR5TRIGSEL_TMR20 = 4
, TIMER_MODE5_TMR5TRIGSEL_TMR21 = 5
, TIMER_MODE5_TMR5TRIGSEL_TMR30 = 6
, TIMER_MODE5_TMR5TRIGSEL_TMR31 = 7
,
TIMER_MODE5_TMR5TRIGSEL_TMR40 = 8
, TIMER_MODE5_TMR5TRIGSEL_TMR41 = 9
, TIMER_MODE5_TMR5TRIGSEL_TMR50 = 10
, TIMER_MODE5_TMR5TRIGSEL_TMR51 = 11
,
TIMER_MODE5_TMR5TRIGSEL_TMR60 = 12
, TIMER_MODE5_TMR5TRIGSEL_TMR61 = 13
, TIMER_MODE5_TMR5TRIGSEL_TMR70 = 14
, TIMER_MODE5_TMR5TRIGSEL_TMR71 = 15
,
TIMER_MODE5_TMR5TRIGSEL_TMR80 = 16
, TIMER_MODE5_TMR5TRIGSEL_TMR81 = 17
, TIMER_MODE5_TMR5TRIGSEL_TMR90 = 18
, TIMER_MODE5_TMR5TRIGSEL_TMR91 = 19
,
TIMER_MODE5_TMR5TRIGSEL_TMR100 = 20
, TIMER_MODE5_TMR5TRIGSEL_TMR101 = 21
, TIMER_MODE5_TMR5TRIGSEL_TMR110 = 22
, TIMER_MODE5_TMR5TRIGSEL_TMR111 = 23
,
TIMER_MODE5_TMR5TRIGSEL_TMR120 = 24
, TIMER_MODE5_TMR5TRIGSEL_TMR121 = 25
, TIMER_MODE5_TMR5TRIGSEL_TMR130 = 26
, TIMER_MODE5_TMR5TRIGSEL_TMR131 = 27
,
TIMER_MODE5_TMR5TRIGSEL_TMR140 = 28
, TIMER_MODE5_TMR5TRIGSEL_TMR141 = 29
, TIMER_MODE5_TMR5TRIGSEL_TMR150 = 30
, TIMER_MODE5_TMR5TRIGSEL_TMR151 = 31
,
TIMER_MODE5_TMR5TRIGSEL_GPIO0 = 128
, TIMER_MODE5_TMR5TRIGSEL_GPIO127 = 255
} |
| |
| enum | TIMER_CTRL6_TMR6TMODE_Enum { TIMER_CTRL6_TMR6TMODE_DIS = 0
, TIMER_CTRL6_TMR6TMODE_RISE = 1
, TIMER_CTRL6_TMR6TMODE_FALL = 2
, TIMER_CTRL6_TMR6TMODE_BOTH = 3
} |
| |
| enum | TIMER_CTRL6_TMR6CLK_Enum {
TIMER_CTRL6_TMR6CLK_HFRC_DIV4 = 0
, TIMER_CTRL6_TMR6CLK_HFRC_DIV16 = 1
, TIMER_CTRL6_TMR6CLK_HFRC_DIV64 = 2
, TIMER_CTRL6_TMR6CLK_HFRC_DIV256 = 3
,
TIMER_CTRL6_TMR6CLK_HFRC_DIV1024 = 4
, TIMER_CTRL6_TMR6CLK_HFRC_DIV4K = 5
, TIMER_CTRL6_TMR6CLK_LFRC = 6
, TIMER_CTRL6_TMR6CLK_LFRC_DIV2 = 7
,
TIMER_CTRL6_TMR6CLK_LFRC_DIV32 = 8
, TIMER_CTRL6_TMR6CLK_LFRC_DIV1K = 9
, TIMER_CTRL6_TMR6CLK_XT = 10
, TIMER_CTRL6_TMR6CLK_XT_DIV2 = 11
,
TIMER_CTRL6_TMR6CLK_XT_DIV4 = 12
, TIMER_CTRL6_TMR6CLK_XT_DIV8 = 13
, TIMER_CTRL6_TMR6CLK_XT_DIV16 = 14
, TIMER_CTRL6_TMR6CLK_XT_DIV32 = 15
,
TIMER_CTRL6_TMR6CLK_XT_DIV128 = 16
, TIMER_CTRL6_TMR6CLK_RTC_100HZ = 17
, TIMER_CTRL6_TMR6CLK_BUCKC = 28
, TIMER_CTRL6_TMR6CLK_BUCKF = 29
,
TIMER_CTRL6_TMR6CLK_BUCKS = 30
, TIMER_CTRL6_TMR6CLK_BUCKC_LV = 31
, TIMER_CTRL6_TMR6CLK_TMR00 = 32
, TIMER_CTRL6_TMR6CLK_TMR01 = 33
,
TIMER_CTRL6_TMR6CLK_TMR10 = 34
, TIMER_CTRL6_TMR6CLK_TMR11 = 35
, TIMER_CTRL6_TMR6CLK_TMR20 = 36
, TIMER_CTRL6_TMR6CLK_TMR21 = 37
,
TIMER_CTRL6_TMR6CLK_TMR30 = 38
, TIMER_CTRL6_TMR6CLK_TMR31 = 39
, TIMER_CTRL6_TMR6CLK_TMR40 = 40
, TIMER_CTRL6_TMR6CLK_TMR41 = 41
,
TIMER_CTRL6_TMR6CLK_TMR50 = 42
, TIMER_CTRL6_TMR6CLK_TMR51 = 43
, TIMER_CTRL6_TMR6CLK_TMR60 = 44
, TIMER_CTRL6_TMR6CLK_TMR61 = 45
,
TIMER_CTRL6_TMR6CLK_TMR70 = 46
, TIMER_CTRL6_TMR6CLK_TMR71 = 47
, TIMER_CTRL6_TMR6CLK_TMR80 = 48
, TIMER_CTRL6_TMR6CLK_TMR81 = 49
,
TIMER_CTRL6_TMR6CLK_TMR90 = 50
, TIMER_CTRL6_TMR6CLK_TMR91 = 51
, TIMER_CTRL6_TMR6CLK_TMR100 = 52
, TIMER_CTRL6_TMR6CLK_TMR101 = 53
,
TIMER_CTRL6_TMR6CLK_TMR110 = 54
, TIMER_CTRL6_TMR6CLK_TMR111 = 55
, TIMER_CTRL6_TMR6CLK_TMR120 = 56
, TIMER_CTRL6_TMR6CLK_TMR121 = 57
,
TIMER_CTRL6_TMR6CLK_TMR130 = 58
, TIMER_CTRL6_TMR6CLK_TMR131 = 59
, TIMER_CTRL6_TMR6CLK_TMR140 = 60
, TIMER_CTRL6_TMR6CLK_TMR141 = 61
,
TIMER_CTRL6_TMR6CLK_TMR150 = 62
, TIMER_CTRL6_TMR6CLK_TMR151 = 63
, TIMER_CTRL6_TMR6CLK_GPIO0 = 128
, TIMER_CTRL6_TMR6CLK_GPIO63 = 191
,
TIMER_CTRL6_TMR6CLK_GPIO95 = 223
, TIMER_CTRL6_TMR6CLK_GPIO127 = 255
} |
| |
| enum | TIMER_CTRL6_TMR6FN_Enum {
TIMER_CTRL6_TMR6FN_EDGE = 1
, TIMER_CTRL6_TMR6FN_UPCOUNT = 2
, TIMER_CTRL6_TMR6FN_PWM = 4
, TIMER_CTRL6_TMR6FN_SINGLEPATTERN = 12
,
TIMER_CTRL6_TMR6FN_REPEATPATTERN = 13
} |
| |
| enum | TIMER_CTRL6_TMR6POL1_Enum { TIMER_CTRL6_TMR6POL1_NORMAL = 0
, TIMER_CTRL6_TMR6POL1_INVERTED = 1
} |
| |
| enum | TIMER_CTRL6_TMR6POL0_Enum { TIMER_CTRL6_TMR6POL0_NORMAL = 0
, TIMER_CTRL6_TMR6POL0_INVERTED = 1
} |
| |
| enum | TIMER_CTRL6_TMR6CLR_Enum { TIMER_CTRL6_TMR6CLR_CLEAR = 1
, TIMER_CTRL6_TMR6CLR_DEFAULT = 0
} |
| |
| enum | TIMER_CTRL6_TMR6EN_Enum { TIMER_CTRL6_TMR6EN_DIS = 0
, TIMER_CTRL6_TMR6EN_EN = 1
} |
| |
| enum | TIMER_MODE6_TMR6TRIGSEL_Enum {
TIMER_MODE6_TMR6TRIGSEL_TMR00 = 0
, TIMER_MODE6_TMR6TRIGSEL_TMR01 = 1
, TIMER_MODE6_TMR6TRIGSEL_TMR10 = 2
, TIMER_MODE6_TMR6TRIGSEL_TMR11 = 3
,
TIMER_MODE6_TMR6TRIGSEL_TMR20 = 4
, TIMER_MODE6_TMR6TRIGSEL_TMR21 = 5
, TIMER_MODE6_TMR6TRIGSEL_TMR30 = 6
, TIMER_MODE6_TMR6TRIGSEL_TMR31 = 7
,
TIMER_MODE6_TMR6TRIGSEL_TMR40 = 8
, TIMER_MODE6_TMR6TRIGSEL_TMR41 = 9
, TIMER_MODE6_TMR6TRIGSEL_TMR50 = 10
, TIMER_MODE6_TMR6TRIGSEL_TMR51 = 11
,
TIMER_MODE6_TMR6TRIGSEL_TMR60 = 12
, TIMER_MODE6_TMR6TRIGSEL_TMR61 = 13
, TIMER_MODE6_TMR6TRIGSEL_TMR70 = 14
, TIMER_MODE6_TMR6TRIGSEL_TMR71 = 15
,
TIMER_MODE6_TMR6TRIGSEL_TMR80 = 16
, TIMER_MODE6_TMR6TRIGSEL_TMR81 = 17
, TIMER_MODE6_TMR6TRIGSEL_TMR90 = 18
, TIMER_MODE6_TMR6TRIGSEL_TMR91 = 19
,
TIMER_MODE6_TMR6TRIGSEL_TMR100 = 20
, TIMER_MODE6_TMR6TRIGSEL_TMR101 = 21
, TIMER_MODE6_TMR6TRIGSEL_TMR110 = 22
, TIMER_MODE6_TMR6TRIGSEL_TMR111 = 23
,
TIMER_MODE6_TMR6TRIGSEL_TMR120 = 24
, TIMER_MODE6_TMR6TRIGSEL_TMR121 = 25
, TIMER_MODE6_TMR6TRIGSEL_TMR130 = 26
, TIMER_MODE6_TMR6TRIGSEL_TMR131 = 27
,
TIMER_MODE6_TMR6TRIGSEL_TMR140 = 28
, TIMER_MODE6_TMR6TRIGSEL_TMR141 = 29
, TIMER_MODE6_TMR6TRIGSEL_TMR150 = 30
, TIMER_MODE6_TMR6TRIGSEL_TMR151 = 31
,
TIMER_MODE6_TMR6TRIGSEL_GPIO0 = 128
, TIMER_MODE6_TMR6TRIGSEL_GPIO127 = 255
} |
| |
| enum | TIMER_CTRL7_TMR7TMODE_Enum { TIMER_CTRL7_TMR7TMODE_DIS = 0
, TIMER_CTRL7_TMR7TMODE_RISE = 1
, TIMER_CTRL7_TMR7TMODE_FALL = 2
, TIMER_CTRL7_TMR7TMODE_BOTH = 3
} |
| |
| enum | TIMER_CTRL7_TMR7CLK_Enum {
TIMER_CTRL7_TMR7CLK_HFRC_DIV4 = 0
, TIMER_CTRL7_TMR7CLK_HFRC_DIV16 = 1
, TIMER_CTRL7_TMR7CLK_HFRC_DIV64 = 2
, TIMER_CTRL7_TMR7CLK_HFRC_DIV256 = 3
,
TIMER_CTRL7_TMR7CLK_HFRC_DIV1024 = 4
, TIMER_CTRL7_TMR7CLK_HFRC_DIV4K = 5
, TIMER_CTRL7_TMR7CLK_LFRC = 6
, TIMER_CTRL7_TMR7CLK_LFRC_DIV2 = 7
,
TIMER_CTRL7_TMR7CLK_LFRC_DIV32 = 8
, TIMER_CTRL7_TMR7CLK_LFRC_DIV1K = 9
, TIMER_CTRL7_TMR7CLK_XT = 10
, TIMER_CTRL7_TMR7CLK_XT_DIV2 = 11
,
TIMER_CTRL7_TMR7CLK_XT_DIV4 = 12
, TIMER_CTRL7_TMR7CLK_XT_DIV8 = 13
, TIMER_CTRL7_TMR7CLK_XT_DIV16 = 14
, TIMER_CTRL7_TMR7CLK_XT_DIV32 = 15
,
TIMER_CTRL7_TMR7CLK_XT_DIV128 = 16
, TIMER_CTRL7_TMR7CLK_RTC_100HZ = 17
, TIMER_CTRL7_TMR7CLK_BUCKC = 28
, TIMER_CTRL7_TMR7CLK_BUCKF = 29
,
TIMER_CTRL7_TMR7CLK_BUCKS = 30
, TIMER_CTRL7_TMR7CLK_BUCKC_LV = 31
, TIMER_CTRL7_TMR7CLK_TMR00 = 32
, TIMER_CTRL7_TMR7CLK_TMR01 = 33
,
TIMER_CTRL7_TMR7CLK_TMR10 = 34
, TIMER_CTRL7_TMR7CLK_TMR11 = 35
, TIMER_CTRL7_TMR7CLK_TMR20 = 36
, TIMER_CTRL7_TMR7CLK_TMR21 = 37
,
TIMER_CTRL7_TMR7CLK_TMR30 = 38
, TIMER_CTRL7_TMR7CLK_TMR31 = 39
, TIMER_CTRL7_TMR7CLK_TMR40 = 40
, TIMER_CTRL7_TMR7CLK_TMR41 = 41
,
TIMER_CTRL7_TMR7CLK_TMR50 = 42
, TIMER_CTRL7_TMR7CLK_TMR51 = 43
, TIMER_CTRL7_TMR7CLK_TMR60 = 44
, TIMER_CTRL7_TMR7CLK_TMR61 = 45
,
TIMER_CTRL7_TMR7CLK_TMR70 = 46
, TIMER_CTRL7_TMR7CLK_TMR71 = 47
, TIMER_CTRL7_TMR7CLK_TMR80 = 48
, TIMER_CTRL7_TMR7CLK_TMR81 = 49
,
TIMER_CTRL7_TMR7CLK_TMR90 = 50
, TIMER_CTRL7_TMR7CLK_TMR91 = 51
, TIMER_CTRL7_TMR7CLK_TMR100 = 52
, TIMER_CTRL7_TMR7CLK_TMR101 = 53
,
TIMER_CTRL7_TMR7CLK_TMR110 = 54
, TIMER_CTRL7_TMR7CLK_TMR111 = 55
, TIMER_CTRL7_TMR7CLK_TMR120 = 56
, TIMER_CTRL7_TMR7CLK_TMR121 = 57
,
TIMER_CTRL7_TMR7CLK_TMR130 = 58
, TIMER_CTRL7_TMR7CLK_TMR131 = 59
, TIMER_CTRL7_TMR7CLK_TMR140 = 60
, TIMER_CTRL7_TMR7CLK_TMR141 = 61
,
TIMER_CTRL7_TMR7CLK_TMR150 = 62
, TIMER_CTRL7_TMR7CLK_TMR151 = 63
, TIMER_CTRL7_TMR7CLK_GPIO0 = 128
, TIMER_CTRL7_TMR7CLK_GPIO63 = 191
,
TIMER_CTRL7_TMR7CLK_GPIO95 = 223
, TIMER_CTRL7_TMR7CLK_GPIO127 = 255
} |
| |
| enum | TIMER_CTRL7_TMR7FN_Enum {
TIMER_CTRL7_TMR7FN_EDGE = 1
, TIMER_CTRL7_TMR7FN_UPCOUNT = 2
, TIMER_CTRL7_TMR7FN_PWM = 4
, TIMER_CTRL7_TMR7FN_SINGLEPATTERN = 12
,
TIMER_CTRL7_TMR7FN_REPEATPATTERN = 13
} |
| |
| enum | TIMER_CTRL7_TMR7POL1_Enum { TIMER_CTRL7_TMR7POL1_NORMAL = 0
, TIMER_CTRL7_TMR7POL1_INVERTED = 1
} |
| |
| enum | TIMER_CTRL7_TMR7POL0_Enum { TIMER_CTRL7_TMR7POL0_NORMAL = 0
, TIMER_CTRL7_TMR7POL0_INVERTED = 1
} |
| |
| enum | TIMER_CTRL7_TMR7CLR_Enum { TIMER_CTRL7_TMR7CLR_CLEAR = 1
, TIMER_CTRL7_TMR7CLR_DEFAULT = 0
} |
| |
| enum | TIMER_CTRL7_TMR7EN_Enum { TIMER_CTRL7_TMR7EN_DIS = 0
, TIMER_CTRL7_TMR7EN_EN = 1
} |
| |
| enum | TIMER_MODE7_TMR7TRIGSEL_Enum {
TIMER_MODE7_TMR7TRIGSEL_TMR00 = 0
, TIMER_MODE7_TMR7TRIGSEL_TMR01 = 1
, TIMER_MODE7_TMR7TRIGSEL_TMR10 = 2
, TIMER_MODE7_TMR7TRIGSEL_TMR11 = 3
,
TIMER_MODE7_TMR7TRIGSEL_TMR20 = 4
, TIMER_MODE7_TMR7TRIGSEL_TMR21 = 5
, TIMER_MODE7_TMR7TRIGSEL_TMR30 = 6
, TIMER_MODE7_TMR7TRIGSEL_TMR31 = 7
,
TIMER_MODE7_TMR7TRIGSEL_TMR40 = 8
, TIMER_MODE7_TMR7TRIGSEL_TMR41 = 9
, TIMER_MODE7_TMR7TRIGSEL_TMR50 = 10
, TIMER_MODE7_TMR7TRIGSEL_TMR51 = 11
,
TIMER_MODE7_TMR7TRIGSEL_TMR60 = 12
, TIMER_MODE7_TMR7TRIGSEL_TMR61 = 13
, TIMER_MODE7_TMR7TRIGSEL_TMR70 = 14
, TIMER_MODE7_TMR7TRIGSEL_TMR71 = 15
,
TIMER_MODE7_TMR7TRIGSEL_TMR80 = 16
, TIMER_MODE7_TMR7TRIGSEL_TMR81 = 17
, TIMER_MODE7_TMR7TRIGSEL_TMR90 = 18
, TIMER_MODE7_TMR7TRIGSEL_TMR91 = 19
,
TIMER_MODE7_TMR7TRIGSEL_TMR100 = 20
, TIMER_MODE7_TMR7TRIGSEL_TMR101 = 21
, TIMER_MODE7_TMR7TRIGSEL_TMR110 = 22
, TIMER_MODE7_TMR7TRIGSEL_TMR111 = 23
,
TIMER_MODE7_TMR7TRIGSEL_TMR120 = 24
, TIMER_MODE7_TMR7TRIGSEL_TMR121 = 25
, TIMER_MODE7_TMR7TRIGSEL_TMR130 = 26
, TIMER_MODE7_TMR7TRIGSEL_TMR131 = 27
,
TIMER_MODE7_TMR7TRIGSEL_TMR140 = 28
, TIMER_MODE7_TMR7TRIGSEL_TMR141 = 29
, TIMER_MODE7_TMR7TRIGSEL_TMR150 = 30
, TIMER_MODE7_TMR7TRIGSEL_TMR151 = 31
,
TIMER_MODE7_TMR7TRIGSEL_GPIO0 = 128
, TIMER_MODE7_TMR7TRIGSEL_GPIO127 = 255
} |
| |
| enum | TIMER_CTRL8_TMR8TMODE_Enum { TIMER_CTRL8_TMR8TMODE_DIS = 0
, TIMER_CTRL8_TMR8TMODE_RISE = 1
, TIMER_CTRL8_TMR8TMODE_FALL = 2
, TIMER_CTRL8_TMR8TMODE_BOTH = 3
} |
| |
| enum | TIMER_CTRL8_TMR8CLK_Enum {
TIMER_CTRL8_TMR8CLK_HFRC_DIV4 = 0
, TIMER_CTRL8_TMR8CLK_HFRC_DIV16 = 1
, TIMER_CTRL8_TMR8CLK_HFRC_DIV64 = 2
, TIMER_CTRL8_TMR8CLK_HFRC_DIV256 = 3
,
TIMER_CTRL8_TMR8CLK_HFRC_DIV1024 = 4
, TIMER_CTRL8_TMR8CLK_HFRC_DIV4K = 5
, TIMER_CTRL8_TMR8CLK_LFRC = 6
, TIMER_CTRL8_TMR8CLK_LFRC_DIV2 = 7
,
TIMER_CTRL8_TMR8CLK_LFRC_DIV32 = 8
, TIMER_CTRL8_TMR8CLK_LFRC_DIV1K = 9
, TIMER_CTRL8_TMR8CLK_XT = 10
, TIMER_CTRL8_TMR8CLK_XT_DIV2 = 11
,
TIMER_CTRL8_TMR8CLK_XT_DIV4 = 12
, TIMER_CTRL8_TMR8CLK_XT_DIV8 = 13
, TIMER_CTRL8_TMR8CLK_XT_DIV16 = 14
, TIMER_CTRL8_TMR8CLK_XT_DIV32 = 15
,
TIMER_CTRL8_TMR8CLK_XT_DIV128 = 16
, TIMER_CTRL8_TMR8CLK_RTC_100HZ = 17
, TIMER_CTRL8_TMR8CLK_BUCKC = 28
, TIMER_CTRL8_TMR8CLK_BUCKF = 29
,
TIMER_CTRL8_TMR8CLK_BUCKS = 30
, TIMER_CTRL8_TMR8CLK_BUCKC_LV = 31
, TIMER_CTRL8_TMR8CLK_TMR00 = 32
, TIMER_CTRL8_TMR8CLK_TMR01 = 33
,
TIMER_CTRL8_TMR8CLK_TMR10 = 34
, TIMER_CTRL8_TMR8CLK_TMR11 = 35
, TIMER_CTRL8_TMR8CLK_TMR20 = 36
, TIMER_CTRL8_TMR8CLK_TMR21 = 37
,
TIMER_CTRL8_TMR8CLK_TMR30 = 38
, TIMER_CTRL8_TMR8CLK_TMR31 = 39
, TIMER_CTRL8_TMR8CLK_TMR40 = 40
, TIMER_CTRL8_TMR8CLK_TMR41 = 41
,
TIMER_CTRL8_TMR8CLK_TMR50 = 42
, TIMER_CTRL8_TMR8CLK_TMR51 = 43
, TIMER_CTRL8_TMR8CLK_TMR60 = 44
, TIMER_CTRL8_TMR8CLK_TMR61 = 45
,
TIMER_CTRL8_TMR8CLK_TMR70 = 46
, TIMER_CTRL8_TMR8CLK_TMR71 = 47
, TIMER_CTRL8_TMR8CLK_TMR80 = 48
, TIMER_CTRL8_TMR8CLK_TMR81 = 49
,
TIMER_CTRL8_TMR8CLK_TMR90 = 50
, TIMER_CTRL8_TMR8CLK_TMR91 = 51
, TIMER_CTRL8_TMR8CLK_TMR100 = 52
, TIMER_CTRL8_TMR8CLK_TMR101 = 53
,
TIMER_CTRL8_TMR8CLK_TMR110 = 54
, TIMER_CTRL8_TMR8CLK_TMR111 = 55
, TIMER_CTRL8_TMR8CLK_TMR120 = 56
, TIMER_CTRL8_TMR8CLK_TMR121 = 57
,
TIMER_CTRL8_TMR8CLK_TMR130 = 58
, TIMER_CTRL8_TMR8CLK_TMR131 = 59
, TIMER_CTRL8_TMR8CLK_TMR140 = 60
, TIMER_CTRL8_TMR8CLK_TMR141 = 61
,
TIMER_CTRL8_TMR8CLK_TMR150 = 62
, TIMER_CTRL8_TMR8CLK_TMR151 = 63
, TIMER_CTRL8_TMR8CLK_GPIO0 = 128
, TIMER_CTRL8_TMR8CLK_GPIO63 = 191
,
TIMER_CTRL8_TMR8CLK_GPIO95 = 223
, TIMER_CTRL8_TMR8CLK_GPIO127 = 255
} |
| |
| enum | TIMER_CTRL8_TMR8FN_Enum {
TIMER_CTRL8_TMR8FN_EDGE = 1
, TIMER_CTRL8_TMR8FN_UPCOUNT = 2
, TIMER_CTRL8_TMR8FN_PWM = 4
, TIMER_CTRL8_TMR8FN_SINGLEPATTERN = 12
,
TIMER_CTRL8_TMR8FN_REPEATPATTERN = 13
} |
| |
| enum | TIMER_CTRL8_TMR8POL1_Enum { TIMER_CTRL8_TMR8POL1_NORMAL = 0
, TIMER_CTRL8_TMR8POL1_INVERTED = 1
} |
| |
| enum | TIMER_CTRL8_TMR8POL0_Enum { TIMER_CTRL8_TMR8POL0_NORMAL = 0
, TIMER_CTRL8_TMR8POL0_INVERTED = 1
} |
| |
| enum | TIMER_CTRL8_TMR8CLR_Enum { TIMER_CTRL8_TMR8CLR_CLEAR = 1
, TIMER_CTRL8_TMR8CLR_DEFAULT = 0
} |
| |
| enum | TIMER_CTRL8_TMR8EN_Enum { TIMER_CTRL8_TMR8EN_DIS = 0
, TIMER_CTRL8_TMR8EN_EN = 1
} |
| |
| enum | TIMER_MODE8_TMR8TRIGSEL_Enum {
TIMER_MODE8_TMR8TRIGSEL_TMR00 = 0
, TIMER_MODE8_TMR8TRIGSEL_TMR01 = 1
, TIMER_MODE8_TMR8TRIGSEL_TMR10 = 2
, TIMER_MODE8_TMR8TRIGSEL_TMR11 = 3
,
TIMER_MODE8_TMR8TRIGSEL_TMR20 = 4
, TIMER_MODE8_TMR8TRIGSEL_TMR21 = 5
, TIMER_MODE8_TMR8TRIGSEL_TMR30 = 6
, TIMER_MODE8_TMR8TRIGSEL_TMR31 = 7
,
TIMER_MODE8_TMR8TRIGSEL_TMR40 = 8
, TIMER_MODE8_TMR8TRIGSEL_TMR41 = 9
, TIMER_MODE8_TMR8TRIGSEL_TMR50 = 10
, TIMER_MODE8_TMR8TRIGSEL_TMR51 = 11
,
TIMER_MODE8_TMR8TRIGSEL_TMR60 = 12
, TIMER_MODE8_TMR8TRIGSEL_TMR61 = 13
, TIMER_MODE8_TMR8TRIGSEL_TMR70 = 14
, TIMER_MODE8_TMR8TRIGSEL_TMR71 = 15
,
TIMER_MODE8_TMR8TRIGSEL_TMR80 = 16
, TIMER_MODE8_TMR8TRIGSEL_TMR81 = 17
, TIMER_MODE8_TMR8TRIGSEL_TMR90 = 18
, TIMER_MODE8_TMR8TRIGSEL_TMR91 = 19
,
TIMER_MODE8_TMR8TRIGSEL_TMR100 = 20
, TIMER_MODE8_TMR8TRIGSEL_TMR101 = 21
, TIMER_MODE8_TMR8TRIGSEL_TMR110 = 22
, TIMER_MODE8_TMR8TRIGSEL_TMR111 = 23
,
TIMER_MODE8_TMR8TRIGSEL_TMR120 = 24
, TIMER_MODE8_TMR8TRIGSEL_TMR121 = 25
, TIMER_MODE8_TMR8TRIGSEL_TMR130 = 26
, TIMER_MODE8_TMR8TRIGSEL_TMR131 = 27
,
TIMER_MODE8_TMR8TRIGSEL_TMR140 = 28
, TIMER_MODE8_TMR8TRIGSEL_TMR141 = 29
, TIMER_MODE8_TMR8TRIGSEL_TMR150 = 30
, TIMER_MODE8_TMR8TRIGSEL_TMR151 = 31
,
TIMER_MODE8_TMR8TRIGSEL_GPIO0 = 128
, TIMER_MODE8_TMR8TRIGSEL_GPIO127 = 255
} |
| |
| enum | TIMER_CTRL9_TMR9TMODE_Enum { TIMER_CTRL9_TMR9TMODE_DIS = 0
, TIMER_CTRL9_TMR9TMODE_RISE = 1
, TIMER_CTRL9_TMR9TMODE_FALL = 2
, TIMER_CTRL9_TMR9TMODE_BOTH = 3
} |
| |
| enum | TIMER_CTRL9_TMR9CLK_Enum {
TIMER_CTRL9_TMR9CLK_HFRC_DIV4 = 0
, TIMER_CTRL9_TMR9CLK_HFRC_DIV16 = 1
, TIMER_CTRL9_TMR9CLK_HFRC_DIV64 = 2
, TIMER_CTRL9_TMR9CLK_HFRC_DIV256 = 3
,
TIMER_CTRL9_TMR9CLK_HFRC_DIV1024 = 4
, TIMER_CTRL9_TMR9CLK_HFRC_DIV4K = 5
, TIMER_CTRL9_TMR9CLK_LFRC = 6
, TIMER_CTRL9_TMR9CLK_LFRC_DIV2 = 7
,
TIMER_CTRL9_TMR9CLK_LFRC_DIV32 = 8
, TIMER_CTRL9_TMR9CLK_LFRC_DIV1K = 9
, TIMER_CTRL9_TMR9CLK_XT = 10
, TIMER_CTRL9_TMR9CLK_XT_DIV2 = 11
,
TIMER_CTRL9_TMR9CLK_XT_DIV4 = 12
, TIMER_CTRL9_TMR9CLK_XT_DIV8 = 13
, TIMER_CTRL9_TMR9CLK_XT_DIV16 = 14
, TIMER_CTRL9_TMR9CLK_XT_DIV32 = 15
,
TIMER_CTRL9_TMR9CLK_XT_DIV128 = 16
, TIMER_CTRL9_TMR9CLK_RTC_100HZ = 17
, TIMER_CTRL9_TMR9CLK_BUCKC = 28
, TIMER_CTRL9_TMR9CLK_BUCKF = 29
,
TIMER_CTRL9_TMR9CLK_BUCKS = 30
, TIMER_CTRL9_TMR9CLK_BUCKC_LV = 31
, TIMER_CTRL9_TMR9CLK_TMR00 = 32
, TIMER_CTRL9_TMR9CLK_TMR01 = 33
,
TIMER_CTRL9_TMR9CLK_TMR10 = 34
, TIMER_CTRL9_TMR9CLK_TMR11 = 35
, TIMER_CTRL9_TMR9CLK_TMR20 = 36
, TIMER_CTRL9_TMR9CLK_TMR21 = 37
,
TIMER_CTRL9_TMR9CLK_TMR30 = 38
, TIMER_CTRL9_TMR9CLK_TMR31 = 39
, TIMER_CTRL9_TMR9CLK_TMR40 = 40
, TIMER_CTRL9_TMR9CLK_TMR41 = 41
,
TIMER_CTRL9_TMR9CLK_TMR50 = 42
, TIMER_CTRL9_TMR9CLK_TMR51 = 43
, TIMER_CTRL9_TMR9CLK_TMR60 = 44
, TIMER_CTRL9_TMR9CLK_TMR61 = 45
,
TIMER_CTRL9_TMR9CLK_TMR70 = 46
, TIMER_CTRL9_TMR9CLK_TMR71 = 47
, TIMER_CTRL9_TMR9CLK_TMR80 = 48
, TIMER_CTRL9_TMR9CLK_TMR81 = 49
,
TIMER_CTRL9_TMR9CLK_TMR90 = 50
, TIMER_CTRL9_TMR9CLK_TMR91 = 51
, TIMER_CTRL9_TMR9CLK_TMR100 = 52
, TIMER_CTRL9_TMR9CLK_TMR101 = 53
,
TIMER_CTRL9_TMR9CLK_TMR110 = 54
, TIMER_CTRL9_TMR9CLK_TMR111 = 55
, TIMER_CTRL9_TMR9CLK_TMR120 = 56
, TIMER_CTRL9_TMR9CLK_TMR121 = 57
,
TIMER_CTRL9_TMR9CLK_TMR130 = 58
, TIMER_CTRL9_TMR9CLK_TMR131 = 59
, TIMER_CTRL9_TMR9CLK_TMR140 = 60
, TIMER_CTRL9_TMR9CLK_TMR141 = 61
,
TIMER_CTRL9_TMR9CLK_TMR150 = 62
, TIMER_CTRL9_TMR9CLK_TMR151 = 63
, TIMER_CTRL9_TMR9CLK_GPIO0 = 128
, TIMER_CTRL9_TMR9CLK_GPIO63 = 191
,
TIMER_CTRL9_TMR9CLK_GPIO95 = 223
, TIMER_CTRL9_TMR9CLK_GPIO127 = 255
} |
| |
| enum | TIMER_CTRL9_TMR9FN_Enum {
TIMER_CTRL9_TMR9FN_EDGE = 1
, TIMER_CTRL9_TMR9FN_UPCOUNT = 2
, TIMER_CTRL9_TMR9FN_PWM = 4
, TIMER_CTRL9_TMR9FN_SINGLEPATTERN = 12
,
TIMER_CTRL9_TMR9FN_REPEATPATTERN = 13
} |
| |
| enum | TIMER_CTRL9_TMR9POL1_Enum { TIMER_CTRL9_TMR9POL1_NORMAL = 0
, TIMER_CTRL9_TMR9POL1_INVERTED = 1
} |
| |
| enum | TIMER_CTRL9_TMR9POL0_Enum { TIMER_CTRL9_TMR9POL0_NORMAL = 0
, TIMER_CTRL9_TMR9POL0_INVERTED = 1
} |
| |
| enum | TIMER_CTRL9_TMR9CLR_Enum { TIMER_CTRL9_TMR9CLR_CLEAR = 1
, TIMER_CTRL9_TMR9CLR_DEFAULT = 0
} |
| |
| enum | TIMER_CTRL9_TMR9EN_Enum { TIMER_CTRL9_TMR9EN_DIS = 0
, TIMER_CTRL9_TMR9EN_EN = 1
} |
| |
| enum | TIMER_MODE9_TMR9TRIGSEL_Enum {
TIMER_MODE9_TMR9TRIGSEL_TMR00 = 0
, TIMER_MODE9_TMR9TRIGSEL_TMR01 = 1
, TIMER_MODE9_TMR9TRIGSEL_TMR10 = 2
, TIMER_MODE9_TMR9TRIGSEL_TMR11 = 3
,
TIMER_MODE9_TMR9TRIGSEL_TMR20 = 4
, TIMER_MODE9_TMR9TRIGSEL_TMR21 = 5
, TIMER_MODE9_TMR9TRIGSEL_TMR30 = 6
, TIMER_MODE9_TMR9TRIGSEL_TMR31 = 7
,
TIMER_MODE9_TMR9TRIGSEL_TMR40 = 8
, TIMER_MODE9_TMR9TRIGSEL_TMR41 = 9
, TIMER_MODE9_TMR9TRIGSEL_TMR50 = 10
, TIMER_MODE9_TMR9TRIGSEL_TMR51 = 11
,
TIMER_MODE9_TMR9TRIGSEL_TMR60 = 12
, TIMER_MODE9_TMR9TRIGSEL_TMR61 = 13
, TIMER_MODE9_TMR9TRIGSEL_TMR70 = 14
, TIMER_MODE9_TMR9TRIGSEL_TMR71 = 15
,
TIMER_MODE9_TMR9TRIGSEL_TMR80 = 16
, TIMER_MODE9_TMR9TRIGSEL_TMR81 = 17
, TIMER_MODE9_TMR9TRIGSEL_TMR90 = 18
, TIMER_MODE9_TMR9TRIGSEL_TMR91 = 19
,
TIMER_MODE9_TMR9TRIGSEL_TMR100 = 20
, TIMER_MODE9_TMR9TRIGSEL_TMR101 = 21
, TIMER_MODE9_TMR9TRIGSEL_TMR110 = 22
, TIMER_MODE9_TMR9TRIGSEL_TMR111 = 23
,
TIMER_MODE9_TMR9TRIGSEL_TMR120 = 24
, TIMER_MODE9_TMR9TRIGSEL_TMR121 = 25
, TIMER_MODE9_TMR9TRIGSEL_TMR130 = 26
, TIMER_MODE9_TMR9TRIGSEL_TMR131 = 27
,
TIMER_MODE9_TMR9TRIGSEL_TMR140 = 28
, TIMER_MODE9_TMR9TRIGSEL_TMR141 = 29
, TIMER_MODE9_TMR9TRIGSEL_TMR150 = 30
, TIMER_MODE9_TMR9TRIGSEL_TMR151 = 31
,
TIMER_MODE9_TMR9TRIGSEL_GPIO0 = 128
, TIMER_MODE9_TMR9TRIGSEL_GPIO127 = 255
} |
| |
| enum | TIMER_CTRL10_TMR10TMODE_Enum { TIMER_CTRL10_TMR10TMODE_DIS = 0
, TIMER_CTRL10_TMR10TMODE_RISE = 1
, TIMER_CTRL10_TMR10TMODE_FALL = 2
, TIMER_CTRL10_TMR10TMODE_BOTH = 3
} |
| |
| enum | TIMER_CTRL10_TMR10CLK_Enum {
TIMER_CTRL10_TMR10CLK_HFRC_DIV4 = 0
, TIMER_CTRL10_TMR10CLK_HFRC_DIV16 = 1
, TIMER_CTRL10_TMR10CLK_HFRC_DIV64 = 2
, TIMER_CTRL10_TMR10CLK_HFRC_DIV256 = 3
,
TIMER_CTRL10_TMR10CLK_HFRC_DIV1024 = 4
, TIMER_CTRL10_TMR10CLK_HFRC_DIV4K = 5
, TIMER_CTRL10_TMR10CLK_LFRC = 6
, TIMER_CTRL10_TMR10CLK_LFRC_DIV2 = 7
,
TIMER_CTRL10_TMR10CLK_LFRC_DIV32 = 8
, TIMER_CTRL10_TMR10CLK_LFRC_DIV1K = 9
, TIMER_CTRL10_TMR10CLK_XT = 10
, TIMER_CTRL10_TMR10CLK_XT_DIV2 = 11
,
TIMER_CTRL10_TMR10CLK_XT_DIV4 = 12
, TIMER_CTRL10_TMR10CLK_XT_DIV8 = 13
, TIMER_CTRL10_TMR10CLK_XT_DIV16 = 14
, TIMER_CTRL10_TMR10CLK_XT_DIV32 = 15
,
TIMER_CTRL10_TMR10CLK_XT_DIV128 = 16
, TIMER_CTRL10_TMR10CLK_RTC_100HZ = 17
, TIMER_CTRL10_TMR10CLK_BUCKC = 28
, TIMER_CTRL10_TMR10CLK_BUCKF = 29
,
TIMER_CTRL10_TMR10CLK_BUCKS = 30
, TIMER_CTRL10_TMR10CLK_BUCKC_LV = 31
, TIMER_CTRL10_TMR10CLK_TMR00 = 32
, TIMER_CTRL10_TMR10CLK_TMR01 = 33
,
TIMER_CTRL10_TMR10CLK_TMR10 = 34
, TIMER_CTRL10_TMR10CLK_TMR11 = 35
, TIMER_CTRL10_TMR10CLK_TMR20 = 36
, TIMER_CTRL10_TMR10CLK_TMR21 = 37
,
TIMER_CTRL10_TMR10CLK_TMR30 = 38
, TIMER_CTRL10_TMR10CLK_TMR31 = 39
, TIMER_CTRL10_TMR10CLK_TMR40 = 40
, TIMER_CTRL10_TMR10CLK_TMR41 = 41
,
TIMER_CTRL10_TMR10CLK_TMR50 = 42
, TIMER_CTRL10_TMR10CLK_TMR51 = 43
, TIMER_CTRL10_TMR10CLK_TMR60 = 44
, TIMER_CTRL10_TMR10CLK_TMR61 = 45
,
TIMER_CTRL10_TMR10CLK_TMR70 = 46
, TIMER_CTRL10_TMR10CLK_TMR71 = 47
, TIMER_CTRL10_TMR10CLK_TMR80 = 48
, TIMER_CTRL10_TMR10CLK_TMR81 = 49
,
TIMER_CTRL10_TMR10CLK_TMR90 = 50
, TIMER_CTRL10_TMR10CLK_TMR91 = 51
, TIMER_CTRL10_TMR10CLK_TMR100 = 52
, TIMER_CTRL10_TMR10CLK_TMR101 = 53
,
TIMER_CTRL10_TMR10CLK_TMR110 = 54
, TIMER_CTRL10_TMR10CLK_TMR111 = 55
, TIMER_CTRL10_TMR10CLK_TMR120 = 56
, TIMER_CTRL10_TMR10CLK_TMR121 = 57
,
TIMER_CTRL10_TMR10CLK_TMR130 = 58
, TIMER_CTRL10_TMR10CLK_TMR131 = 59
, TIMER_CTRL10_TMR10CLK_TMR140 = 60
, TIMER_CTRL10_TMR10CLK_TMR141 = 61
,
TIMER_CTRL10_TMR10CLK_TMR150 = 62
, TIMER_CTRL10_TMR10CLK_TMR151 = 63
, TIMER_CTRL10_TMR10CLK_GPIO0 = 128
, TIMER_CTRL10_TMR10CLK_GPIO63 = 191
,
TIMER_CTRL10_TMR10CLK_GPIO95 = 223
, TIMER_CTRL10_TMR10CLK_GPIO127 = 255
} |
| |
| enum | TIMER_CTRL10_TMR10FN_Enum {
TIMER_CTRL10_TMR10FN_EDGE = 1
, TIMER_CTRL10_TMR10FN_UPCOUNT = 2
, TIMER_CTRL10_TMR10FN_PWM = 4
, TIMER_CTRL10_TMR10FN_SINGLEPATTERN = 12
,
TIMER_CTRL10_TMR10FN_REPEATPATTERN = 13
} |
| |
| enum | TIMER_CTRL10_TMR10POL1_Enum { TIMER_CTRL10_TMR10POL1_NORMAL = 0
, TIMER_CTRL10_TMR10POL1_INVERTED = 1
} |
| |
| enum | TIMER_CTRL10_TMR10POL0_Enum { TIMER_CTRL10_TMR10POL0_NORMAL = 0
, TIMER_CTRL10_TMR10POL0_INVERTED = 1
} |
| |
| enum | TIMER_CTRL10_TMR10CLR_Enum { TIMER_CTRL10_TMR10CLR_CLEAR = 1
, TIMER_CTRL10_TMR10CLR_DEFAULT = 0
} |
| |
| enum | TIMER_CTRL10_TMR10EN_Enum { TIMER_CTRL10_TMR10EN_DIS = 0
, TIMER_CTRL10_TMR10EN_EN = 1
} |
| |
| enum | TIMER_MODE10_TMR10TRIGSEL_Enum {
TIMER_MODE10_TMR10TRIGSEL_TMR00 = 0
, TIMER_MODE10_TMR10TRIGSEL_TMR01 = 1
, TIMER_MODE10_TMR10TRIGSEL_TMR10 = 2
, TIMER_MODE10_TMR10TRIGSEL_TMR11 = 3
,
TIMER_MODE10_TMR10TRIGSEL_TMR20 = 4
, TIMER_MODE10_TMR10TRIGSEL_TMR21 = 5
, TIMER_MODE10_TMR10TRIGSEL_TMR30 = 6
, TIMER_MODE10_TMR10TRIGSEL_TMR31 = 7
,
TIMER_MODE10_TMR10TRIGSEL_TMR40 = 8
, TIMER_MODE10_TMR10TRIGSEL_TMR41 = 9
, TIMER_MODE10_TMR10TRIGSEL_TMR50 = 10
, TIMER_MODE10_TMR10TRIGSEL_TMR51 = 11
,
TIMER_MODE10_TMR10TRIGSEL_TMR60 = 12
, TIMER_MODE10_TMR10TRIGSEL_TMR61 = 13
, TIMER_MODE10_TMR10TRIGSEL_TMR70 = 14
, TIMER_MODE10_TMR10TRIGSEL_TMR71 = 15
,
TIMER_MODE10_TMR10TRIGSEL_TMR80 = 16
, TIMER_MODE10_TMR10TRIGSEL_TMR81 = 17
, TIMER_MODE10_TMR10TRIGSEL_TMR90 = 18
, TIMER_MODE10_TMR10TRIGSEL_TMR91 = 19
,
TIMER_MODE10_TMR10TRIGSEL_TMR100 = 20
, TIMER_MODE10_TMR10TRIGSEL_TMR101 = 21
, TIMER_MODE10_TMR10TRIGSEL_TMR110 = 22
, TIMER_MODE10_TMR10TRIGSEL_TMR111 = 23
,
TIMER_MODE10_TMR10TRIGSEL_TMR120 = 24
, TIMER_MODE10_TMR10TRIGSEL_TMR121 = 25
, TIMER_MODE10_TMR10TRIGSEL_TMR130 = 26
, TIMER_MODE10_TMR10TRIGSEL_TMR131 = 27
,
TIMER_MODE10_TMR10TRIGSEL_TMR140 = 28
, TIMER_MODE10_TMR10TRIGSEL_TMR141 = 29
, TIMER_MODE10_TMR10TRIGSEL_TMR150 = 30
, TIMER_MODE10_TMR10TRIGSEL_TMR151 = 31
,
TIMER_MODE10_TMR10TRIGSEL_GPIO0 = 128
, TIMER_MODE10_TMR10TRIGSEL_GPIO127 = 255
} |
| |
| enum | TIMER_CTRL11_TMR11TMODE_Enum { TIMER_CTRL11_TMR11TMODE_DIS = 0
, TIMER_CTRL11_TMR11TMODE_RISE = 1
, TIMER_CTRL11_TMR11TMODE_FALL = 2
, TIMER_CTRL11_TMR11TMODE_BOTH = 3
} |
| |
| enum | TIMER_CTRL11_TMR11CLK_Enum {
TIMER_CTRL11_TMR11CLK_HFRC_DIV4 = 0
, TIMER_CTRL11_TMR11CLK_HFRC_DIV16 = 1
, TIMER_CTRL11_TMR11CLK_HFRC_DIV64 = 2
, TIMER_CTRL11_TMR11CLK_HFRC_DIV256 = 3
,
TIMER_CTRL11_TMR11CLK_HFRC_DIV1024 = 4
, TIMER_CTRL11_TMR11CLK_HFRC_DIV4K = 5
, TIMER_CTRL11_TMR11CLK_LFRC = 6
, TIMER_CTRL11_TMR11CLK_LFRC_DIV2 = 7
,
TIMER_CTRL11_TMR11CLK_LFRC_DIV32 = 8
, TIMER_CTRL11_TMR11CLK_LFRC_DIV1K = 9
, TIMER_CTRL11_TMR11CLK_XT = 10
, TIMER_CTRL11_TMR11CLK_XT_DIV2 = 11
,
TIMER_CTRL11_TMR11CLK_XT_DIV4 = 12
, TIMER_CTRL11_TMR11CLK_XT_DIV8 = 13
, TIMER_CTRL11_TMR11CLK_XT_DIV16 = 14
, TIMER_CTRL11_TMR11CLK_XT_DIV32 = 15
,
TIMER_CTRL11_TMR11CLK_XT_DIV128 = 16
, TIMER_CTRL11_TMR11CLK_RTC_100HZ = 17
, TIMER_CTRL11_TMR11CLK_BUCKC = 28
, TIMER_CTRL11_TMR11CLK_BUCKF = 29
,
TIMER_CTRL11_TMR11CLK_BUCKS = 30
, TIMER_CTRL11_TMR11CLK_BUCKC_LV = 31
, TIMER_CTRL11_TMR11CLK_TMR00 = 32
, TIMER_CTRL11_TMR11CLK_TMR01 = 33
,
TIMER_CTRL11_TMR11CLK_TMR10 = 34
, TIMER_CTRL11_TMR11CLK_TMR11 = 35
, TIMER_CTRL11_TMR11CLK_TMR20 = 36
, TIMER_CTRL11_TMR11CLK_TMR21 = 37
,
TIMER_CTRL11_TMR11CLK_TMR30 = 38
, TIMER_CTRL11_TMR11CLK_TMR31 = 39
, TIMER_CTRL11_TMR11CLK_TMR40 = 40
, TIMER_CTRL11_TMR11CLK_TMR41 = 41
,
TIMER_CTRL11_TMR11CLK_TMR50 = 42
, TIMER_CTRL11_TMR11CLK_TMR51 = 43
, TIMER_CTRL11_TMR11CLK_TMR60 = 44
, TIMER_CTRL11_TMR11CLK_TMR61 = 45
,
TIMER_CTRL11_TMR11CLK_TMR70 = 46
, TIMER_CTRL11_TMR11CLK_TMR71 = 47
, TIMER_CTRL11_TMR11CLK_TMR80 = 48
, TIMER_CTRL11_TMR11CLK_TMR81 = 49
,
TIMER_CTRL11_TMR11CLK_TMR90 = 50
, TIMER_CTRL11_TMR11CLK_TMR91 = 51
, TIMER_CTRL11_TMR11CLK_TMR100 = 52
, TIMER_CTRL11_TMR11CLK_TMR101 = 53
,
TIMER_CTRL11_TMR11CLK_TMR110 = 54
, TIMER_CTRL11_TMR11CLK_TMR111 = 55
, TIMER_CTRL11_TMR11CLK_TMR120 = 56
, TIMER_CTRL11_TMR11CLK_TMR121 = 57
,
TIMER_CTRL11_TMR11CLK_TMR130 = 58
, TIMER_CTRL11_TMR11CLK_TMR131 = 59
, TIMER_CTRL11_TMR11CLK_TMR140 = 60
, TIMER_CTRL11_TMR11CLK_TMR141 = 61
,
TIMER_CTRL11_TMR11CLK_TMR150 = 62
, TIMER_CTRL11_TMR11CLK_TMR151 = 63
, TIMER_CTRL11_TMR11CLK_GPIO0 = 128
, TIMER_CTRL11_TMR11CLK_GPIO63 = 191
,
TIMER_CTRL11_TMR11CLK_GPIO95 = 223
, TIMER_CTRL11_TMR11CLK_GPIO127 = 255
} |
| |
| enum | TIMER_CTRL11_TMR11FN_Enum {
TIMER_CTRL11_TMR11FN_EDGE = 1
, TIMER_CTRL11_TMR11FN_UPCOUNT = 2
, TIMER_CTRL11_TMR11FN_PWM = 4
, TIMER_CTRL11_TMR11FN_SINGLEPATTERN = 12
,
TIMER_CTRL11_TMR11FN_REPEATPATTERN = 13
} |
| |
| enum | TIMER_CTRL11_TMR11POL1_Enum { TIMER_CTRL11_TMR11POL1_NORMAL = 0
, TIMER_CTRL11_TMR11POL1_INVERTED = 1
} |
| |
| enum | TIMER_CTRL11_TMR11POL0_Enum { TIMER_CTRL11_TMR11POL0_NORMAL = 0
, TIMER_CTRL11_TMR11POL0_INVERTED = 1
} |
| |
| enum | TIMER_CTRL11_TMR11CLR_Enum { TIMER_CTRL11_TMR11CLR_CLEAR = 1
, TIMER_CTRL11_TMR11CLR_DEFAULT = 0
} |
| |
| enum | TIMER_CTRL11_TMR11EN_Enum { TIMER_CTRL11_TMR11EN_DIS = 0
, TIMER_CTRL11_TMR11EN_EN = 1
} |
| |
| enum | TIMER_MODE11_TMR11TRIGSEL_Enum {
TIMER_MODE11_TMR11TRIGSEL_TMR00 = 0
, TIMER_MODE11_TMR11TRIGSEL_TMR01 = 1
, TIMER_MODE11_TMR11TRIGSEL_TMR10 = 2
, TIMER_MODE11_TMR11TRIGSEL_TMR11 = 3
,
TIMER_MODE11_TMR11TRIGSEL_TMR20 = 4
, TIMER_MODE11_TMR11TRIGSEL_TMR21 = 5
, TIMER_MODE11_TMR11TRIGSEL_TMR30 = 6
, TIMER_MODE11_TMR11TRIGSEL_TMR31 = 7
,
TIMER_MODE11_TMR11TRIGSEL_TMR40 = 8
, TIMER_MODE11_TMR11TRIGSEL_TMR41 = 9
, TIMER_MODE11_TMR11TRIGSEL_TMR50 = 10
, TIMER_MODE11_TMR11TRIGSEL_TMR51 = 11
,
TIMER_MODE11_TMR11TRIGSEL_TMR60 = 12
, TIMER_MODE11_TMR11TRIGSEL_TMR61 = 13
, TIMER_MODE11_TMR11TRIGSEL_TMR70 = 14
, TIMER_MODE11_TMR11TRIGSEL_TMR71 = 15
,
TIMER_MODE11_TMR11TRIGSEL_TMR80 = 16
, TIMER_MODE11_TMR11TRIGSEL_TMR81 = 17
, TIMER_MODE11_TMR11TRIGSEL_TMR90 = 18
, TIMER_MODE11_TMR11TRIGSEL_TMR91 = 19
,
TIMER_MODE11_TMR11TRIGSEL_TMR100 = 20
, TIMER_MODE11_TMR11TRIGSEL_TMR101 = 21
, TIMER_MODE11_TMR11TRIGSEL_TMR110 = 22
, TIMER_MODE11_TMR11TRIGSEL_TMR111 = 23
,
TIMER_MODE11_TMR11TRIGSEL_TMR120 = 24
, TIMER_MODE11_TMR11TRIGSEL_TMR121 = 25
, TIMER_MODE11_TMR11TRIGSEL_TMR130 = 26
, TIMER_MODE11_TMR11TRIGSEL_TMR131 = 27
,
TIMER_MODE11_TMR11TRIGSEL_TMR140 = 28
, TIMER_MODE11_TMR11TRIGSEL_TMR141 = 29
, TIMER_MODE11_TMR11TRIGSEL_TMR150 = 30
, TIMER_MODE11_TMR11TRIGSEL_TMR151 = 31
,
TIMER_MODE11_TMR11TRIGSEL_GPIO0 = 128
, TIMER_MODE11_TMR11TRIGSEL_GPIO127 = 255
} |
| |
| enum | TIMER_CTRL12_TMR12TMODE_Enum { TIMER_CTRL12_TMR12TMODE_DIS = 0
, TIMER_CTRL12_TMR12TMODE_RISE = 1
, TIMER_CTRL12_TMR12TMODE_FALL = 2
, TIMER_CTRL12_TMR12TMODE_BOTH = 3
} |
| |
| enum | TIMER_CTRL12_TMR12CLK_Enum {
TIMER_CTRL12_TMR12CLK_HFRC_DIV4 = 0
, TIMER_CTRL12_TMR12CLK_HFRC_DIV16 = 1
, TIMER_CTRL12_TMR12CLK_HFRC_DIV64 = 2
, TIMER_CTRL12_TMR12CLK_HFRC_DIV256 = 3
,
TIMER_CTRL12_TMR12CLK_HFRC_DIV1024 = 4
, TIMER_CTRL12_TMR12CLK_HFRC_DIV4K = 5
, TIMER_CTRL12_TMR12CLK_LFRC = 6
, TIMER_CTRL12_TMR12CLK_LFRC_DIV2 = 7
,
TIMER_CTRL12_TMR12CLK_LFRC_DIV32 = 8
, TIMER_CTRL12_TMR12CLK_LFRC_DIV1K = 9
, TIMER_CTRL12_TMR12CLK_XT = 10
, TIMER_CTRL12_TMR12CLK_XT_DIV2 = 11
,
TIMER_CTRL12_TMR12CLK_XT_DIV4 = 12
, TIMER_CTRL12_TMR12CLK_XT_DIV8 = 13
, TIMER_CTRL12_TMR12CLK_XT_DIV16 = 14
, TIMER_CTRL12_TMR12CLK_XT_DIV32 = 15
,
TIMER_CTRL12_TMR12CLK_XT_DIV128 = 16
, TIMER_CTRL12_TMR12CLK_RTC_100HZ = 17
, TIMER_CTRL12_TMR12CLK_BUCKC = 28
, TIMER_CTRL12_TMR12CLK_BUCKF = 29
,
TIMER_CTRL12_TMR12CLK_BUCKS = 30
, TIMER_CTRL12_TMR12CLK_BUCKC_LV = 31
, TIMER_CTRL12_TMR12CLK_TMR00 = 32
, TIMER_CTRL12_TMR12CLK_TMR01 = 33
,
TIMER_CTRL12_TMR12CLK_TMR10 = 34
, TIMER_CTRL12_TMR12CLK_TMR11 = 35
, TIMER_CTRL12_TMR12CLK_TMR20 = 36
, TIMER_CTRL12_TMR12CLK_TMR21 = 37
,
TIMER_CTRL12_TMR12CLK_TMR30 = 38
, TIMER_CTRL12_TMR12CLK_TMR31 = 39
, TIMER_CTRL12_TMR12CLK_TMR40 = 40
, TIMER_CTRL12_TMR12CLK_TMR41 = 41
,
TIMER_CTRL12_TMR12CLK_TMR50 = 42
, TIMER_CTRL12_TMR12CLK_TMR51 = 43
, TIMER_CTRL12_TMR12CLK_TMR60 = 44
, TIMER_CTRL12_TMR12CLK_TMR61 = 45
,
TIMER_CTRL12_TMR12CLK_TMR70 = 46
, TIMER_CTRL12_TMR12CLK_TMR71 = 47
, TIMER_CTRL12_TMR12CLK_TMR80 = 48
, TIMER_CTRL12_TMR12CLK_TMR81 = 49
,
TIMER_CTRL12_TMR12CLK_TMR90 = 50
, TIMER_CTRL12_TMR12CLK_TMR91 = 51
, TIMER_CTRL12_TMR12CLK_TMR100 = 52
, TIMER_CTRL12_TMR12CLK_TMR101 = 53
,
TIMER_CTRL12_TMR12CLK_TMR110 = 54
, TIMER_CTRL12_TMR12CLK_TMR111 = 55
, TIMER_CTRL12_TMR12CLK_TMR120 = 56
, TIMER_CTRL12_TMR12CLK_TMR121 = 57
,
TIMER_CTRL12_TMR12CLK_TMR130 = 58
, TIMER_CTRL12_TMR12CLK_TMR131 = 59
, TIMER_CTRL12_TMR12CLK_TMR140 = 60
, TIMER_CTRL12_TMR12CLK_TMR141 = 61
,
TIMER_CTRL12_TMR12CLK_TMR150 = 62
, TIMER_CTRL12_TMR12CLK_TMR151 = 63
, TIMER_CTRL12_TMR12CLK_GPIO0 = 128
, TIMER_CTRL12_TMR12CLK_GPIO63 = 191
,
TIMER_CTRL12_TMR12CLK_GPIO95 = 223
, TIMER_CTRL12_TMR12CLK_GPIO127 = 255
} |
| |
| enum | TIMER_CTRL12_TMR12FN_Enum {
TIMER_CTRL12_TMR12FN_EDGE = 1
, TIMER_CTRL12_TMR12FN_UPCOUNT = 2
, TIMER_CTRL12_TMR12FN_PWM = 4
, TIMER_CTRL12_TMR12FN_SINGLEPATTERN = 12
,
TIMER_CTRL12_TMR12FN_REPEATPATTERN = 13
} |
| |
| enum | TIMER_CTRL12_TMR12POL1_Enum { TIMER_CTRL12_TMR12POL1_NORMAL = 0
, TIMER_CTRL12_TMR12POL1_INVERTED = 1
} |
| |
| enum | TIMER_CTRL12_TMR12POL0_Enum { TIMER_CTRL12_TMR12POL0_NORMAL = 0
, TIMER_CTRL12_TMR12POL0_INVERTED = 1
} |
| |
| enum | TIMER_CTRL12_TMR12CLR_Enum { TIMER_CTRL12_TMR12CLR_CLEAR = 1
, TIMER_CTRL12_TMR12CLR_DEFAULT = 0
} |
| |
| enum | TIMER_CTRL12_TMR12EN_Enum { TIMER_CTRL12_TMR12EN_DIS = 0
, TIMER_CTRL12_TMR12EN_EN = 1
} |
| |
| enum | TIMER_MODE12_TMR12TRIGSEL_Enum {
TIMER_MODE12_TMR12TRIGSEL_TMR00 = 0
, TIMER_MODE12_TMR12TRIGSEL_TMR01 = 1
, TIMER_MODE12_TMR12TRIGSEL_TMR10 = 2
, TIMER_MODE12_TMR12TRIGSEL_TMR11 = 3
,
TIMER_MODE12_TMR12TRIGSEL_TMR20 = 4
, TIMER_MODE12_TMR12TRIGSEL_TMR21 = 5
, TIMER_MODE12_TMR12TRIGSEL_TMR30 = 6
, TIMER_MODE12_TMR12TRIGSEL_TMR31 = 7
,
TIMER_MODE12_TMR12TRIGSEL_TMR40 = 8
, TIMER_MODE12_TMR12TRIGSEL_TMR41 = 9
, TIMER_MODE12_TMR12TRIGSEL_TMR50 = 10
, TIMER_MODE12_TMR12TRIGSEL_TMR51 = 11
,
TIMER_MODE12_TMR12TRIGSEL_TMR60 = 12
, TIMER_MODE12_TMR12TRIGSEL_TMR61 = 13
, TIMER_MODE12_TMR12TRIGSEL_TMR70 = 14
, TIMER_MODE12_TMR12TRIGSEL_TMR71 = 15
,
TIMER_MODE12_TMR12TRIGSEL_TMR80 = 16
, TIMER_MODE12_TMR12TRIGSEL_TMR81 = 17
, TIMER_MODE12_TMR12TRIGSEL_TMR90 = 18
, TIMER_MODE12_TMR12TRIGSEL_TMR91 = 19
,
TIMER_MODE12_TMR12TRIGSEL_TMR100 = 20
, TIMER_MODE12_TMR12TRIGSEL_TMR101 = 21
, TIMER_MODE12_TMR12TRIGSEL_TMR110 = 22
, TIMER_MODE12_TMR12TRIGSEL_TMR111 = 23
,
TIMER_MODE12_TMR12TRIGSEL_TMR120 = 24
, TIMER_MODE12_TMR12TRIGSEL_TMR121 = 25
, TIMER_MODE12_TMR12TRIGSEL_TMR130 = 26
, TIMER_MODE12_TMR12TRIGSEL_TMR131 = 27
,
TIMER_MODE12_TMR12TRIGSEL_TMR140 = 28
, TIMER_MODE12_TMR12TRIGSEL_TMR141 = 29
, TIMER_MODE12_TMR12TRIGSEL_TMR150 = 30
, TIMER_MODE12_TMR12TRIGSEL_TMR151 = 31
,
TIMER_MODE12_TMR12TRIGSEL_GPIO0 = 128
, TIMER_MODE12_TMR12TRIGSEL_GPIO127 = 255
} |
| |
| enum | TIMER_CTRL13_TMR13TMODE_Enum { TIMER_CTRL13_TMR13TMODE_DIS = 0
, TIMER_CTRL13_TMR13TMODE_RISE = 1
, TIMER_CTRL13_TMR13TMODE_FALL = 2
, TIMER_CTRL13_TMR13TMODE_BOTH = 3
} |
| |
| enum | TIMER_CTRL13_TMR13CLK_Enum {
TIMER_CTRL13_TMR13CLK_HFRC_DIV4 = 0
, TIMER_CTRL13_TMR13CLK_HFRC_DIV16 = 1
, TIMER_CTRL13_TMR13CLK_HFRC_DIV64 = 2
, TIMER_CTRL13_TMR13CLK_HFRC_DIV256 = 3
,
TIMER_CTRL13_TMR13CLK_HFRC_DIV1024 = 4
, TIMER_CTRL13_TMR13CLK_HFRC_DIV4K = 5
, TIMER_CTRL13_TMR13CLK_LFRC = 6
, TIMER_CTRL13_TMR13CLK_LFRC_DIV2 = 7
,
TIMER_CTRL13_TMR13CLK_LFRC_DIV32 = 8
, TIMER_CTRL13_TMR13CLK_LFRC_DIV1K = 9
, TIMER_CTRL13_TMR13CLK_XT = 10
, TIMER_CTRL13_TMR13CLK_XT_DIV2 = 11
,
TIMER_CTRL13_TMR13CLK_XT_DIV4 = 12
, TIMER_CTRL13_TMR13CLK_XT_DIV8 = 13
, TIMER_CTRL13_TMR13CLK_XT_DIV16 = 14
, TIMER_CTRL13_TMR13CLK_XT_DIV32 = 15
,
TIMER_CTRL13_TMR13CLK_XT_DIV128 = 16
, TIMER_CTRL13_TMR13CLK_RTC_100HZ = 17
, TIMER_CTRL13_TMR13CLK_BUCKC = 28
, TIMER_CTRL13_TMR13CLK_BUCKF = 29
,
TIMER_CTRL13_TMR13CLK_BUCKS = 30
, TIMER_CTRL13_TMR13CLK_BUCKC_LV = 31
, TIMER_CTRL13_TMR13CLK_TMR00 = 32
, TIMER_CTRL13_TMR13CLK_TMR01 = 33
,
TIMER_CTRL13_TMR13CLK_TMR10 = 34
, TIMER_CTRL13_TMR13CLK_TMR11 = 35
, TIMER_CTRL13_TMR13CLK_TMR20 = 36
, TIMER_CTRL13_TMR13CLK_TMR21 = 37
,
TIMER_CTRL13_TMR13CLK_TMR30 = 38
, TIMER_CTRL13_TMR13CLK_TMR31 = 39
, TIMER_CTRL13_TMR13CLK_TMR40 = 40
, TIMER_CTRL13_TMR13CLK_TMR41 = 41
,
TIMER_CTRL13_TMR13CLK_TMR50 = 42
, TIMER_CTRL13_TMR13CLK_TMR51 = 43
, TIMER_CTRL13_TMR13CLK_TMR60 = 44
, TIMER_CTRL13_TMR13CLK_TMR61 = 45
,
TIMER_CTRL13_TMR13CLK_TMR70 = 46
, TIMER_CTRL13_TMR13CLK_TMR71 = 47
, TIMER_CTRL13_TMR13CLK_TMR80 = 48
, TIMER_CTRL13_TMR13CLK_TMR81 = 49
,
TIMER_CTRL13_TMR13CLK_TMR90 = 50
, TIMER_CTRL13_TMR13CLK_TMR91 = 51
, TIMER_CTRL13_TMR13CLK_TMR100 = 52
, TIMER_CTRL13_TMR13CLK_TMR101 = 53
,
TIMER_CTRL13_TMR13CLK_TMR110 = 54
, TIMER_CTRL13_TMR13CLK_TMR111 = 55
, TIMER_CTRL13_TMR13CLK_TMR120 = 56
, TIMER_CTRL13_TMR13CLK_TMR121 = 57
,
TIMER_CTRL13_TMR13CLK_TMR130 = 58
, TIMER_CTRL13_TMR13CLK_TMR131 = 59
, TIMER_CTRL13_TMR13CLK_TMR140 = 60
, TIMER_CTRL13_TMR13CLK_TMR141 = 61
,
TIMER_CTRL13_TMR13CLK_TMR150 = 62
, TIMER_CTRL13_TMR13CLK_TMR151 = 63
, TIMER_CTRL13_TMR13CLK_GPIO0 = 128
, TIMER_CTRL13_TMR13CLK_GPIO63 = 191
,
TIMER_CTRL13_TMR13CLK_GPIO95 = 223
, TIMER_CTRL13_TMR13CLK_GPIO127 = 255
} |
| |
| enum | TIMER_CTRL13_TMR13FN_Enum {
TIMER_CTRL13_TMR13FN_EDGE = 1
, TIMER_CTRL13_TMR13FN_UPCOUNT = 2
, TIMER_CTRL13_TMR13FN_PWM = 4
, TIMER_CTRL13_TMR13FN_SINGLEPATTERN = 12
,
TIMER_CTRL13_TMR13FN_REPEATPATTERN = 13
} |
| |
| enum | TIMER_CTRL13_TMR13POL1_Enum { TIMER_CTRL13_TMR13POL1_NORMAL = 0
, TIMER_CTRL13_TMR13POL1_INVERTED = 1
} |
| |
| enum | TIMER_CTRL13_TMR13POL0_Enum { TIMER_CTRL13_TMR13POL0_NORMAL = 0
, TIMER_CTRL13_TMR13POL0_INVERTED = 1
} |
| |
| enum | TIMER_CTRL13_TMR13CLR_Enum { TIMER_CTRL13_TMR13CLR_CLEAR = 1
, TIMER_CTRL13_TMR13CLR_DEFAULT = 0
} |
| |
| enum | TIMER_CTRL13_TMR13EN_Enum { TIMER_CTRL13_TMR13EN_DIS = 0
, TIMER_CTRL13_TMR13EN_EN = 1
} |
| |
| enum | TIMER_MODE13_TMR13TRIGSEL_Enum {
TIMER_MODE13_TMR13TRIGSEL_TMR00 = 0
, TIMER_MODE13_TMR13TRIGSEL_TMR01 = 1
, TIMER_MODE13_TMR13TRIGSEL_TMR10 = 2
, TIMER_MODE13_TMR13TRIGSEL_TMR11 = 3
,
TIMER_MODE13_TMR13TRIGSEL_TMR20 = 4
, TIMER_MODE13_TMR13TRIGSEL_TMR21 = 5
, TIMER_MODE13_TMR13TRIGSEL_TMR30 = 6
, TIMER_MODE13_TMR13TRIGSEL_TMR31 = 7
,
TIMER_MODE13_TMR13TRIGSEL_TMR40 = 8
, TIMER_MODE13_TMR13TRIGSEL_TMR41 = 9
, TIMER_MODE13_TMR13TRIGSEL_TMR50 = 10
, TIMER_MODE13_TMR13TRIGSEL_TMR51 = 11
,
TIMER_MODE13_TMR13TRIGSEL_TMR60 = 12
, TIMER_MODE13_TMR13TRIGSEL_TMR61 = 13
, TIMER_MODE13_TMR13TRIGSEL_TMR70 = 14
, TIMER_MODE13_TMR13TRIGSEL_TMR71 = 15
,
TIMER_MODE13_TMR13TRIGSEL_TMR80 = 16
, TIMER_MODE13_TMR13TRIGSEL_TMR81 = 17
, TIMER_MODE13_TMR13TRIGSEL_TMR90 = 18
, TIMER_MODE13_TMR13TRIGSEL_TMR91 = 19
,
TIMER_MODE13_TMR13TRIGSEL_TMR100 = 20
, TIMER_MODE13_TMR13TRIGSEL_TMR101 = 21
, TIMER_MODE13_TMR13TRIGSEL_TMR110 = 22
, TIMER_MODE13_TMR13TRIGSEL_TMR111 = 23
,
TIMER_MODE13_TMR13TRIGSEL_TMR120 = 24
, TIMER_MODE13_TMR13TRIGSEL_TMR121 = 25
, TIMER_MODE13_TMR13TRIGSEL_TMR130 = 26
, TIMER_MODE13_TMR13TRIGSEL_TMR131 = 27
,
TIMER_MODE13_TMR13TRIGSEL_TMR140 = 28
, TIMER_MODE13_TMR13TRIGSEL_TMR141 = 29
, TIMER_MODE13_TMR13TRIGSEL_TMR150 = 30
, TIMER_MODE13_TMR13TRIGSEL_TMR151 = 31
,
TIMER_MODE13_TMR13TRIGSEL_GPIO0 = 128
, TIMER_MODE13_TMR13TRIGSEL_GPIO127 = 255
} |
| |
| enum | TIMER_CTRL14_TMR14TMODE_Enum { TIMER_CTRL14_TMR14TMODE_DIS = 0
, TIMER_CTRL14_TMR14TMODE_RISE = 1
, TIMER_CTRL14_TMR14TMODE_FALL = 2
, TIMER_CTRL14_TMR14TMODE_BOTH = 3
} |
| |
| enum | TIMER_CTRL14_TMR14CLK_Enum {
TIMER_CTRL14_TMR14CLK_HFRC_DIV4 = 0
, TIMER_CTRL14_TMR14CLK_HFRC_DIV16 = 1
, TIMER_CTRL14_TMR14CLK_HFRC_DIV64 = 2
, TIMER_CTRL14_TMR14CLK_HFRC_DIV256 = 3
,
TIMER_CTRL14_TMR14CLK_HFRC_DIV1024 = 4
, TIMER_CTRL14_TMR14CLK_HFRC_DIV4K = 5
, TIMER_CTRL14_TMR14CLK_LFRC = 6
, TIMER_CTRL14_TMR14CLK_LFRC_DIV2 = 7
,
TIMER_CTRL14_TMR14CLK_LFRC_DIV32 = 8
, TIMER_CTRL14_TMR14CLK_LFRC_DIV1K = 9
, TIMER_CTRL14_TMR14CLK_XT = 10
, TIMER_CTRL14_TMR14CLK_XT_DIV2 = 11
,
TIMER_CTRL14_TMR14CLK_XT_DIV4 = 12
, TIMER_CTRL14_TMR14CLK_XT_DIV8 = 13
, TIMER_CTRL14_TMR14CLK_XT_DIV16 = 14
, TIMER_CTRL14_TMR14CLK_XT_DIV32 = 15
,
TIMER_CTRL14_TMR14CLK_XT_DIV128 = 16
, TIMER_CTRL14_TMR14CLK_RTC_100HZ = 17
, TIMER_CTRL14_TMR14CLK_BUCKC = 28
, TIMER_CTRL14_TMR14CLK_BUCKF = 29
,
TIMER_CTRL14_TMR14CLK_BUCKS = 30
, TIMER_CTRL14_TMR14CLK_BUCKC_LV = 31
, TIMER_CTRL14_TMR14CLK_TMR00 = 32
, TIMER_CTRL14_TMR14CLK_TMR01 = 33
,
TIMER_CTRL14_TMR14CLK_TMR10 = 34
, TIMER_CTRL14_TMR14CLK_TMR11 = 35
, TIMER_CTRL14_TMR14CLK_TMR20 = 36
, TIMER_CTRL14_TMR14CLK_TMR21 = 37
,
TIMER_CTRL14_TMR14CLK_TMR30 = 38
, TIMER_CTRL14_TMR14CLK_TMR31 = 39
, TIMER_CTRL14_TMR14CLK_TMR40 = 40
, TIMER_CTRL14_TMR14CLK_TMR41 = 41
,
TIMER_CTRL14_TMR14CLK_TMR50 = 42
, TIMER_CTRL14_TMR14CLK_TMR51 = 43
, TIMER_CTRL14_TMR14CLK_TMR60 = 44
, TIMER_CTRL14_TMR14CLK_TMR61 = 45
,
TIMER_CTRL14_TMR14CLK_TMR70 = 46
, TIMER_CTRL14_TMR14CLK_TMR71 = 47
, TIMER_CTRL14_TMR14CLK_TMR80 = 48
, TIMER_CTRL14_TMR14CLK_TMR81 = 49
,
TIMER_CTRL14_TMR14CLK_TMR90 = 50
, TIMER_CTRL14_TMR14CLK_TMR91 = 51
, TIMER_CTRL14_TMR14CLK_TMR100 = 52
, TIMER_CTRL14_TMR14CLK_TMR101 = 53
,
TIMER_CTRL14_TMR14CLK_TMR110 = 54
, TIMER_CTRL14_TMR14CLK_TMR111 = 55
, TIMER_CTRL14_TMR14CLK_TMR120 = 56
, TIMER_CTRL14_TMR14CLK_TMR121 = 57
,
TIMER_CTRL14_TMR14CLK_TMR130 = 58
, TIMER_CTRL14_TMR14CLK_TMR131 = 59
, TIMER_CTRL14_TMR14CLK_TMR140 = 60
, TIMER_CTRL14_TMR14CLK_TMR141 = 61
,
TIMER_CTRL14_TMR14CLK_TMR150 = 62
, TIMER_CTRL14_TMR14CLK_TMR151 = 63
, TIMER_CTRL14_TMR14CLK_GPIO0 = 128
, TIMER_CTRL14_TMR14CLK_GPIO63 = 191
,
TIMER_CTRL14_TMR14CLK_GPIO95 = 223
, TIMER_CTRL14_TMR14CLK_GPIO127 = 255
} |
| |
| enum | TIMER_CTRL14_TMR14FN_Enum {
TIMER_CTRL14_TMR14FN_EDGE = 1
, TIMER_CTRL14_TMR14FN_UPCOUNT = 2
, TIMER_CTRL14_TMR14FN_PWM = 4
, TIMER_CTRL14_TMR14FN_SINGLEPATTERN = 12
,
TIMER_CTRL14_TMR14FN_REPEATPATTERN = 13
} |
| |
| enum | TIMER_CTRL14_TMR14POL1_Enum { TIMER_CTRL14_TMR14POL1_NORMAL = 0
, TIMER_CTRL14_TMR14POL1_INVERTED = 1
} |
| |
| enum | TIMER_CTRL14_TMR14POL0_Enum { TIMER_CTRL14_TMR14POL0_NORMAL = 0
, TIMER_CTRL14_TMR14POL0_INVERTED = 1
} |
| |
| enum | TIMER_CTRL14_TMR14CLR_Enum { TIMER_CTRL14_TMR14CLR_CLEAR = 1
, TIMER_CTRL14_TMR14CLR_DEFAULT = 0
} |
| |
| enum | TIMER_CTRL14_TMR14EN_Enum { TIMER_CTRL14_TMR14EN_DIS = 0
, TIMER_CTRL14_TMR14EN_EN = 1
} |
| |
| enum | TIMER_MODE14_TMR14TRIGSEL_Enum {
TIMER_MODE14_TMR14TRIGSEL_TMR00 = 0
, TIMER_MODE14_TMR14TRIGSEL_TMR01 = 1
, TIMER_MODE14_TMR14TRIGSEL_TMR10 = 2
, TIMER_MODE14_TMR14TRIGSEL_TMR11 = 3
,
TIMER_MODE14_TMR14TRIGSEL_TMR20 = 4
, TIMER_MODE14_TMR14TRIGSEL_TMR21 = 5
, TIMER_MODE14_TMR14TRIGSEL_TMR30 = 6
, TIMER_MODE14_TMR14TRIGSEL_TMR31 = 7
,
TIMER_MODE14_TMR14TRIGSEL_TMR40 = 8
, TIMER_MODE14_TMR14TRIGSEL_TMR41 = 9
, TIMER_MODE14_TMR14TRIGSEL_TMR50 = 10
, TIMER_MODE14_TMR14TRIGSEL_TMR51 = 11
,
TIMER_MODE14_TMR14TRIGSEL_TMR60 = 12
, TIMER_MODE14_TMR14TRIGSEL_TMR61 = 13
, TIMER_MODE14_TMR14TRIGSEL_TMR70 = 14
, TIMER_MODE14_TMR14TRIGSEL_TMR71 = 15
,
TIMER_MODE14_TMR14TRIGSEL_TMR80 = 16
, TIMER_MODE14_TMR14TRIGSEL_TMR81 = 17
, TIMER_MODE14_TMR14TRIGSEL_TMR90 = 18
, TIMER_MODE14_TMR14TRIGSEL_TMR91 = 19
,
TIMER_MODE14_TMR14TRIGSEL_TMR100 = 20
, TIMER_MODE14_TMR14TRIGSEL_TMR101 = 21
, TIMER_MODE14_TMR14TRIGSEL_TMR110 = 22
, TIMER_MODE14_TMR14TRIGSEL_TMR111 = 23
,
TIMER_MODE14_TMR14TRIGSEL_TMR120 = 24
, TIMER_MODE14_TMR14TRIGSEL_TMR121 = 25
, TIMER_MODE14_TMR14TRIGSEL_TMR130 = 26
, TIMER_MODE14_TMR14TRIGSEL_TMR131 = 27
,
TIMER_MODE14_TMR14TRIGSEL_TMR140 = 28
, TIMER_MODE14_TMR14TRIGSEL_TMR141 = 29
, TIMER_MODE14_TMR14TRIGSEL_TMR150 = 30
, TIMER_MODE14_TMR14TRIGSEL_TMR151 = 31
,
TIMER_MODE14_TMR14TRIGSEL_GPIO0 = 128
, TIMER_MODE14_TMR14TRIGSEL_GPIO127 = 255
} |
| |
| enum | TIMER_CTRL15_TMR15TMODE_Enum { TIMER_CTRL15_TMR15TMODE_DIS = 0
, TIMER_CTRL15_TMR15TMODE_RISE = 1
, TIMER_CTRL15_TMR15TMODE_FALL = 2
, TIMER_CTRL15_TMR15TMODE_BOTH = 3
} |
| |
| enum | TIMER_CTRL15_TMR15CLK_Enum {
TIMER_CTRL15_TMR15CLK_HFRC_DIV4 = 0
, TIMER_CTRL15_TMR15CLK_HFRC_DIV16 = 1
, TIMER_CTRL15_TMR15CLK_HFRC_DIV64 = 2
, TIMER_CTRL15_TMR15CLK_HFRC_DIV256 = 3
,
TIMER_CTRL15_TMR15CLK_HFRC_DIV1024 = 4
, TIMER_CTRL15_TMR15CLK_HFRC_DIV4K = 5
, TIMER_CTRL15_TMR15CLK_LFRC = 6
, TIMER_CTRL15_TMR15CLK_LFRC_DIV2 = 7
,
TIMER_CTRL15_TMR15CLK_LFRC_DIV32 = 8
, TIMER_CTRL15_TMR15CLK_LFRC_DIV1K = 9
, TIMER_CTRL15_TMR15CLK_XT = 10
, TIMER_CTRL15_TMR15CLK_XT_DIV2 = 11
,
TIMER_CTRL15_TMR15CLK_XT_DIV4 = 12
, TIMER_CTRL15_TMR15CLK_XT_DIV8 = 13
, TIMER_CTRL15_TMR15CLK_XT_DIV16 = 14
, TIMER_CTRL15_TMR15CLK_XT_DIV32 = 15
,
TIMER_CTRL15_TMR15CLK_XT_DIV128 = 16
, TIMER_CTRL15_TMR15CLK_RTC_100HZ = 17
, TIMER_CTRL15_TMR15CLK_BUCKC = 28
, TIMER_CTRL15_TMR15CLK_BUCKF = 29
,
TIMER_CTRL15_TMR15CLK_BUCKS = 30
, TIMER_CTRL15_TMR15CLK_BUCKC_LV = 31
, TIMER_CTRL15_TMR15CLK_TMR00 = 32
, TIMER_CTRL15_TMR15CLK_TMR01 = 33
,
TIMER_CTRL15_TMR15CLK_TMR10 = 34
, TIMER_CTRL15_TMR15CLK_TMR11 = 35
, TIMER_CTRL15_TMR15CLK_TMR20 = 36
, TIMER_CTRL15_TMR15CLK_TMR21 = 37
,
TIMER_CTRL15_TMR15CLK_TMR30 = 38
, TIMER_CTRL15_TMR15CLK_TMR31 = 39
, TIMER_CTRL15_TMR15CLK_TMR40 = 40
, TIMER_CTRL15_TMR15CLK_TMR41 = 41
,
TIMER_CTRL15_TMR15CLK_TMR50 = 42
, TIMER_CTRL15_TMR15CLK_TMR51 = 43
, TIMER_CTRL15_TMR15CLK_TMR60 = 44
, TIMER_CTRL15_TMR15CLK_TMR61 = 45
,
TIMER_CTRL15_TMR15CLK_TMR70 = 46
, TIMER_CTRL15_TMR15CLK_TMR71 = 47
, TIMER_CTRL15_TMR15CLK_TMR80 = 48
, TIMER_CTRL15_TMR15CLK_TMR81 = 49
,
TIMER_CTRL15_TMR15CLK_TMR90 = 50
, TIMER_CTRL15_TMR15CLK_TMR91 = 51
, TIMER_CTRL15_TMR15CLK_TMR100 = 52
, TIMER_CTRL15_TMR15CLK_TMR101 = 53
,
TIMER_CTRL15_TMR15CLK_TMR110 = 54
, TIMER_CTRL15_TMR15CLK_TMR111 = 55
, TIMER_CTRL15_TMR15CLK_TMR120 = 56
, TIMER_CTRL15_TMR15CLK_TMR121 = 57
,
TIMER_CTRL15_TMR15CLK_TMR130 = 58
, TIMER_CTRL15_TMR15CLK_TMR131 = 59
, TIMER_CTRL15_TMR15CLK_TMR140 = 60
, TIMER_CTRL15_TMR15CLK_TMR141 = 61
,
TIMER_CTRL15_TMR15CLK_TMR150 = 62
, TIMER_CTRL15_TMR15CLK_TMR151 = 63
, TIMER_CTRL15_TMR15CLK_GPIO0 = 128
, TIMER_CTRL15_TMR15CLK_GPIO63 = 191
,
TIMER_CTRL15_TMR15CLK_GPIO95 = 223
, TIMER_CTRL15_TMR15CLK_GPIO127 = 255
} |
| |
| enum | TIMER_CTRL15_TMR15FN_Enum {
TIMER_CTRL15_TMR15FN_EDGE = 1
, TIMER_CTRL15_TMR15FN_UPCOUNT = 2
, TIMER_CTRL15_TMR15FN_PWM = 4
, TIMER_CTRL15_TMR15FN_SINGLEPATTERN = 12
,
TIMER_CTRL15_TMR15FN_REPEATPATTERN = 13
} |
| |
| enum | TIMER_CTRL15_TMR15POL1_Enum { TIMER_CTRL15_TMR15POL1_NORMAL = 0
, TIMER_CTRL15_TMR15POL1_INVERTED = 1
} |
| |
| enum | TIMER_CTRL15_TMR15POL0_Enum { TIMER_CTRL15_TMR15POL0_NORMAL = 0
, TIMER_CTRL15_TMR15POL0_INVERTED = 1
} |
| |
| enum | TIMER_CTRL15_TMR15CLR_Enum { TIMER_CTRL15_TMR15CLR_CLEAR = 1
, TIMER_CTRL15_TMR15CLR_DEFAULT = 0
} |
| |
| enum | TIMER_CTRL15_TMR15EN_Enum { TIMER_CTRL15_TMR15EN_DIS = 0
, TIMER_CTRL15_TMR15EN_EN = 1
} |
| |
| enum | TIMER_MODE15_TMR15TRIGSEL_Enum {
TIMER_MODE15_TMR15TRIGSEL_TMR00 = 0
, TIMER_MODE15_TMR15TRIGSEL_TMR01 = 1
, TIMER_MODE15_TMR15TRIGSEL_TMR10 = 2
, TIMER_MODE15_TMR15TRIGSEL_TMR11 = 3
,
TIMER_MODE15_TMR15TRIGSEL_TMR20 = 4
, TIMER_MODE15_TMR15TRIGSEL_TMR21 = 5
, TIMER_MODE15_TMR15TRIGSEL_TMR30 = 6
, TIMER_MODE15_TMR15TRIGSEL_TMR31 = 7
,
TIMER_MODE15_TMR15TRIGSEL_TMR40 = 8
, TIMER_MODE15_TMR15TRIGSEL_TMR41 = 9
, TIMER_MODE15_TMR15TRIGSEL_TMR50 = 10
, TIMER_MODE15_TMR15TRIGSEL_TMR51 = 11
,
TIMER_MODE15_TMR15TRIGSEL_TMR60 = 12
, TIMER_MODE15_TMR15TRIGSEL_TMR61 = 13
, TIMER_MODE15_TMR15TRIGSEL_TMR70 = 14
, TIMER_MODE15_TMR15TRIGSEL_TMR71 = 15
,
TIMER_MODE15_TMR15TRIGSEL_TMR80 = 16
, TIMER_MODE15_TMR15TRIGSEL_TMR81 = 17
, TIMER_MODE15_TMR15TRIGSEL_TMR90 = 18
, TIMER_MODE15_TMR15TRIGSEL_TMR91 = 19
,
TIMER_MODE15_TMR15TRIGSEL_TMR100 = 20
, TIMER_MODE15_TMR15TRIGSEL_TMR101 = 21
, TIMER_MODE15_TMR15TRIGSEL_TMR110 = 22
, TIMER_MODE15_TMR15TRIGSEL_TMR111 = 23
,
TIMER_MODE15_TMR15TRIGSEL_TMR120 = 24
, TIMER_MODE15_TMR15TRIGSEL_TMR121 = 25
, TIMER_MODE15_TMR15TRIGSEL_TMR130 = 26
, TIMER_MODE15_TMR15TRIGSEL_TMR131 = 27
,
TIMER_MODE15_TMR15TRIGSEL_TMR140 = 28
, TIMER_MODE15_TMR15TRIGSEL_TMR141 = 29
, TIMER_MODE15_TMR15TRIGSEL_TMR150 = 30
, TIMER_MODE15_TMR15TRIGSEL_TMR151 = 31
,
TIMER_MODE15_TMR15TRIGSEL_GPIO0 = 128
, TIMER_MODE15_TMR15TRIGSEL_GPIO127 = 255
} |
| |
| enum | UART0_DR_OEDATA_Enum { UART0_DR_OEDATA_NOERR = 0
, UART0_DR_OEDATA_ERR = 1
} |
| |
| enum | UART0_DR_BEDATA_Enum { UART0_DR_BEDATA_NOERR = 0
, UART0_DR_BEDATA_ERR = 1
} |
| |
| enum | UART0_DR_PEDATA_Enum { UART0_DR_PEDATA_NOERR = 0
, UART0_DR_PEDATA_ERR = 1
} |
| |
| enum | UART0_DR_FEDATA_Enum { UART0_DR_FEDATA_NOERR = 0
, UART0_DR_FEDATA_ERR = 1
} |
| |
| enum | UART0_RSR_OESTAT_Enum { UART0_RSR_OESTAT_NOERR = 0
, UART0_RSR_OESTAT_ERR = 1
} |
| |
| enum | UART0_RSR_BESTAT_Enum { UART0_RSR_BESTAT_NOERR = 0
, UART0_RSR_BESTAT_ERR = 1
} |
| |
| enum | UART0_RSR_PESTAT_Enum { UART0_RSR_PESTAT_NOERR = 0
, UART0_RSR_PESTAT_ERR = 1
} |
| |
| enum | UART0_RSR_FESTAT_Enum { UART0_RSR_FESTAT_NOERR = 0
, UART0_RSR_FESTAT_ERR = 1
} |
| |
| enum | UART0_FR_TXFE_Enum { UART0_FR_TXFE_XMTFIFO_EMPTY = 1
, UART0_FR_TXFE_XMTFIFO_NOTEMPTY = 0
} |
| |
| enum | UART0_FR_RXFF_Enum { UART0_FR_RXFF_RCVFIFO_FULL = 1
, UART0_FR_RXFF_RCVFIFO_NOTFULL = 0
} |
| |
| enum | UART0_FR_TXFF_Enum { UART0_FR_TXFF_XMTFIFO_FULL = 1
, UART0_FR_TXFF_XMTFIFO_NOTFULL = 0
} |
| |
| enum | UART0_FR_RXFE_Enum { UART0_FR_RXFE_RCVFIFO_EMPTY = 1
, UART0_FR_RXFE_RCVFIFO_NOTEMPTY = 0
} |
| |
| enum | UART0_FR_BUSY_Enum { UART0_FR_BUSY_BUSY = 1
, UART0_FR_BUSY_NOTBUSY = 0
} |
| |
| enum | UART0_FR_DCD_Enum { UART0_FR_DCD_DETECTED = 1
, UART0_FR_DCD_DEFAULT = 0
} |
| |
| enum | UART0_FR_DSR_Enum { UART0_FR_DSR_READY = 1
, UART0_FR_DSR_NOTREADY = 0
} |
| |
| enum | UART0_FR_CTS_Enum { UART0_FR_CTS_CLEARTOSEND = 1
, UART0_FR_CTS_DEFAULT = 0
} |
| |
| enum | UART0_CR_CLKSEL_Enum {
UART0_CR_CLKSEL_NOCLK = 0
, UART0_CR_CLKSEL_24MHZ = 1
, UART0_CR_CLKSEL_12MHZ = 2
, UART0_CR_CLKSEL_6MHZ = 3
,
UART0_CR_CLKSEL_3MHZ = 4
, UART0_CR_CLKSEL_48MHZ = 5
} |
| |
| enum | USB_CFG0_EP5InIntStat_Enum { USB_CFG0_EP5InIntStat_INACTIVE = 0
, USB_CFG0_EP5InIntStat_ACTIVE = 1
} |
| |
| enum | USB_CFG0_EP4InIntStat_Enum { USB_CFG0_EP4InIntStat_INACTIVE = 0
, USB_CFG0_EP4InIntStat_ACTIVE = 1
} |
| |
| enum | USB_CFG0_EP3InIntStat_Enum { USB_CFG0_EP3InIntStat_INACTIVE = 0
, USB_CFG0_EP3InIntStat_ACTIVE = 1
} |
| |
| enum | USB_CFG0_EP2InIntStat_Enum { USB_CFG0_EP2InIntStat_INACTIVE = 0
, USB_CFG0_EP2InIntStat_ACTIVE = 1
} |
| |
| enum | USB_CFG0_EP1InIntStat_Enum { USB_CFG0_EP1InIntStat_INACTIVE = 0
, USB_CFG0_EP1InIntStat_ACTIVE = 1
} |
| |
| enum | USB_CFG0_EP0InIntStat_Enum { USB_CFG0_EP0InIntStat_INACTIVE = 0
, USB_CFG0_EP0InIntStat_ACTIVE = 1
} |
| |
| enum | USB_CFG0_ISOUpdate_Enum { USB_CFG0_ISOUpdate_DONT_WAIT = 0
, USB_CFG0_ISOUpdate_WAIT = 1
} |
| |
| enum | USB_CFG0_AMSPECIFIC_Enum { USB_CFG0_AMSPECIFIC_NOT_CONNECTED = 0
, USB_CFG0_AMSPECIFIC_CONNECTED = 1
} |
| |
| enum | USB_CFG0_HSEnab_Enum { USB_CFG0_HSEnab_DIS_HS = 0
, USB_CFG0_HSEnab_EN_HS = 1
} |
| |
| enum | USB_CFG0_HSMode_Enum { USB_CFG0_HSMode_FS_MODE = 0
, USB_CFG0_HSMode_HS_MODE = 1
} |
| |
| enum | USB_CFG0_Reset_Enum { USB_CFG0_Reset_NEG_RESET_COMPLETE = 0
, USB_CFG0_Reset_RESETTING = 1
} |
| |
| enum | USB_CFG0_Resume_Enum { USB_CFG0_Resume_END_RESUME = 0
, USB_CFG0_Resume_RESUME = 1
} |
| |
| enum | USB_CFG0_Suspen_Enum { USB_CFG0_Suspen_RESUMED = 0
, USB_CFG0_Suspen_SUSPENDED = 1
} |
| |
| enum | USB_CFG0_Enabl_Enum { USB_CFG0_Enabl_DISABLE_SUSPENDM = 0
, USB_CFG0_Enabl_ENABLE_SUSPENDM = 1
} |
| |
| enum | USB_CFG0_Update_Enum { USB_CFG0_Update_NEW_ADDR_SET = 0
, USB_CFG0_Update_NEW_ADDR_WRITTEN = 1
} |
| |
| enum | USB_CFG1_EP5InIntEn_Enum { USB_CFG1_EP5InIntEn_DIS = 0
, USB_CFG1_EP5InIntEn_EN = 1
} |
| |
| enum | USB_CFG1_EP4InIntEn_Enum { USB_CFG1_EP4InIntEn_DIS = 0
, USB_CFG1_EP4InIntEn_EN = 1
} |
| |
| enum | USB_CFG1_EP3InIntEn_Enum { USB_CFG1_EP3InIntEn_DIS = 0
, USB_CFG1_EP3InIntEn_EN = 1
} |
| |
| enum | USB_CFG1_EP2InIntEn_Enum { USB_CFG1_EP2InIntEn_DIS = 0
, USB_CFG1_EP2InIntEn_EN = 1
} |
| |
| enum | USB_CFG1_EP1InIntEn_Enum { USB_CFG1_EP1InIntEn_DIS = 0
, USB_CFG1_EP1InIntEn_EN = 1
} |
| |
| enum | USB_CFG1_EP0InIntEn_Enum { USB_CFG1_EP0InIntEn_DIS = 0
, USB_CFG1_EP0InIntEn_EN = 1
} |
| |
| enum | USB_CFG1_EP5OutIntStat_Enum { USB_CFG1_EP5OutIntStat_INACTIVE = 0
, USB_CFG1_EP5OutIntStat_ACTIVE = 1
} |
| |
| enum | USB_CFG1_EP4OutIntStat_Enum { USB_CFG1_EP4OutIntStat_INACTIVE = 0
, USB_CFG1_EP4OutIntStat_ACTIVE = 1
} |
| |
| enum | USB_CFG1_EP3OutIntStat_Enum { USB_CFG1_EP3OutIntStat_INACTIVE = 0
, USB_CFG1_EP3OutIntStat_ACTIVE = 1
} |
| |
| enum | USB_CFG1_EP2OutIntStat_Enum { USB_CFG1_EP2OutIntStat_INACTIVE = 0
, USB_CFG1_EP2OutIntStat_ACTIVE = 1
} |
| |
| enum | USB_CFG1_EP1OutIntStat_Enum { USB_CFG1_EP1OutIntStat_INACTIVE = 0
, USB_CFG1_EP1OutIntStat_ACTIVE = 1
} |
| |
| enum | USB_CFG1_EP0OutIntStat_Enum { USB_CFG1_EP0OutIntStat_INACTIVE = 0
, USB_CFG1_EP0OutIntStat_ACTIVE = 1
} |
| |
| enum | USB_CFG2_SOFE_Enum { USB_CFG2_SOFE_DIS = 0
, USB_CFG2_SOFE_EN = 1
} |
| |
| enum | USB_CFG2_ResetE_Enum { USB_CFG2_ResetE_DIS = 0
, USB_CFG2_ResetE_EN = 1
} |
| |
| enum | USB_CFG2_ResumeE_Enum { USB_CFG2_ResumeE_DIS = 0
, USB_CFG2_ResumeE_EN = 1
} |
| |
| enum | USB_CFG2_SuspendE_Enum { USB_CFG2_SuspendE_DIS = 0
, USB_CFG2_SuspendE_EN = 1
} |
| |
| enum | USB_CFG2_SOF_Enum { USB_CFG2_SOF_SOF_INACTIVE = 0
, USB_CFG2_SOF_SOF_ACTIVE = 1
} |
| |
| enum | USB_CFG2_Reset_Enum { USB_CFG2_Reset_RESET_INACTIVE = 0
, USB_CFG2_Reset_RESET_ACTIVE = 1
} |
| |
| enum | USB_CFG2_Resume_Enum { USB_CFG2_Resume_RESUME_INACTIVE = 0
, USB_CFG2_Resume_RESUME_ACTIVE = 1
} |
| |
| enum | USB_CFG2_Suspend_Enum { USB_CFG2_Suspend_SUSPEND_INACTIVE = 0
, USB_CFG2_Suspend_SUSPEND_ACTIVE = 1
} |
| |
| enum | USB_CFG2_EP5OutIntEn_Enum { USB_CFG2_EP5OutIntEn_DIS = 0
, USB_CFG2_EP5OutIntEn_EN = 1
} |
| |
| enum | USB_CFG2_EP4OutIntEn_Enum { USB_CFG2_EP4OutIntEn_DIS = 0
, USB_CFG2_EP4OutIntEn_EN = 1
} |
| |
| enum | USB_CFG2_EP3OutIntEn_Enum { USB_CFG2_EP3OutIntEn_DIS = 0
, USB_CFG2_EP3OutIntEn_EN = 1
} |
| |
| enum | USB_CFG2_EP2OutIntEn_Enum { USB_CFG2_EP2OutIntEn_DIS = 0
, USB_CFG2_EP2OutIntEn_EN = 1
} |
| |
| enum | USB_CFG2_EP1OutIntEn_Enum { USB_CFG2_EP1OutIntEn_DIS = 0
, USB_CFG2_EP1OutIntEn_EN = 1
} |
| |
| enum | USB_CFG2_EP0OutIntEn_Enum { USB_CFG2_EP0OutIntEn_DIS = 0
, USB_CFG2_EP0OutIntEn_EN = 1
} |
| |
| enum | USB_CFG3_ForceFS_Enum { USB_CFG3_ForceFS_FS_NOT_FORCED = 0
, USB_CFG3_ForceFS_FS_FORCED = 1
} |
| |
| enum | USB_CFG3_ForceHS_Enum { USB_CFG3_ForceHS_HS_NOT_FORCED = 0
, USB_CFG3_ForceHS_HS_FORCED = 1
} |
| |
| enum | USB_CFG3_TestPacket_Enum { USB_CFG3_TestPacket_STOP_TPTM = 0
, USB_CFG3_TestPacket_START_TPTM = 1
} |
| |
| enum | USB_CFG3_TestK_Enum { USB_CFG3_TestK_STOP_TESTK = 0
, USB_CFG3_TestK_START_TESTK = 1
} |
| |
| enum | USB_CFG3_TestJ_Enum { USB_CFG3_TestJ_STOP_TESTJ = 0
, USB_CFG3_TestJ_START_TESTJ = 1
} |
| |
| enum | USB_CFG3_TestSE0NAK_Enum { USB_CFG3_TestSE0NAK_STOP_TESTSE0NAK = 0
, USB_CFG3_TestSE0NAK_START_TESTSE0NAK = 1
} |
| |
| enum | USB_CFG3_ENDPOINT_Enum {
USB_CFG3_ENDPOINT_ENDPOINT0 = 0
, USB_CFG3_ENDPOINT_ENDPOINT1 = 1
, USB_CFG3_ENDPOINT_ENDPOINT2 = 2
, USB_CFG3_ENDPOINT_ENDPOINT3 = 3
,
USB_CFG3_ENDPOINT_ENDPOINT4 = 4
, USB_CFG3_ENDPOINT_ENDPOINT5 = 5
} |
| |
| enum | USB_IDX0_AutoSet_Enum { USB_IDX0_AutoSet_NO_AUTOSET = 0
, USB_IDX0_AutoSet_AUTOSET = 1
} |
| |
| enum | USB_IDX0_ISO_Enum { USB_IDX0_ISO_BULK_INT = 0
, USB_IDX0_ISO_ISO = 1
} |
| |
| enum | USB_IDX0_Mode_Enum { USB_IDX0_Mode_OUT = 0
, USB_IDX0_Mode_IN = 1
} |
| |
| enum | USB_IDX0_FrcDataTog_Enum { USB_IDX0_FrcDataTog_NO_FORCE_TOGGLE = 0
, USB_IDX0_FrcDataTog_FORCE_TOGGLE = 1
} |
| |
| enum | USB_IDX0_DPktBufDis_Enum { USB_IDX0_DPktBufDis_EN_DPB = 0
, USB_IDX0_DPktBufDis_DIS_DPB = 1
} |
| |
| enum | USB_IDX0_IncompTxServiceSetupEnd_Enum { USB_IDX0_IncompTxServiceSetupEnd_NO_PACKET_SPLIT = 0
, USB_IDX0_IncompTxServiceSetupEnd_PACKET_SPLIT = 1
} |
| |
| enum | USB_IDX1_AutoClear_Enum { USB_IDX1_AutoClear_NO_AUTOCLR = 0
, USB_IDX1_AutoClear_AUTOCLR = 1
} |
| |
| enum | USB_IDX1_ISO_Enum { USB_IDX1_ISO_BULK_INT = 0
, USB_IDX1_ISO_ISO = 1
} |
| |
| enum | USB_IDX1_DPktBufDis_Enum { USB_IDX1_DPktBufDis_EN_DPB = 0
, USB_IDX1_DPktBufDis_DIS_DPB = 1
} |
| |
| enum | USB_CLKCTRL_PHYREFCLKSEL_Enum { USB_CLKCTRL_PHYREFCLKSEL_HFRC48 = 0
, USB_CLKCTRL_PHYREFCLKSEL_HFRC248 = 1
, USB_CLKCTRL_PHYREFCLKSEL_HFRC24 = 2
} |
| |
| enum | USB_SRAMCTRL_RAWLM_Enum { USB_SRAMCTRL_RAWLM_INCDLY = 3
, USB_SRAMCTRL_RAWLM_MBINCDLY = 2
, USB_SRAMCTRL_RAWLM_IMNB = 1
, USB_SRAMCTRL_RAWLM_MMNB = 0
} |
| |
| enum | USB_UTMISTICKYSTATUS_obsportstciky_Enum { USB_UTMISTICKYSTATUS_obsportstciky_OBS3 = 3
, USB_UTMISTICKYSTATUS_obsportstciky_OBS2 = 2
, USB_UTMISTICKYSTATUS_obsportstciky_OBS1 = 1
, USB_UTMISTICKYSTATUS_obsportstciky_OBS0 = 0
} |
| |
| enum | USB_BCDETCRTL1_USBDCOMPREF_Enum { USB_BCDETCRTL1_USBDCOMPREF_1P25V = 3
, USB_BCDETCRTL1_USBDCOMPREF_2P35 = 2
, USB_BCDETCRTL1_USBDCOMPREF_3P10V = 1
, USB_BCDETCRTL1_USBDCOMPREF_1P65 = 0
} |
| |
| enum | VCOMP_CFG_LVLSEL_Enum {
VCOMP_CFG_LVLSEL_0P58V = 0
, VCOMP_CFG_LVLSEL_0P77V = 1
, VCOMP_CFG_LVLSEL_0P97V = 2
, VCOMP_CFG_LVLSEL_1P16V = 3
,
VCOMP_CFG_LVLSEL_1P35V = 4
, VCOMP_CFG_LVLSEL_1P55V = 5
, VCOMP_CFG_LVLSEL_1P74V = 6
, VCOMP_CFG_LVLSEL_1P93V = 7
,
VCOMP_CFG_LVLSEL_2P13V = 8
, VCOMP_CFG_LVLSEL_2P32V = 9
, VCOMP_CFG_LVLSEL_2P51V = 10
, VCOMP_CFG_LVLSEL_2P71V = 11
,
VCOMP_CFG_LVLSEL_2P90V = 12
, VCOMP_CFG_LVLSEL_3P09V = 13
, VCOMP_CFG_LVLSEL_3P29V = 14
, VCOMP_CFG_LVLSEL_3P48V = 15
} |
| |
| enum | VCOMP_CFG_NSEL_Enum { VCOMP_CFG_NSEL_VREFEXT1 = 0
, VCOMP_CFG_NSEL_VREFEXT2 = 1
, VCOMP_CFG_NSEL_VREFEXT3 = 2
, VCOMP_CFG_NSEL_DAC = 3
} |
| |
| enum | VCOMP_CFG_PSEL_Enum { VCOMP_CFG_PSEL_VDDADJ = 0
, VCOMP_CFG_PSEL_VTEMP = 1
, VCOMP_CFG_PSEL_VEXT1 = 2
, VCOMP_CFG_PSEL_VEXT2 = 3
} |
| |
| enum | VCOMP_STAT_PWDSTAT_Enum { VCOMP_STAT_PWDSTAT_POWERED_DOWN = 1
, VCOMP_STAT_PWDSTAT_POWERED_UP = 0
} |
| |
| enum | VCOMP_STAT_CMPOUT_Enum { VCOMP_STAT_CMPOUT_VOUT_LOW = 0
, VCOMP_STAT_CMPOUT_VOUT_HIGH = 1
} |
| |
| enum | VCOMP_PWDKEY_PWDKEY_Enum { VCOMP_PWDKEY_PWDKEY_Key = 55
} |
| |
| enum | WDT_CFG_CLKSEL_Enum {
WDT_CFG_CLKSEL_OFF = 0
, WDT_CFG_CLKSEL_128HZ = 1
, WDT_CFG_CLKSEL_16HZ = 2
, WDT_CFG_CLKSEL_1HZ = 3
,
WDT_CFG_CLKSEL_1_16HZ = 4
} |
| |
| enum | WDT_RSTRT_RSTRT_Enum { WDT_RSTRT_RSTRT_KEYVALUE = 178
, WDT_RSTRT_RSTRT_DEFAULT = 0
} |
| |
| enum | WDT_LOCK_LOCK_Enum { WDT_LOCK_LOCK_KEYVALUE = 58
, WDT_LOCK_LOCK_DEFAULT = 0
} |
| |
| enum | WDT_DSP0RSTRT_DSP0RSTART_Enum { WDT_DSP0RSTRT_DSP0RSTART_KEYVALUE = 105
, WDT_DSP0RSTRT_DSP0RSTART_DEFAULT = 0
} |
| |
| enum | WDT_DSP0TLOCK_DSP0LOCK_Enum { WDT_DSP0TLOCK_DSP0LOCK_KEYVALUE = 167
, WDT_DSP0TLOCK_DSP0LOCK_DEFAULT = 0
} |
| |
| enum | WDT_DSP1RSTRT_DSP1RSTART_Enum { WDT_DSP1RSTRT_DSP1RSTART_KEYVALUE = 210
, WDT_DSP1RSTRT_DSP1RSTART_DEFAULT = 0
} |
| |
| enum | WDT_DSP1TLOCK_DSP1LOCK_Enum { WDT_DSP1TLOCK_DSP1LOCK_KEYVALUE = 78
, WDT_DSP1TLOCK_DSP1LOCK_DEFAULT = 0
} |
| |
1.9.2